// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.1.110.3.16
// IP Version: 6.4
// =============================================================================

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//                                                                       
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//                                                                       
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.                                                
//
////////////////////////////////////////////////////////////////////////////////

`define IP_UUID _4baff3c4bcd643d4ace07f79d93bbfaa
`define IP_NAME_CONCAT(a,b) a``b
`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
module efx_tsemac
(
    input mac_reset,
    input proto_reset,
    input [9:0] s_axi_araddr,
    output [1:0] s_axi_rresp,
    output rx_mac_aclk,
    input tx_mac_aclk,
    output [2:0] eth_speed,
    output MdoEn,
    input rx_axis_clk,
    output rx_axis_mac_tuser,
    output Mdc,
    output rx_axis_mac_tlast,
    input Mdi,
    output rx_axis_mac_tvalid,
    output s_axi_rvalid,
    output s_axi_arready,
    input rx_axis_mac_tready,
    output [31:0] s_axi_rdata,
    input tx_axis_clk,
    input tx_axis_mac_tvalid,
    output s_axi_bvalid,
    output s_axi_wready,
    input s_axi_rready,
    input tx_axis_mac_tlast,
    output Mdo,
    input tx_axis_mac_tuser,
    input [31:0] s_axi_wdata,
    output tx_axis_mac_tready,
    output [3:0] rgmii_txd_HI,
    output [3:0] rgmii_txd_LO,
    output rgmii_tx_ctl_HI,
    output rgmii_tx_ctl_LO,
    output rgmii_txc_HI,
    output rgmii_txc_LO,
    input [3:0] rgmii_rxd_HI,
    input [3:0] rgmii_rxd_LO,
    input rgmii_rx_ctl_HI,
    input rgmii_rx_ctl_LO,
    input rgmii_rxc,
    input s_axi_aclk,
    input s_axi_bready,
    input [9:0] s_axi_awaddr,
    input s_axi_arvalid,
    input s_axi_awvalid,
    output s_axi_awready,
    input s_axi_wvalid,
    output [7:0] rx_axis_mac_tdata,
    input [7:0] tx_axis_mac_tdata,
    input [0:0] tx_axis_mac_tstrb,
    output [0:0] rx_axis_mac_tstrb,
    output [1:0] s_axi_bresp
);
`IP_MODULE_NAME(tsemac)
#(
    .VERSION (16),
    .TXFIFO_EN (1'b1),
    .RXFIFO_EN (1'b1),
    .TXFIFO_DTH (4096),
    .RXFIFO_DTH (4096),
    .PHY_INTF_MODE (0),
    .AXIS_DW (8),
    .RGMII_RXC_EDGE (1'b1),
    .RGMII_TXC_DLY (1'b1)
)
u_tsemac
(
    .mac_reset ( mac_reset ),
    .proto_reset ( proto_reset ),
    .s_axi_araddr ( s_axi_araddr ),
    .s_axi_rresp ( s_axi_rresp ),
    .rx_mac_aclk ( rx_mac_aclk ),
    .tx_mac_aclk ( tx_mac_aclk ),
    .eth_speed ( eth_speed ),
    .MdoEn ( MdoEn ),
    .rx_axis_clk ( rx_axis_clk ),
    .rx_axis_mac_tuser ( rx_axis_mac_tuser ),
    .Mdc ( Mdc ),
    .rx_axis_mac_tlast ( rx_axis_mac_tlast ),
    .Mdi ( Mdi ),
    .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ),
    .s_axi_rvalid ( s_axi_rvalid ),
    .s_axi_arready ( s_axi_arready ),
    .rx_axis_mac_tready ( rx_axis_mac_tready ),
    .s_axi_rdata ( s_axi_rdata ),
    .tx_axis_clk ( tx_axis_clk ),
    .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ),
    .s_axi_bvalid ( s_axi_bvalid ),
    .s_axi_wready ( s_axi_wready ),
    .s_axi_rready ( s_axi_rready ),
    .tx_axis_mac_tlast ( tx_axis_mac_tlast ),
    .Mdo ( Mdo ),
    .tx_axis_mac_tuser ( tx_axis_mac_tuser ),
    .s_axi_wdata ( s_axi_wdata ),
    .tx_axis_mac_tready ( tx_axis_mac_tready ),
    .rgmii_txd_HI ( rgmii_txd_HI ),
    .rgmii_txd_LO ( rgmii_txd_LO ),
    .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ),
    .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ),
    .rgmii_txc_HI ( rgmii_txc_HI ),
    .rgmii_txc_LO ( rgmii_txc_LO ),
    .rgmii_rxd_HI ( rgmii_rxd_HI ),
    .rgmii_rxd_LO ( rgmii_rxd_LO ),
    .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ),
    .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ),
    .rgmii_rxc ( rgmii_rxc ),
    .s_axi_aclk ( s_axi_aclk ),
    .s_axi_bready ( s_axi_bready ),
    .s_axi_awaddr ( s_axi_awaddr ),
    .s_axi_arvalid ( s_axi_arvalid ),
    .s_axi_awvalid ( s_axi_awvalid ),
    .s_axi_awready ( s_axi_awready ),
    .s_axi_wvalid ( s_axi_wvalid ),
    .rx_axis_mac_tdata ( rx_axis_mac_tdata ),
    .tx_axis_mac_tdata ( tx_axis_mac_tdata ),
    .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ),
    .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ),
    .s_axi_bresp ( s_axi_bresp )
);
endmodule

/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_top) # (
    parameter FAMILY             = "TRION",       // New Param
    parameter SYNC_CLK           = 0,
    parameter BYPASS_RESET_SYNC  = 0,             // New Param
    parameter SYNC_STAGE         = 2,             // New Param
    parameter MODE               = "STANDARD",
    parameter DEPTH              = 512,           // Reverted (Equivalent to WDATA_DEPTH) 
    parameter DATA_WIDTH         = 32,            // Reverted (Equivalent to WDATA_WIDTH)
    parameter PIPELINE_REG       = 1,             // Reverted (By default is ON)
    parameter OPTIONAL_FLAGS     = 1,             // Reverted
    parameter OUTPUT_REG         = 0,
    parameter PROGRAMMABLE_FULL  = "STATIC_DUAL", // Set to "NONE" if not require this feature
    parameter PROG_FULL_ASSERT   = 27,
    parameter PROG_FULL_NEGATE   = 23,
    parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature
    parameter PROG_EMPTY_ASSERT  = 5,
    parameter PROG_EMPTY_NEGATE  = 7,
    parameter ALMOST_FLAG        = OPTIONAL_FLAGS,
    parameter HANDSHAKE_FLAG     = OPTIONAL_FLAGS,
    parameter ASYM_WIDTH_RATIO   = 4,
    parameter WADDR_WIDTH        = depth2width(DEPTH),
    parameter RDATA_WIDTH        = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH),
    parameter RD_DEPTH           = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH),
    parameter RADDR_WIDTH        = depth2width(RD_DEPTH),
    parameter ENDIANESS		      = 0,
    parameter OVERFLOW_PROTECT   = 1,
    parameter UNDERFLOW_PROTECT  = 1,
    parameter RAM_STYLE          = "block_ram"

)(
    input  wire                   a_rst_i,
    input  wire                   a_wr_rst_i,
    input  wire                   a_rd_rst_i,
    input  wire                   clk_i,
    input  wire                   wr_clk_i,
    input  wire                   rd_clk_i,
    input  wire                   wr_en_i,
    input  wire                   rd_en_i,
    input  wire [DATA_WIDTH-1:0]  wdata,
    output wire                   almost_full_o,
    output wire                   prog_full_o,
    output wire                   full_o,
    output wire                   overflow_o,
    output wire                   wr_ack_o,
    output wire [WADDR_WIDTH :0]  datacount_o,
    output wire [WADDR_WIDTH :0]  wr_datacount_o,
    output wire                   empty_o,
    output wire                   almost_empty_o,
    output wire                   prog_empty_o,
    output wire                   underflow_o,
    output wire                   rd_valid_o,
    output wire [RDATA_WIDTH-1:0] rdata,
    output wire [RADDR_WIDTH :0]  rd_datacount_o,
    output wire                   rst_busy
); 

localparam WR_DEPTH      = DEPTH;
localparam WDATA_WIDTH   = DATA_WIDTH;
localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 :
                           (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 :
                           (RDATA_WIDTH <= WDATA_WIDTH/8)  ? 8  :
                           (RDATA_WIDTH <= WDATA_WIDTH/4)  ? 4  :
                           (RDATA_WIDTH <= WDATA_WIDTH/2)  ? 2  :
                           (RDATA_WIDTH <= WDATA_WIDTH)    ? 1  :
                           (RDATA_WIDTH <= WDATA_WIDTH*2)  ? 2  :
                           (RDATA_WIDTH <= WDATA_WIDTH*4)  ? 4  :
                           (RDATA_WIDTH <= WDATA_WIDTH*8)  ? 8  :
                           (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32;           

wire                   wr_rst_int;
wire                   rd_rst_int;
wire                   wr_en_int;
wire                   rd_en_int;
wire [WADDR_WIDTH-1:0] waddr;
wire [RADDR_WIDTH-1:0] raddr;
wire                   wr_clk_int;
wire                   rd_clk_int;
wire [WADDR_WIDTH :0]  wr_datacount_int;
wire [RADDR_WIDTH :0]  rd_datacount_int;

generate
    if (ASYM_WIDTH_RATIO == 4) begin
        if (SYNC_CLK) begin
            assign wr_clk_int     = clk_i;    
            assign rd_clk_int     = clk_i;
            assign datacount_o    = wr_datacount_int;
            assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}};
            assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}};
        end
        else begin
            assign wr_clk_int     = wr_clk_i;    
            assign rd_clk_int     = rd_clk_i;
            assign datacount_o    = {(WADDR_WIDTH+1){1'b0}};
            assign wr_datacount_o = wr_datacount_int;
            assign rd_datacount_o = rd_datacount_int;
        end
    end
    else begin
        assign datacount_o    = {(WADDR_WIDTH+1){1'b0}};
        assign wr_datacount_o = wr_datacount_int;
        assign rd_datacount_o = rd_datacount_int;
        if (SYNC_CLK) begin
            assign wr_clk_int     = clk_i;    
            assign rd_clk_int     = clk_i;
        end
        else begin
            assign wr_clk_int     = wr_clk_i;    
            assign rd_clk_int     = rd_clk_i;
        end
    end    

    if (!SYNC_CLK) begin
        //(* async_reg = "true" *) reg [1:0] wr_rst;
        //(* async_reg = "true" *) reg [1:0] rd_rst;
        //
        //always @ (posedge wr_clk_int or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        wr_rst <= 2'b11;
        //    else 
        //        wr_rst <= {wr_rst[0],1'b0};            
        //end
        //
        //always @ (posedge rd_clk_int or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        rd_rst <= 2'b11;
        //    else 
        //        rd_rst <= {rd_rst[0],1'b0};            
        //end
        

        if (BYPASS_RESET_SYNC) begin
            assign wr_rst_int = a_wr_rst_i;
            assign rd_rst_int = a_rd_rst_i; 
            assign rst_busy   = 1'b0;
        end 
        else begin
            `IP_MODULE_NAME(efx_resetsync) #(
               .ACTIVE_LOW (0)
            ) efx_resetsync_wr_rst (
               .clk   (wr_clk_int),
               .reset (a_rst_i),
               .d_o   (wr_rst_int)
            );

            `IP_MODULE_NAME(efx_resetsync) #(
               .ACTIVE_LOW (0)
            ) efx_resetsync_rd_rst (
               .clk   (rd_clk_int),
               .reset (a_rst_i),
               .d_o   (rd_rst_int)
            );
            assign rst_busy   = wr_rst_int | rd_rst_int;
        end

    end
    else begin
        //(* async_reg = "true" *) reg [1:0] a_rst;
        //
        //always @ (posedge clk_i or posedge a_rst_i) begin
        //    if (a_rst_i) 
        //        a_rst <= 2'b11;
        //    else 
        //        a_rst <= {a_rst[0],1'b0};            
        //end
        wire   a_rst;

        `IP_MODULE_NAME(efx_resetsync) #(
           .ACTIVE_LOW (0)
        ) efx_resetsync_a_rst (
           .clk   (clk_i),
           .reset (a_rst_i),
           .d_o   (a_rst)
        );

        if (BYPASS_RESET_SYNC) begin
            assign wr_rst_int = a_rst_i;
            assign rd_rst_int = a_rst_i;
            assign rst_busy   = 1'b0;
        end
        else begin
            assign wr_rst_int = a_rst;
            assign rd_rst_int = a_rst;   
            assign rst_busy   = wr_rst_int | rd_rst_int;
        end
    end 
endgenerate

`IP_MODULE_NAME(efx_fifo_ram) # (
    .FAMILY        (FAMILY),
    .WR_DEPTH      (WR_DEPTH),
    .RD_DEPTH      (RD_DEPTH),
    .WDATA_WIDTH   (WDATA_WIDTH),
    .RDATA_WIDTH   (RDATA_WIDTH),
    .WADDR_WIDTH   (WADDR_WIDTH),
    .RADDR_WIDTH   (RADDR_WIDTH),
    .OUTPUT_REG    (OUTPUT_REG),
    .RAM_MUX_RATIO (RAM_MUX_RATIO),
    .ENDIANESS	    (ENDIANESS),
    .RAM_STYLE     (RAM_STYLE)
) xefx_fifo_ram (
    .wdata (wdata), 
    .waddr (waddr),
    .raddr (raddr), 
    .we    (wr_en_int), 
    .re    (rd_en_int),
    .wclk  (wr_clk_int),
    .rclk  (rd_clk_int),
    .rdata (rdata)
);

`IP_MODULE_NAME(efx_fifo_ctl) # (
    .SYNC_CLK           (SYNC_CLK),
    .SYNC_STAGE         (SYNC_STAGE),
    .MODE               (MODE),
    .WR_DEPTH           (WR_DEPTH),
    .WADDR_WIDTH        (WADDR_WIDTH),
    .RADDR_WIDTH        (RADDR_WIDTH),
    .ASYM_WIDTH_RATIO   (ASYM_WIDTH_RATIO),
    .RAM_MUX_RATIO      (RAM_MUX_RATIO),
    .PIPELINE_REG       (PIPELINE_REG),
    .ALMOST_FLAG        (ALMOST_FLAG),
    .PROGRAMMABLE_FULL  (PROGRAMMABLE_FULL),
    .PROG_FULL_ASSERT   (PROG_FULL_ASSERT),
    .PROG_FULL_NEGATE   (PROG_FULL_NEGATE),
    .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY),
    .PROG_EMPTY_ASSERT  (PROG_EMPTY_ASSERT),
    .PROG_EMPTY_NEGATE  (PROG_EMPTY_NEGATE),
    .OUTPUT_REG         (OUTPUT_REG),
    .HANDSHAKE_FLAG     (HANDSHAKE_FLAG),
    .OVERFLOW_PROTECT   (OVERFLOW_PROTECT),
    .UNDERFLOW_PROTECT  (UNDERFLOW_PROTECT)
) xefx_fifo_ctl (
    .wr_rst          (wr_rst_int),
    .rd_rst          (rd_rst_int),
    .wclk            (wr_clk_int),
    .rclk            (rd_clk_int),
    .we              (wr_en_i),
    .re              (rd_en_i),
    .wr_full         (full_o),
    .wr_ack          (wr_ack_o),
    .rd_empty        (empty_o),
    .wr_almost_full  (almost_full_o),
    .rd_almost_empty (almost_empty_o),
    .wr_prog_full    (prog_full_o),
    .rd_prog_empty   (prog_empty_o),
    .wr_en_int       (wr_en_int),
    .rd_en_int       (rd_en_int),
    .waddr           (waddr),
    .raddr           (raddr),
    .wr_datacount    (wr_datacount_int),
    .rd_datacount    (rd_datacount_int),
    .rd_vld          (rd_valid_o),
    .wr_overflow     (overflow_o),
    .rd_underflow    (underflow_o)
);

function integer depth2width;
input [31:0] depth;
begin : fnDepth2Width
    if (depth > 1) begin
        depth = depth - 1;
        for (depth2width=0; depth>0; depth2width = depth2width + 1)
            depth = depth>>1;
        end
    else
       depth2width = 0;
end
endfunction 

function integer width2depth;
input [31:0] width;
begin : fnWidth2Depth
    width2depth = width**2;
end
endfunction

function integer rdwidthcompute;
input [31:0] asym_option;
input [31:0] wr_width;
begin : RdWidthCompute
    rdwidthcompute = (asym_option==0)? wr_width/16 :
                     (asym_option==1)? wr_width/8  :
                     (asym_option==2)? wr_width/4  :
                     (asym_option==3)? wr_width/2  :
                     (asym_option==4)? wr_width/1  :
                     (asym_option==5)? wr_width*2  :
                     (asym_option==6)? wr_width*4  :
                     (asym_option==7)? wr_width*8  :
                     (asym_option==8)? wr_width*16 : wr_width/1;
end
endfunction

function integer rddepthcompute;
input [31:0] wr_depth;
input [31:0] wr_width;
input [31:0] rd_width;
begin : RdDepthCompute
    rddepthcompute = (wr_depth * wr_width) / rd_width;
end
endfunction

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_ram) #(
    parameter FAMILY        = "TRION",
    parameter WR_DEPTH      = 512,
    parameter RD_DEPTH      = 512,
    parameter WDATA_WIDTH   = 8,
    parameter RDATA_WIDTH   = 8,
    parameter WADDR_WIDTH   = 9,
    parameter RADDR_WIDTH   = 9,
    parameter OUTPUT_REG    = 1,
    parameter RAM_MUX_RATIO = 4,
    parameter ENDIANESS 	 = 0, //0: Big endian (default)   1: Little endian 
    parameter RAM_STYLE     = "block_ram"
) (
    input  wire                     wclk,
    input  wire                     rclk,
    input  wire                     we,
    input  wire                     re,
    input  wire [(WDATA_WIDTH-1):0] wdata,
    input  wire [(WADDR_WIDTH-1):0] waddr,
    input  wire [(RADDR_WIDTH-1):0] raddr,
    output wire [(RDATA_WIDTH-1):0] rdata
);

localparam MEM_DEPTH         = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH;
localparam MEM_DATA_WIDTH    = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH;   
localparam LSB_WIDTH         = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH);
localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" :
                               (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" :
                               (RDATA_WIDTH <= WDATA_WIDTH/8)  ? "ONE_EIGHTH"    :
                               (RDATA_WIDTH <= WDATA_WIDTH/4)  ? "ONE_FOURTH"    :
                               (RDATA_WIDTH <= WDATA_WIDTH/2)  ? "ONE_HALF"      :
                               (RDATA_WIDTH <= WDATA_WIDTH)    ? "ONE"           :
                               (RDATA_WIDTH <= WDATA_WIDTH*2)  ? "TWO_TIMES"     :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "FOUR_TIMES"    :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "EIGHT_TIMES"   :
                               (RDATA_WIDTH <= WDATA_WIDTH*4)  ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES";

(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0];
reg [RDATA_WIDTH-1:0]    r_rdata_1P;
reg [RDATA_WIDTH-1:0]    r_rdata_2P;

wire                     re_int;

generate
    if (FAMILY == "TRION") begin
        if (RDATA_WDATA_RATIO == "ONE") begin
            always @ (posedge wclk) begin
                if (we)
                    ram[waddr] <= wdata;
            end
    
            always @ (posedge rclk) begin
                if (re_int) begin
                    r_rdata_1P <= ram[raddr];
                end
                r_rdata_2P <= r_rdata_1P;
            end
        end
        
        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
            if (ENDIANESS == 0) begin 
            	integer i;
            	always @ (posedge wclk) begin
                	for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            ram[{waddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                end
                always @ (posedge rclk) begin 
                	if (re_int) begin
                		r_rdata_1P <= ram[raddr];
                    end
                		r_rdata_2P <= r_rdata_1P;
                end
            end
            else begin //endianess == 1
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            ram[{waddr,LSB_WIDTH'(i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                end
                always @ (posedge rclk) begin 
                	if (re_int) begin
                		r_rdata_1P <= ram[raddr];
                	end
                		r_rdata_2P <= r_rdata_1P;
                end
            end
        end
        
        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  ||RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
            //integer i;
        	if (ENDIANESS == 0) begin
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
        		always @ (posedge rclk) begin
        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}];
                    	end
                        	r_rdata_2P <= r_rdata_1P;
                    end
                end 
            end
            else begin //endianess == 1
            	always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
        		always @ (posedge rclk) begin
        			for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(i)}];
                    	end
                        	r_rdata_2P <= r_rdata_1P;
                    end
                end
            end
        end
        if (OUTPUT_REG) begin
            assign re_int = re;
            assign rdata  = r_rdata_2P;            
        end
        else begin
            assign re_int = re;
            assign rdata  = r_rdata_1P;
        end
    end
    else begin
        if (RDATA_WDATA_RATIO == "ONE") begin
            always @ (posedge wclk) begin
                if (we)
                    ram[waddr] <= wdata;
            end
    
            always @ (posedge rclk) begin
                if (re_int) begin
                    r_rdata_1P <= ram[raddr];
                    r_rdata_2P <= r_rdata_1P;
                end
            end
        end 
        else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH"  || RDATA_WDATA_RATIO == "ONE_HALF" ) begin
            //integer i;
            if (ENDIANESS == 0) begin
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            	ram[{waddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                 end
               	always @ (posedge rclk) begin 
               		if (re_int) begin
               			r_rdata_1P <= ram[raddr];
               			r_rdata_2P <= r_rdata_1P;
               		end
               	end
            end
            
            else begin //endianess == 1
            	integer i;
            	always @ (posedge wclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (we) begin
                            	ram[{waddr,LSB_WIDTH'(i)}] <= wdata[((WDATA_WIDTH/RAM_MUX_RATIO)*i) +: WDATA_WIDTH/RAM_MUX_RATIO];
                        end
                    end
                 end
               	always @ (posedge rclk) begin 
               		if (re_int) begin
               			r_rdata_1P <= ram[raddr];
               			r_rdata_2P <= r_rdata_1P;
               		end
               	end
            end
        end
        else if (RDATA_WDATA_RATIO == "TWO_TIMES" || RDATA_WDATA_RATIO == "FOUR_TIMES"  || RDATA_WDATA_RATIO == "EIGHT_TIMES"  || RDATA_WDATA_RATIO == "SIXTEEN_TIMES"  || RDATA_WDATA_RATIO == "THIRTYTWO_TIMES" ) begin
        	//integer i;
        	if (ENDIANESS == 0) begin
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
            	always @ (posedge rclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(RAM_MUX_RATIO-1-i)}];
                    		r_rdata_2P                                                               <= r_rdata_1P;
                    	end
                    end
                end 
            end
            
            else begin //endianess ==1
        		always @ (posedge wclk) begin
        			if (we)
        				ram[waddr] <= wdata;
        		end
        		integer i;
            	always @ (posedge rclk) begin
            		for (i=0; i<RAM_MUX_RATIO; i=i+1) begin
                    	if (re_int) begin
                    		r_rdata_1P[((RDATA_WIDTH/RAM_MUX_RATIO)*i) +: RDATA_WIDTH/RAM_MUX_RATIO] <= ram[{raddr,LSB_WIDTH'(i)}];
                    		r_rdata_2P                                                               <= r_rdata_1P;
                    	end
                    end
                end 
            end
        end
        // NIC
        //if (MODE == "STANDARD") begin     
        //    if (OUTPUT_REG) begin
        //        reg re_r;
        //        always @ (posedge rclk) begin
        //            re_r <= re;
        //        end
        //        assign re_int = re | re_r;        
        //        assign rdata  = r_rdata_2P;            
        //    end
        //    else begin
        //        assign re_int = re;
        //        assign rdata  = r_rdata_1P;
        //    end
        //end
        //else begin
        //    assign re_int = re;
        //    assign rdata  = r_rdata_1P;
        //end    
        if (OUTPUT_REG) begin
            reg re_r;
            always @ (posedge rclk) begin
                re_r <= re;
            end
            assign re_int = re | re_r;        
            assign rdata  = r_rdata_2P;            
        end
        else begin
            assign re_int = re;
            assign rdata  = r_rdata_1P;
        end    
    end
endgenerate

endmodule

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   gray2bin.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Gray to Binary Encoding Convertor
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

`resetall
`timescale 1ns/1ps

module `IP_MODULE_NAME(efx_fifo_gray2bin)
#(parameter WIDTH=5)
(// outputs
 output wire [WIDTH-1:0] bin_o,
 // input
 input [WIDTH-1:0] gray_i);

//---------------------------------------------------------------------
// Recursive Module
// Description: reduction xor
generate
   if (WIDTH > 1) begin
      wire [1:0] bin_1;
      assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]};
      if (WIDTH == 2) begin
	 assign bin_o = bin_1;
      end
      else begin
	 assign bin_o[WIDTH-1] = bin_1[1];
	 `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]}));
      end
   end
   else /* if (WIDTH == 1) */
     assign bin_o = gray_i;
endgenerate
   
endmodule 

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   pipe_reg.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Parallel Pipelining Shift Register
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_datasync) #(
    parameter STAGE = 32,
    parameter WIDTH = 4
) (
 input  wire             clk_i,
 input  wire [WIDTH-1:0] d_i,
 output wire [WIDTH-1:0] d_o
);

(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0];
integer i;

always @(posedge clk_i) begin
  for (i=STAGE-1; i>0; i = i - 1) begin
    pipe_reg[i] <= pipe_reg[i-1];
  end
  pipe_reg[0] <= d_i;
end
assign d_o = pipe_reg[STAGE-1];
   

endmodule

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////



// synopsys translate_off
`timescale 1 ns / 1 ps													
// synopsys translate_on

module `IP_MODULE_NAME(efx_resetsync) #(
    parameter ASYNC_STAGE = 2,
    parameter ACTIVE_LOW = 1
) (
    input  wire             clk,
    input  wire             reset,
    output wire             d_o
);


generate
   if (ACTIVE_LOW == 1) begin: active_low
      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH      (1),
         .ACTIVE_LOW (1),
         .RST_VALUE  (0)
      ) efx_resetsync_active_low (
         .clk     (clk),
         .reset_n (reset),
         .d_i     (1'b1),
         .d_o     (d_o)
      );
   end
   else begin: active_high
      `IP_MODULE_NAME(efx_asyncreg) #(
         .WIDTH      (1),
         .ACTIVE_LOW (0),
         .RST_VALUE  (1)
      ) efx_resetsync_active_high (
         .clk     (clk),
         .reset_n (reset),
         .d_i     (1'b0),
         .d_o     (d_o)
      );
   end
endgenerate

endmodule



// synopsys translate_off
`timescale 1 ns / 1 ps													
// synopsys translate_on

module `IP_MODULE_NAME(efx_asyncreg) #(
    parameter ASYNC_STAGE = 2,
    parameter WIDTH = 4,
    parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset
    parameter RST_VALUE = 0 
) (
    input  wire             clk,
    input  wire             reset_n,
    input  wire [WIDTH-1:0] d_i,
    output wire [WIDTH-1:0] d_o
);

(* async_reg = "true" *) reg [WIDTH-1:0] async_reg[ASYNC_STAGE-1:0];

assign d_o = async_reg[ASYNC_STAGE-1];

genvar i;
generate
   if (ACTIVE_LOW == 1) begin: active_low
      if (RST_VALUE == 0) begin: low_reset_0
         always @ (posedge clk or negedge reset_n) begin
             if(!reset_n) begin
                 async_reg[0]         <= {WIDTH{1'b0}};
             end
             else begin 
                 async_reg[0]         <= d_i;
             end
         end
             
         for (i=1; i<ASYNC_STAGE; i=i+1) begin
             always @ (posedge clk or negedge reset_n) begin
                 if(!reset_n) begin
                     async_reg[i]         <= {WIDTH{1'b0}};
                 end
                 else begin 
                     async_reg[i]         <= async_reg[i-1];
                 end
             end
         end
      end
      else begin: low_reset_1
         always @ (posedge clk or negedge reset_n) begin
             if(!reset_n) begin
                 async_reg[0]         <= {WIDTH{1'b1}};
             end
             else begin 
                 async_reg[0]         <= d_i;
             end
         end
             
         for (i=1; i<ASYNC_STAGE; i=i+1) begin
             always @ (posedge clk or negedge reset_n) begin
                 if(!reset_n) begin
                     async_reg[i]         <= {WIDTH{1'b1}};
                 end
                 else begin 
                     async_reg[i]         <= async_reg[i-1];
                 end
             end
         end
      end
   end
   else begin: active_high
      if (RST_VALUE == 0) begin: high_reset_0
         always @ (posedge clk or posedge reset_n) begin
             if(reset_n) begin
                 async_reg[0]         <= {WIDTH{1'b0}};
             end
             else begin 
                 async_reg[0]         <= d_i;
             end
         end
             
         for (i=1; i<ASYNC_STAGE; i=i+1) begin
             always @ (posedge clk or posedge reset_n) begin
                 if(reset_n) begin
                     async_reg[i]         <= {WIDTH{1'b0}};
                 end
                 else begin 
                     async_reg[i]         <= async_reg[i-1];
                 end
             end
         end
      end
      else begin: high_reset_1
         always @ (posedge clk or posedge reset_n) begin
             if(reset_n) begin
                 async_reg[0]         <= {WIDTH{1'b1}};
             end
             else begin 
                 async_reg[0]         <= d_i;
             end
         end
             
         for (i=1; i<ASYNC_STAGE; i=i+1) begin
             always @ (posedge clk or posedge reset_n) begin
                 if(reset_n) begin
                     async_reg[i]         <= {WIDTH{1'b1}};
                 end
                 else begin 
                     async_reg[i]         <= async_reg[i-1];
                 end
             end
         end
      end
   end
endgenerate

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   simple_dual_port_ram_fifo.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      EFX FIFO
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
//
// *******************************

module `IP_MODULE_NAME(efx_fifo_ctl) # (
    parameter SYNC_CLK           = 1,
    parameter SYNC_STAGE         = 2,
    parameter MODE               = "STANDARD",
    parameter WR_DEPTH           = 512,
    parameter WADDR_WIDTH        = 9,
    parameter RADDR_WIDTH        = 9,
    parameter ASYM_WIDTH_RATIO   = 4,
    parameter RAM_MUX_RATIO      = 1,
    parameter PIPELINE_REG       = 1,
    parameter ALMOST_FLAG        = 1,
    parameter PROGRAMMABLE_FULL  = "NONE",
    parameter PROG_FULL_ASSERT   = 0,
    parameter PROG_FULL_NEGATE   = 0,
    parameter PROGRAMMABLE_EMPTY = "NONE",
    parameter PROG_EMPTY_ASSERT  = 0,
    parameter PROG_EMPTY_NEGATE  = 0,
    parameter OUTPUT_REG         = 0,
    parameter HANDSHAKE_FLAG     = 1, 
    parameter OVERFLOW_PROTECT   = 0,
    parameter UNDERFLOW_PROTECT  = 0
)(
    input   wire                   wr_rst,
    input   wire                   rd_rst,
    input   wire                   wclk,
    input   wire                   rclk,
    input   wire                   we,
    input   wire                   re,
    output  wire                   wr_full,
    output  reg                    wr_ack,
    output  wire                   wr_almost_full,
    output  wire                   rd_empty,
    output  wire                   rd_almost_empty,
    output  wire                   wr_prog_full,
    output  wire                   rd_prog_empty,
    output  wire                   wr_en_int,
    output  wire                   rd_en_int,
    output  wire [WADDR_WIDTH-1:0] waddr,
    output  wire [RADDR_WIDTH-1:0] raddr,
    output  wire [WADDR_WIDTH:0]   wr_datacount,
    output  wire [RADDR_WIDTH:0]   rd_datacount,
    output  wire                   rd_vld,
    output  reg                    wr_overflow,
    output  reg                    rd_underflow
);

reg  [WADDR_WIDTH:0] waddr_cntr;
reg  [WADDR_WIDTH:0] waddr_cntr_r;
reg  [RADDR_WIDTH:0] raddr_cntr;
reg                  rd_valid;

wire [WADDR_WIDTH:0] waddr_int;
wire [RADDR_WIDTH:0] raddr_int;
wire                 rd_empty_int;
wire [WADDR_WIDTH:0] wr_datacount_int;
wire [RADDR_WIDTH:0] rd_datacount_int;

assign waddr     = waddr_cntr[WADDR_WIDTH-1:0];
// NIC
wire [RADDR_WIDTH:0] ram_raddr;
assign raddr     = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0];
//assign raddr     = raddr_cntr[RADDR_WIDTH-1:0];
//assign wr_en_int = we & ~wr_full;
assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we;

assign wr_datacount  = wr_datacount_int;
assign rd_datacount  = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int;


generate
    if (MODE == "FWFT") begin    
        // NIC
        //assign rd_en_int     = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int);
        //assign rd_empty      = rd_empty_fwft;

        assign rd_en_int     = 1'b1;
        //assign rd_empty      = rd_empty_int;
        
        //always @ (posedge rclk or posedge rd_rst) begin
        //    if (rd_rst) begin
        //        init_set <= 1'b1;
        //    end
        //    else if (~init_set & rd_empty) begin
        //        init_set <= 1'b1;            
        //    end
        //    else if (~rd_empty_int) begin
        //        init_set <= 1'b0;            
        //    end
        //    else if (rd_empty) begin
        //        init_set <= 1'b1;            
        //    end
        //end
        // NIC 
        //always @ (posedge rclk or posedge rd_rst) begin
        //    if (rd_rst) begin
        //        rd_empty_fwft <= 1'b1;
        //    end
        //    else if (rd_en_int) begin
        //        rd_empty_fwft <= 1'b0;            
        //    end
        //    else if (re) begin
        //        rd_empty_fwft <= 1'b1;            
        //    end
        //end          
        
        //if (FAMILY == "TRION") begin
        if (OUTPUT_REG) begin
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid <= 1'b0;
                end
                else begin
                    rd_valid <= ~rd_empty;
                end
            end
            assign rd_vld = rd_valid;                
        end    
        else begin
            assign rd_vld = ~rd_empty;                
        end
        
        assign rd_empty = rd_empty_int;
    end
    else begin
        assign rd_en_int     = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re;
        assign rd_empty      = rd_empty_int;
        
        if (OUTPUT_REG) begin
            reg rd_valid_r;
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid_r <= 'h0;
                    rd_valid   <= 'h0;
                end
                else begin
                    {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int};
                end
            end
            assign rd_vld = rd_valid;            
        end
        else begin
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    rd_valid  <= 'h0;
                end
                else begin
                    rd_valid <= rd_en_int;
                end
            end
            assign rd_vld = rd_valid;
        end
    end
    
    if (ALMOST_FLAG) begin
        assign wr_almost_full   = wr_datacount >= WR_DEPTH-1;
        assign rd_almost_empty  = rd_datacount <= 'd1;
    end
    else begin
        assign wr_almost_full   = 1'b0;
        assign rd_almost_empty  = 1'b0;        
    end
    
    if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin
        reg    wr_prog_full_int;
        assign wr_prog_full  = wr_datacount >= PROG_FULL_ASSERT;
        
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_prog_full_int  <= 1'b0;
            end
            else begin
                wr_prog_full_int  <= wr_prog_full;
            end
        end  
    end
    else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin
        reg    wr_prog_full_int;
        assign wr_prog_full  = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT;   

        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_prog_full_int  <= 1'b0;
            end
            else begin
                wr_prog_full_int  <= wr_prog_full;
            end
        end              
    end
    else begin
        assign wr_prog_full  = 1'b0; 
    end
        
    if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin
        reg    rd_prog_empty_int;
        assign rd_prog_empty  = rd_datacount <= PROG_EMPTY_ASSERT;
            
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_prog_empty_int <= 1'b1;
            end
            else begin
                rd_prog_empty_int <= rd_prog_empty;
            end
        end
    end
    else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin
        reg    rd_prog_empty_int;
        assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT);
            
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_prog_empty_int <= 1'b1;
            end
            else begin
                rd_prog_empty_int <= rd_prog_empty;
            end
        end  
    end
    else begin
        assign rd_prog_empty  = 1'b0; 
    end
    
    if (HANDSHAKE_FLAG) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_ack <= 1'b0;
            end
            else begin
                // NIC
                //wr_ack <= wr_en_int & ~wr_overflow;
                wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int;
            end
        end
    end

    if (OVERFLOW_PROTECT) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_overflow <= 1'b0;
            end
            else if (we && wr_full) begin
                wr_overflow <= 1'b1;
            end
            else begin
                wr_overflow <= 1'b0;            
            end
        end
    end
    else if (HANDSHAKE_FLAG) begin
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                wr_overflow <= 1'b0;
            end
            else begin
                wr_overflow <= we && wr_full ? 1'b1 : wr_overflow;
            end
        end
    end

    if (UNDERFLOW_PROTECT) begin     
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_underflow <= 1'b0;
            end
            else if (re && rd_empty) begin
                rd_underflow <= 1'b1;
            end
            else begin
                rd_underflow <= 1'b0;            
            end
        end
    end
    else if (HANDSHAKE_FLAG) begin
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                rd_underflow <= 1'b0;
            end
            else begin
                rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow;
            end
        end
    end
    
    localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH;
    
    if (ASYM_WIDTH_RATIO < 4) begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]);
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH];
        assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO);
        assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr;
    end
    // NIC
    else if (ASYM_WIDTH_RATIO == 4) begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]);
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0];
        assign wr_datacount_int = waddr_cntr - raddr_int;
        assign rd_datacount_int = waddr_int - raddr_cntr;
    end
    else begin
        assign wr_full          = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]);
        // NIC
        //assign rd_empty_int     = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO;
        assign rd_empty_int     = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0];
        assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO);
        assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr;
    end
endgenerate

always @ (posedge wclk or posedge wr_rst) begin
    if (wr_rst) begin
        waddr_cntr   <= 'h0;
    end
    else if (wr_en_int) begin
        waddr_cntr   <= waddr_cntr + 1'b1;
    end
end

always @ (posedge wclk or posedge wr_rst) begin
    if (wr_rst) begin
        waddr_cntr_r  <= 'h0;
    end
    else begin
        waddr_cntr_r  <= waddr_cntr;
    end
end

always @ (posedge rclk or posedge rd_rst) begin
    if (rd_rst) begin
        raddr_cntr   <= 'h0;
    end
    // NIC
    //else if (rd_en_int) begin
    else begin
        //raddr_cntr   <= raddr_cntr + 1'b1;
        //raddr_cntr   <= raddr_cntr + (re & ~rd_empty_int);
        raddr_cntr   <= ram_raddr;
    end
end
// NIC
assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re);


generate
    if (SYNC_CLK) begin : sync_clk
       if (MODE == "FWFT") begin
          assign waddr_int = waddr_cntr_r;
          assign raddr_int        = raddr_cntr;
       end
       else begin
          assign waddr_int        = waddr_cntr;
          assign raddr_int        = raddr_cntr;
       end
    end
    else begin : async_clk
        reg  [RADDR_WIDTH:0] raddr_cntr_gry_r;
        reg  [WADDR_WIDTH:0] waddr_cntr_gry_r;
        
        wire [RADDR_WIDTH:0] raddr_cntr_gry;
        wire [RADDR_WIDTH:0] raddr_cntr_gry_sync;
        wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b;
        wire [WADDR_WIDTH:0] waddr_cntr_gry;
        wire [WADDR_WIDTH:0] waddr_cntr_gry_sync;
        wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b;

        if (PIPELINE_REG) begin
            reg  [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r;    
            reg  [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r;        
        
            assign waddr_int        = waddr_cntr_sync_g2b_r;
            assign raddr_int        = raddr_cntr_sync_g2b_r;
            
            always @ (posedge wclk or posedge wr_rst) begin
                if (wr_rst) begin
                    raddr_cntr_sync_g2b_r <= 'h0;
                end
                else begin
                    raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b;
                end
            end
            
            always @ (posedge rclk or posedge rd_rst) begin
                if (rd_rst) begin
                    waddr_cntr_sync_g2b_r <= 'h0;
                end
                else begin
                    waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b;
                end
            end
        end
        else begin
            assign waddr_int        = waddr_cntr_sync_g2b;
            assign raddr_int        = raddr_cntr_sync_g2b;        
        end
      
        always @ (posedge rclk or posedge rd_rst) begin
            if (rd_rst) begin
                raddr_cntr_gry_r <= 'h0;
            end
            else begin
                raddr_cntr_gry_r <= raddr_cntr_gry;
            end
        end
        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1)                                           ) xrd2wr_bin2gray    (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry));
        `IP_MODULE_NAME(efx_asyncreg)      # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0)) xrd2wr_addr_sync   (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync));
        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1)                                           ) xrd2wr_gray2bin    (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b));
        
        always @ (posedge wclk or posedge wr_rst) begin
            if (wr_rst) begin
                waddr_cntr_gry_r <= 'h0;
            end
            else begin
                waddr_cntr_gry_r <= waddr_cntr_gry;
            end
        end        
        `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1)                                           ) wr2rd_bin2gray  (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry));
        `IP_MODULE_NAME(efx_asyncreg)      # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync));
        `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1)                                           ) wr2rd_gray2bin  (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b));        

    end
endgenerate
endmodule


////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   bin2gray.v
//       / / .'     /    
//    __/ /.'      /     Description:
//   __   \       /      Binary to Gray Encoding Convertor
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

`resetall
`timescale 1ns/1ps

module `IP_MODULE_NAME(efx_fifo_bin2gray)
#(parameter WIDTH=5)
(// outputs
 output wire [WIDTH-1:0] gray_o,
 // input
 input [WIDTH-1:0] bin_i
 );

//---------------------------------------------------------------------
// Function :   bit_xor
// Description: reduction xor
function bit_xor (
  input [31:0] nex_bit,
  input [31:0] curr_bit,
  input [WIDTH-1:0] xor_in);
  begin : fn_bit_xor
    bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit];
  end
endfunction

// Convert Binary to Gray, bit by bit
generate 
begin
  genvar bit_idx;
  for(bit_idx=0; bit_idx<WIDTH-1; bit_idx=bit_idx+1) begin : gBinBits
    assign gray_o[bit_idx] = bit_xor(bit_idx+1, bit_idx, bin_i);
  end
  assign   gray_o[WIDTH-1] = bin_i[WIDTH-1];
end
endgenerate

endmodule 

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
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`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5328 )
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qA6xvz9K9/isRFHF3+PxrugHzqedTh2pWNfEbTe38VFIgi+J5EjS/2AOfc9Vpv97
a72gIn6+tnPFKkbP+6ICJIvXXaq2iSuunxd/mqmRdCxGSiXGdvq2vm5AvFsag9gI
HYTRGEghDC85+czudkQUreNxkflX+v8qdt7EoPITr4EZFJiMLRG6l3aMspFVcuBC
p+XzuZ5n6VcukOwCeygar246fizodXUDaC+o5PluHoU1cQv32uv1Z/RMA4thPdcp
S4mtUYNMd1udWp2jj3QsG1K2RerWZP4C6vmG7TjjRqiegdFbHfWWz1UgUhxBR7rn
oWkAjUrR4O8pLvXkukAaQjeSzeM4bDAXoMfWjuLJ5okmK7FrrfvJis8rsZsNfCro
2KsjzEZbFTlqnzDfjxrwfIOqqlas5/kmG8VntndctlcWiGVNsCXbXpQNlrDQfIWF
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fFDefxK5AFfLFp7yhLAQHG8W99NPGej3i24U7ad3f3GjjWNxuyhT95uf7BCgtdgC
LNx31VG6wWppJSj1cC3XkgbWMckv/zvOR1+uFjwFGMk4RDNYKq6YkxcEhwGnrAB+
JcOSH5VTcbp+kPUskvBkEbK+0wY+rZuV4zBYQea725NPr1q8lDoP7SnO20zTwq1m
Y3P46UVekvwP3/g9zIMjnBbKd1wNqDYUZbJffZfZCpHj6rEa6tLGyPRhCUlpu2EO
hFpRNAXuOesUZEGbnwuls2McNkw3YbqVKRibXdGH3K7Q/c03Wmx0xey4k/nUV95b
2iqjJ0p039WFpzNn0Kp/0yHlbrkG95KEVqOi1IFGluTXpRCJyH7DIJd2kYXJNPmC
6d6KcKnaxoMgI0Gjo7KlU1566ebuht3ZYIvOZmyBdiwlunUqqkAPUb4yKCg5AH8r
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B4cERfKhg1ABJ3d8Y09LRaolSCGp/YjSTO03k067tO4tujH0RJIjg3YoPW9kb7NV
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
nJgnLaMMhKfu2u4XEaRIJtPXMy+GdJWf8MphqdFOzpPWcgYqavV24ZH3Fb1XKm0D
RYouBJETmZDyA9OHB5vhXctF79TFLkbh668E5KD+1AVV2RXVnYbAXCKA7+sKITdv
kzUdbOEs8ptW7L7JwVNntydTiawwMl5gKe1iRgICz+ZJErk+ua1pUV7ySLsyR6MK
OfQ6MokP3fTofmoeWleHZP7hlfiTVbV29ph0m2bcBah8QcT6e2cAX8K/BNbyf2ky
CeDqG4lHtwOyTG0mMVoLNQkyPdTYfrimhsS4SnLDUhVbrqKqAuEH1SO3eyVnEPn0
a4AwlqxatmJ3IGGqkF5piQ==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 624 )
`pragma protect data_block
CLSJR0UGj/cwSk/00Oqg6Le/W1grUImVlUS8zVbaME84SVdzRPNzRHc0p8+A5q9I
tivKMxmOBiOFwYlcMqmvwA3gReO8/vcbqqOyDrnGjC3iJA1B14GCctYGevoa0wJk
MXdVY8bSP4XtOYSneYQwqzx/WIMQouMdkglgpzeVrL72kQYkAchgnQP+tLGrBHO2
BW175+LIhZp2GkDcfmtKEuiRMMuKA/PWkjmMMMjs5yLUdoNPZQw/SKSYvhGdUa4t
J8dH2Np3lLbwhmGfDc/2eWoZI4JRMqzXHwbKJtvdSTZGLY3Cx+Sr8W5iMYRImrEu
l1W6iziSdXEmgIHyTiKx2HMQuybk+yAmkBl9bbNpN85wmq+eTr+kMgO4fpTkvgXC
TICzgkLqCw4W6Rf45uC6DiV+8ng6i1MvCEg7Tshy7G3aigTMSz+HqXKfOQxS9VJo
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JohTNkudmmUiGD52234oy3/g9d5MEM1kBV9JYnjF5pSKPABwHRYVQuWVjUq0O0m/
yvN/mb6eqTeEutvHfBj2gYoR3tnaTLnXwNy3jpZlOBnlEErXEJQfK/YBfsAweGXs
kM3tlKr8ujZ6U4g7uWN/awKcH3Y4nQD1iUmeSnEhjPqzEQcVApOTScAC1vlyRZpb
AWiXXNrfk2Qgf9HaURptsCnYhqf86ZpSad16YURJDgHd1kBEZhUhe0UH+0cxsaU8
8J8oRcrDJJcC8i/PPeLtMiaP9v77SCvgkY6uvS2xUixQU3ObXjW7MnO0ZbhccfDG
`pragma protect end_protected

//pragma protect end


//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
FoiDQ5MRk1hD69+iCS+SpSPqrecuCylYskFJULCGHhT1TDOEvmfbSmL14qERSazx
XIvjSk+Tv8pkZ9V8meo8edWmSZtn8GicdAIDZjraJuR9mYyJqR4UL/GxB05Vuz1m
mIycd72qyJEnJIR6xYt83/JfOkZ4DhYmIwUhhzIoYmR6mLWCo1Yb+8qdmu9Rm9MG
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xJHiw/vNygUxdNWA7DwQZo4bfKRVpDVxBsf/Otq9xmU9xT0ESdd82q6ODqvDUcFU
BihXmHxlNWGlcKASsRnH+A==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 3760 )
`pragma protect data_block
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VG7MU+xynFpwebzHD/nvqg+aGVXOZNwnakf+W4yIcjxRPf9VcENKgmIj4TiLGwgd
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qH461SuoPkCuOrGY064tYig8IEDUMgp5/6IhHnQHioV3p0Ti8zi+j5g6WotgWkQ+
Lo8y5geDtX74szrv9tdg8/vMtFAUkaOklw5uvdJ8pyGRA/Ct7oAFnsgt7xBOhheV
AzVfX7FZnNL998lOxa0K9BlAg9Itco7HHuilM3Z9Vi9OSktyZul3+IWVVwyBkbtk
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II4CSvgs0Ka0rxTsleXB+/6LHBwbckNirT8DhEdhqu5XMt3pirKiUr9G98avLyfF
M0FRMJXOARjY//Pt5WFvZ5tjjCdDG/JairkV5Pip2FiVY+7rjUU5uLtedaMU/UKE
DJkA28iA6SZejOjc0EwKMvE0S9ekAR2KjQ2Zse2u6Zo5WcKHurhLfFmB7tjQtaAy
stdtW2vXnQXe4lDzLYb5xV2Zuq+Fqfcixd0aHmHQUHHZn/+l0GWPzHCHiG9OHmtu
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U5RqS7QEcayh6zlvFHHkW9lkvTgMRE5JRTzM0pwnjle5r4kCOUx8faTXzI+qMQWZ
w/ixtqMSBHP7Wub5c7sm+EajWZNzfmldlyp9D1hx0BE/uOJoJ0aZeHsFwFeMsdg+
8QJ8730czxnTCi40usAc4G8ThwsWyUl9sNcZRr5R+6LoITB8RflJhFmgMVH8zcqp
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bz5/aBvV8SZe2lTTf4c58nZjLIeuhXHvrMW1Trfx2EoX9Xz0ChOSyfC/Z0UTttIm
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V7eiagwP9OPmEesF/g7QhN+f+bD2XuRy+vGDWCIrLFcVUmio4iD9blF6tN+ljkBP
HMJ/eBmpp+7JfkNbXvVH9rvRPo0xJO1hofNr7eFcLCPL3I15QdmCnHOEDIsQ6X/i
4tiSJ59+1CbEsj0gfq00YM0VnIvNTgV2+KdEC1sBZQUU5RldMltsUpvv5LTJHPL+
fS6PblqjQ8IYpxGfM+iby1yGP7fNPwDs6UbEEu+1zO+3rMtnqsBg8qdxkpACh57W
Ltk9Puo5M5pbM67wnYezQOyOVmyuAXuTQoyM1qm4GDMAK2TPljE0SxLIA35OD0uA
Ed2wRLV5NcD5IPhVaBE5n3Am8lpCNpBsjpwtv0N8XeeJ0kG1X1ItvIJcjstIC4um
8NJdNv5u3W2ko2iKo4jAu0AzAtexY/ASEeMpi9ORs8x74/KLTa7wNQl34/j+GqiB
n8dCkwFafwzpXKg24LovRoCPyEFub1LrV8tObncpzNmaWeb2uWYEN9lKGXUzsKcQ
+ZDrgMUkc9BtvjxCmNKuX4mwtN/60OyCi7w4knOxuPwiXRKWE/BJdn5750J2ivrP
XRkOaLN9KlxUbcp6FhG8nskhyGF5HeL6WU8TY/PlvlT2HS6XLAkFugn2auiylY/u
qzkAyoj+RWShr2gXSeOrTVH5bIFEgYQ6tkD4PMPH7HzVxyD/KTU2omc2A26zCVPx
hN7SVNjtHEj4iExWGwA2aHcQJcbKqFCQGRKVD6ghkVULarYVLSKy5qFJQX+L4blv
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HhWNj8KzbC9DjCR/RuTIrR/Dx3C2qZCann+lpN8V2jNusVAt6HqgAp6P3G/9Peqh
0eARUOZaW/3RQOaG0Oa79g==
`pragma protect end_protected

//pragma protect end


`timescale 1ns/10ps
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
lDC8aCCj7YnQzRClR/1zA1JU3g5BPVmd7B+bk4FhhVvSfnTAYYXh3yftfgLDM5if
P31YhPkBrBoDg7S3Ke2IdsZdH8Ohu/4EXXgCtZGCBtk7Z8XfbFtsqNd3NMtpOJK9
qHKFiF3W0PQkYLXz8ZDlIuQoCy1TjFgREgMiJHEosD92avlNvRGThU+nXnbnHQXR
10BGg3KadBwrL88NgK5Y2ODGFn+U9AkJHW1VnZkKWqEyyf/LaUW7mYyljvXZkcF1
ayBunX+jdRJYDzrAS6hG0hNRJfSNNYZWMdoUkkAYgDpsFnOCzVgTt3j92Iz65JRQ
wzh8KMUvv+WCkSNOE+iWuQ==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1168 )
`pragma protect data_block
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jFfD8/9riZoeORSIP8g1fKvCuNKGrJVpaeWzyb2M4LwJfQeJWXSuSZGiGkwTe0GN
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FO1QV1dRRGCQsZdznDE5jtUYv2tDkK1v5XbBy3hU1qa0AMNidnU5wYMW9Fo0AQdw
1oOeNwIq9ns99vt8rpx5yhUJjjt0Awsr2sS2b+9uqes3udBJk1sULF2gm9d+Gpbp
IlWZd2mFvhZuDDEINQEH2TG3l4x9NpBwurh5YRxSSDmExINj0uybfR1hsuAUQI+N
hbGr8V3pClMylpkQOy256BUrdfAbOeDh6FYae5TJObYx1BHdYNrg8WlUqjbtFj9i
Q+ojyteTKdaX23KIYhIyOw5rCnydThTgFxL0o8wUk8gSF7j2W4IcAV/mW+1Dx26N
R1GbkEBx0kHb5RPvjxr+rFwc92bIy4FNPREQfkXk9HwyM/bmy3dtZzN4OzQJiPXt
5nNuaSj6DPyvlXZofbsqLLotR6aH0lDXkK2pwyR98utaSAncisR4pdx+upy1mwpR
uz4KHqWoQnFbM1HzZtNcLnq21P43EUwoFewwyIloxFNRwLQ9e+jj9Y8GN2k2/eq3
Yrpsn8LL8WcwYueu+FAJTlU9bup3aD5FM7qKucF8TFii/mos+imjPQAVjZUQOuHO
WnvI5dvv6PdqeqKilf81+18UjGOQRJreLZ2z1Wo2bILHdMVg5id1k5EVuwPP8t6O
xrKFX0Z04ceDvaNe/weFyxCZPF6nH574w2sJfbtfWJUj95fhK7Yzgz7nTURYinmh
noSXzHEFuptGxlD1Dp2Qe27JqNzaB+XfolEHqGmXs1iUKLasutNLZy7wN3B7nJJl
aQ7pa4xSdEM6JcXw3v0FRD7cKqOsN+H/5bChlbV0pJ6ZlyPyttnCV5yPpPXBo7C3
j1QX9LZUcBIXMm1uN54kmcnGRRUqgzki7uKc6CAeHIK2lJUMMRo9L010cGhyXlH7
ZXLikKsynp5GXAycfuJ0FuCvrNZl0uZiPtmeWMHtsB/LqMsMmcPHl2qC7xSAvpuI
gPtcteDPLPKhCwXcHCoN5zL1TpZ3CoBp5nHJwmEI4PshtmmGAUEHRHoy73izx/Mm
Du0je403ptoTeE85CW6iV126Hk+raI2+vcS9PCYsTkVqAa9A0Uj/UNoQhKCSS6gj
EnqIdisYL0IsXWBFtoYUcHN/mmZYHEDuzqditfSt+RobYhgwlCw/1GT4DFQ8xx6D
1tbmL2mv/jeUnihyquEkGfFLkfb8pP41cBFfI8DklHBh03bzWM9/Ygw0rquP2vsR
8xLYCvqW/wF8FG96VbrK1MfLEgk3l/SHVmg+OxV5N9C9hJ02zvLeXwHXWIs8rKIe
wblSpyGqVY4zgazTbIl2fQ==
`pragma protect end_protected

//pragma protect end


`timescale 1ns/10ps
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
kyDUqqHobwKicI1SiAqBLzMxdApYi8tOKWM3fYe/zjVqYPvpSBbTmdtTpUoQoBKQ
fEyYw95Ts1CIeNNlUPnyqakYHUgKWY8RSPerwHlP2fJQmNdzhYybS7BOTYuj64ZJ
OPoN07U3U5ltZMrq1qrVM9oTr7XW36alP2ZMYpA+RHDtphzdr2+vuB/ZMzQFQMH8
KUI9nqHor3YlNwxKi4g91Jsd58NV8XJY1K2RVfWkvTQIlOtDJCAODEz2qKy3jF4w
4pXcrtnEyu5HliRr1Q3MYAZhIRzAbnB2IAJLq/ZITBZ18yH4fw7nK+a7xxwWhbfF
fCDXgowpIOlGpJsU/v+PMg==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8288 )
`pragma protect data_block
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qNzUSR8JvTY2SQUV++kv7jG1t2gNIKjmuaoEMsEI6OTAwB/FACX5pprBIiMglslY
p/o4XQKf/OTDE/bX9Y3sj3jlQKlHTwzgFIad4PeVMggeqiQWvihsc6TBhds1uzvJ
jeEIeB/D5S42U3eYbrqQ/K0KwlBJdzC6oln9ZW1T+hMeYQDgwkVbqhU6qXtnnhXN
97rpeVZ+rZ5J1y9Fq6aH8IVctsPZRgazx1ezDXk5nmuDazHMDyZ6as5jYiT2UaXf
HbX9HJPKdv426wGjydsyB5JsAsblA7OCu8Ki7XFlBTQTXbHRSp/XHY1GIApKGNS4
nJIXDTUJVUNZUML90tV5A3p4Sqj36LxJsqP/H5i3KidPaF6nXNUng8pZoKgaNm2l
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JB9CG8nt1N3AeLo4xUiUg54hdclBxvpPdwgI2rEyDrW8JcxeEqbnuAxxfr+dj1hd
8WRDDRv06KftBlQ7m5V30uyEdhNT6mNcDiBXw7H1SuA0MLhVWxyJ2iLYiZC7LMC8
gny5uVT3vXSjKeDIugXdQ+mqPk7+jy1gAh1eNaTCPLvp0YyW30FgrXLRd+I8VmVV
6jEjV0UAnpAqr5SVVbXAWNdiIbziVGmIi5hCPi6CllU4hMu2WVcsmWuSLs6/1yhh
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34VVYfIYBD5fNMMRGLEw4UW1jY72d4vzG56Nga8vH+0zN2n489TXsVTuHjS7goTY
Yt1jno3M9ZC3Ab45Y0owCghvnhpy2aUplotVcMEx1P8w2lWJKD18yhg3FvlNulDa
vn+LXoR+uQpUGCTVzAQ6u5Ll1qbTiqcebfFLNxbF0h51VrTtIcpwVry0Q2TE81t+
3bu7bjGDz3q6btP3DW/OyZCPswMQoWIYrEcxjIjcgXAleKo8moJlNi5FeXvrHJDh
lBMQVa6uH4tT4OcsAB/ykQDZGAJ7NYpG+6VwY573Xn4CIPRLs+YvwQVOi6ejtQAN
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rkP6pUahmoqQXQE5h4mvYNEL/1kxwly+50lu/9DgOmTLTNIpYscftzRfvauk0WMA
aWSYonck0HGBHCR2dDJOEAobq3CsF3mZrAUUeTRGaz1hu63lvvtq/59cwkqdvVMW
PWaPbttOmkMoHbm+HjhHlgssiG8fSOICD3jbZdvzx+aBOXdIrsM4Wm+cLHJ4rqZJ
K2CZ9xfBbB785IiAMWRwpwuCBPrRNM/DqQLv1UvABZ0qjrYzE11m9eQMlO5wYP2L
mwJkbVW//BnxztYz5YItIDyvb5cR2ATSBo+HpvKBNeE8BHriQj6AdfB9rXxQA8wF
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jhZGBvIkjPkvprcWmdp9FmHBS3aGQRkR7IOGk3mKASagxU01UlABVa1vXlLqu1o8
YAamBvxMSmGc/ht+TCMjDp2KgLqaCohPX6ZWjRLpmXdfqWel8POI06HLzJa170Eu
NSo7627WG/D+SceE/CmwSsUDYsffMGvX7eEVXO6k5UjSzqnS9H1QxpY/E4+pf172
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kVGkwYAQvvpGbJMimi/76yITUIZ1JQ6YF09jh/9aYzj84znMM47CPVbBrlm8ciI/
otTs5JMFiM5SjFVVOoZgOTN5cNG6Svgl7sLIul/8O7dWjBgGSy5QsRnKNWJ9ZThH
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H+gcwGrRFqvUMezGry6ArBaLTCccs7wCwOfQHJlca3ipn26yRLtfUjL4FxpugvsH
ahcRUFstLGcpW2pZ4uICdDuWnCcgMZBa8z8Dyw4kObKYKb4mr+m1Hs7lk739YtEF
DA+IwH1uthKlVIX9MojNR98EIi2oLn0OJpsc88h+x16FZ6R8YmzKp7wMrQPr7ukZ
x7qWLDWL4yeYfKrxAER3CeIJStR5xRQ2hFxUCkQetlI=
`pragma protect end_protected

//pragma protect end


`timescale 1ns/10ps
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
eXP6UghbvhkuRa3wjCSGUdYo5j8DzqKptmDeg7TRSZUHgezuSBsvtlFFj3GGElL0
leDCL04/HfAmTGu5Qle5EZYNXm8oiTKjSm4B7uvzJke2aVD+ja7c/c7xl55J+myN
PdhEX5cEtGZmlr4y4xuiZbvHP8YYQMsx38HgL0o07WxEVM04cwyWu8g4iB+sPVCU
CruAhVEQl8wZZ1HqFoMK3pc09NPWyE2qJW9MyYF37EPGpCZhpfoXK27LHnOVhYBg
FhskoEkJrMAEQOTGz2AN39bsi6hNqPHAhqy2wMtIrwXxR72hJlR0lxIS8deA9fFl
aXYCci1uT2fSWTLWtNbphg==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1696 )
`pragma protect data_block
GO+vr5fVHX6kWytOaBOck8XlbTpR5cgh7FAgAIxKwUzeNTpP9k1TzMNydSwqA0yg
QGqOMuf3m5I3NE4j3KqlVfblYd4EJ35YOkuq0F7skz1xIr9CAdINMxruvPtHddpP
ArT5u7gnNqoyv4eiTD6S6cRZZKAaNQxf0xuztSif1ZvlwG0UFDa1BAJTaJXh5U+x
Lg7gTyZrRQyMQuX6nbMfe43D1ViZjwvc2mmPKB0Nsk28eDnVunxM6RPoY05eYe9V
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lFpvQQfF9UGl7zZTMY2m24RkCKN9sUmLUiDzW3E2u13qik2PJqW0zw0RzRZ9AMFw
5B4NBxMbZJRlA1wMw1O2LPy+z4NjS00qkbKsUvvfAz7EuR+axHv8unDhtu944uk3
6iSMpFZZWqdpm7xPmUvJjTF9UJjkoVmFpfsD3aXKF6x9Hy7etRcX42AlhGJu/k8B
oG/M7sXMWIa1ymEUc4uh4ibo+Sm/CP5NxVNi5Lv8ZrW+8OTZpGlq4J1hsxGptRz8
X8SAEG0D92BRECfeLWo6vkhLf5bc2WnadTBp/tU/v5GfYGq/KaWdUhGxmk3y2ZSf
oHaIJ+V4BsK6c0R4vTyiKF1XD5CEROVDBe3EAvxzMAhRGeEPE1PfxjaP6egQaRVK
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V0utfP4rkCFpUWXlYkdMTmmbsMaaCYw2Yrc4Q/4CjKvelTHunTMtD/qpluKiI8Bd
eZHT/kr7bwmDbHthqfVUh0cVBb+qkoYNTG/qrMm+5cdcG1/9Ac31wc+RkFLxpTd1
1RqHh/x8M4XouSJVFzBxQP7M/EMQKv+JaVXzKoWsu4HtqExm5wFkQkf2UzP6Zlur
tGiDXuJu35vPOsKn6XJmpsNkeTk8wNEX5ywPagGoV+6zpAGXshuM1kXjmndpxSd1
DD/l1kQ5IlRD6Mom/iBxmJPAESEA1LHHD+na7Es0P3s3UOdI8A1KTdGzgfg0nr7e
maJlgrmj1WjZKwmR0MPcScUXvWKIPGxVT16aa2oy5oEyafYaK2r5vEZy7ucucn0U
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bkcp+4IVPmHRV49vlL8RbHFvepu8kxVJCM5YxGydLAXenLXAuiN5xoY8kiPp+wwD
GvoLCvNEoETfcNlLmfFzp2t7rfHvwk5sWSdF1wrn5yx842WB0LgecmiIb/NvLDo/
iZHxZFBUZFAQf6NNojwvLob3qTh2GV5y4Vv+YuWhYnI7i5PLYx7DMPBqZpfTwah8
JtTF81C/K6AXQu5vbX85e4QQfuzTZIRhdY0/vtC6OB6TC/srczFlPHPCLjhbdfiR
ZGQ8g3gHCOdxgwIGzJ/VKw==
`pragma protect end_protected

//pragma protect end


`timescale 1ns/10ps
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
fcVf9stqq61DLeq9hkZQEcSflbGK4KTXlx1AHMMgjkSi2GoWM3M/TTauJYVEFjV5
Vb+94C9+VqhOA65dgVosuwAEhQiJx/o5BaCRmQ7LPwtSmFrEwjvrtG1nzDnlEZLS
TyNq0iHVMm/+LqCuQCehPBO58IOOJrxmcEFQQPzzPI7ILCB6zR6mcNzVFevM5K+o
l4OWQE3CNptUjpu70NO34scsVXHqbWOWjcMRqkRO6wGBJ1Ciu9Q/jRXiuHmp8E/J
sPw5lc4YTovTi+eF2AsGFIsYVDHOcSq0VF+qCLc+3hxR8kp4ZAdbHZiITFHgL+OA
An+SUmpB42I+/6fMV61eHg==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1984 )
`pragma protect data_block
HUBr/IcEYHQs9WR1bPhE9kxF7oJ6Jp4fgxvYo3PH+40KWk09T+44GEe0pMXl76ZD
1d73ITHhZozJP6GcW60KAxMoLlHIGxnwlQYCjaPDcYeh8cHJlegQPWmd/OPclw6o
FRI2FyJb26lJGFsCoFF4Tl/b0aSbQDjkOM6t64S7kH26GDmvSAq1X+pcQMmlJOZs
zZphig+SeBwG80HuIr3+PQzRxM3Z1HLVChN8EWgQdwivgDVXz7abMfgnKb0luFqF
t6vRZQWnDxUmNrVK5k6Xc5kCUlRor1FTrvYoUsHCE1uDsw9mkiMb6f96wY2hKkRF
kEe2uBLy/tKTBmhik/pof9/eKKLqrCyBrgAaxpuPThIBc/6XMy2yqswKwk+yub5d
uMgJ/tomAMXSE12S8FaneUAdDhYRY6ry4+1OKpXPTIiVc1hg/qzQy/CWVkFfphSS
IJmWsJON6j64c5PKtd7ITYOAcfbzY2BjyRCX1wDlichaMHT6bM7vrJp9u1E7FNt9
7VoQa68EFrUx5ENHolUdkh9hxwYrfXWMM58waYytp0nD51c+19AnLwqu3Ac9os0q
IClDOx6FkSJ9/Cq60xZij2YfWtX7jremLqnn7w439O6YQonQu2oTFLmFmK2WNoq2
rj6N0b3OTBMI+vkshqOet2TDi5yneXs6V/resNGPr7cEwhc8zyPaL1lbnjU6LKoO
NUh9p5Cz7e/uaRzXjebDHzl5UHuoz9gnpIJ375V1Jo08DnI+L5Ezh4U6x7gkLiRR
pqSMg3M3b3UmAu7U1BGZ0P4H6FWVWjbR1yBTNekyDFczFbuGNje0tiKPQlfwR+6g
1OqsXXoAUmYfd5teMwQ40edyB/YeVBD0TCgTXwIAzaTa6EI8CgC+N82k96GcCUFn
EUlovEDnHmwcx3YD79XvOxTZj414Cz4vfXzAtROD/PK+tjVkId+L1tjDMBEpDq7x
SDWKS0eC1txefRqY4Bh1D/vYFJJ/ZGQtdUi6THOXpOR/4Y5VIwGnIXXYg5twMj5f
ozKfk7dvJLJj66RAsUFFUvZQ3oiIY44fgVckmmnq6p9Akn7cyaNl6kAL1N17UFsF
PleXp0pHJMuhpIC+YIxDILowJ+1VAtJcJSdPVbxsq4vtRB2mi6dnSUdenMFBa2uo
McGYhLNFDwjxCnTswoVhrQ3Y233PPsDc/ftb0IIwn6xQod7X5YVD48SP49nkeQH8
p2bROf2bsCE5NYd52x8vd6kOCpU6S5GdhM188J+t8U3piy502ww5r3oKaJGQFFtX
7xYsXSgYdPnHyQSETECxTPM/BsJPcqTUNlK9yghVGGqUTlhl9ma4JX7EwVk058nB
9QzBctKTLs6BBDt8l/FVlkzVHVrcJbSkfW9X83At+qQ2fLpvZcNhsYIjZA/COExH
+E/GuCBfVlbnij6L1vHq6gZNh9ISOu3ScoWzwuaL94/PMh6WXknJCSCDL5qQGNSR
VH+THfXAqJFpeKho7LhDA6lzYmFmwou8qJVi+8JXvLhLvuxz7WjdOVoosvCG9xwX
UPB/nHIaWJEP24jNF1K1pdqjityEX0QiqwFuQafCYmoO1S7vB9MSEj5eOINeTRoF
1XO3lr7sXS21r7mXcrPbC8eoEkCimJRJe9HYTDYlHdxQrKKyHMoSyNAAF4Q4DJU/
Abexx/g44PFNdVNZIOzl8xXZKuq3he4j7oWsMLbKbUV00kZpDQX7ctViw8ad9IeX
sOmPieUZHTj743V4u5UEKtGgqi6iMTJ5ACJ+flVstNJBBvQq8QfwhVH1cbiVgcXN
aPghveBy9WeVnbblGBqMw8aeLu3Z4IkOqvUkZDYdLKqIsKGJ1Rkuteyipw3txjGz
o3IgfhmQ3zE/B+pvG1dTfMqY5kEc2Gey+E0CxYPOThYrBf8ZMJM3KcUF2cbZGucU
lxSFSs1fATwSsZ2CRi0MlwN/nQgYZ77Hm7BAMq/xsqCiaoDQbA24r6jHNOr556hf
BqILbsTM/Up5l/g8plw4q4YA1r9sjanuy3vU0icSvK6yJNezmc6HhA8CPIXzNyck
iH3ppxJYBso5qPZ5GXKROTF/Y+PfaCksuMxD2ZvrlL2TEDfV3NozAUA8rWtoRlvU
ZjHmG0tu4QjAhzYMAY6u/gzd7AJB8WBFKShLAFBei10nM6xnqQq/fzeFN4XW81PL
bTqSl5um0F00Hf2qMsqYfQfa+fV+RQSSUh1Bx+H1P6SEEE7AVPcO0w3V8vp+5jma
hBEYmhXf8UiggdXmOtj2CRXl7tkDus8yzpvd+7oXDgnMBGXJR4wthiypg4zTBTs/
G1GiFyRVfIeyK/ijBDwjXwWXMNNRSozTKCqo6aKlw+xuv3vLTcgPCC4/YHJDPcZs
bcEnBPmeBS2Cvs+mqLq6ftMPpVy+SimLIy6BF8nmzBy/B6afkT1b9dfZka7V6uOc
Fct/DDRRL2dvWN+89z7a0UuJk8RRgieutcEOperbpVVX6q6VmFwBkrP8aSPyuYwG
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Cn6fdzmbH4OTqesLnVB2iw==
`pragma protect end_protected

//pragma protect end


`timescale 1 ns / 1 ns
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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ClhzyLguPuhYKmmMH5pY2eK1SCbKz3An/GRoz/P7X/ypPQZohUmShp8tlRm6gp/a
uyIx77AR2fQHOYEnw/W3/xXMd5DTEr7SjROVix4qh6ZIzkSGux8PEeP8CRxyDhLI
fd1kvH9SOV2tizD9KcmqNdhltkctU064qx+WNideafFSLn0GLJh4u2x3xr5ass4S
Ze4KiF72tDSfxOf0NR0v41w4YXj3pqQByrUEHegYst+hrhnDWwnKMgc2kABVLb3z
2RnY0694N3XWXKJNPYYgGw==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2592 )
`pragma protect data_block
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+wy/e9aITfGdB02/M8bBr1YVEPxiioArqYpVpMyKEnIzq0ONKTAejzSUGTL/+aBH
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uvuFCk1op/RjBj8HomiVINdLmf7FGn0azJ0B63oc5hZTFEdxhWu3BvzOwwgDiMmn
HAy593OLN3+Hd9Ir75tsGfpi4WQTBIA0oJJDX83rD1FsCUxXTEMBjLj+0cwfXl24
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m464qTvFKU0lStElerrtY7XJhg5BiEs1R+vx6QcW+aih+C97p7LzCsgZkwJ3I9xW
B1IP/id/CjFhXEQrOP/XgyX4Ie1PdQmyraAx/5Ihvm6fofBQyqpE4tzm8LTXnspu
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89DHJuBsd3UAqSKUzoT9MjYT6Gb129rjxiYTx+BABXvRfdYSyIwZ9qrFSHatNrkw
O+UJaAoxlgdxgvoF+/t6I2XlRWLId0obW4DQJ0J7SclzRzrsfOydEZpML7TyBic3
oQGydaCZ8ooMvqWJBCZ5lx//z7A9gCxnjsQ4mHQUHT81YtDQLXl2wBQeernd1rK6
rIbOsvriQa+x8F40c/Tj7wBd7RcJv3O5Xpf6WVJtJFpFfXaySWFuJtnvdTMsz8yI
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xJEufR82cZRIOfbdQeUHw2CraiEtA6wtBl2knadX1BPOx1mSQafDyERZjOtHX5xn
`pragma protect end_protected

//pragma protect end


`timescale 1 ns / 1 ns
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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gdKqDKF71HzDfMD+9yQouaN6jQP3trMCJ3i9QxH2MjGH6wo5f5NGw1nRw7rvKy0D
Jdvss6dCOolCvt4e37dvfWOjFKoZBF/NSDE+lgQAg92wtaI4XIRk8AwLMX50G9xb
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cL9RSCI3ynpv7eQZTe8qeQ==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 16240 )
`pragma protect data_block
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kODikgX9H24JKf/FHKOb5KrU+LBKt77mVG4QYy6Y5aeLdNMeoM3uLIghm9lI3T7p
ZzHcJ8gQh9nnQ5WTXh/TY7Al/R8IaATyKfs77w/fmvFDYrIvpaU/Ny5y1OacROc+
K4Twuf5yECkc4jpL4N39ap6f3RchaOuRsswvmL/vkhny4EwfK9+vEgeD7El3bFKV
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s80l/2g05T0WTB+EZsR5vw==
`pragma protect end_protected

//pragma protect end


`timescale 1 ns / 1 ns
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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adrGmFWXAsiHrqjClUk8CESEBOpgFFuvhMVinWd3sBtPUVMzPLDqgF71+p2YQhVO
RJ3gZR89rzHxB7sm4/JaSw==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 10080 )
`pragma protect data_block
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`pragma protect end_protected

//pragma protect end


`timescale 1 ns / 1 ns
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 18720 )
`pragma protect data_block
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`pragma protect end_protected

//pragma protect end


`timescale 1 ns / 1 ns
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5408 )
`pragma protect data_block
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`pragma protect end_protected

//pragma protect end


`timescale 1 ns / 1 ns
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 7200 )
`pragma protect data_block
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VgmjCvg/tub/eNMcYSN3dbLBa2U8LGkiqi23sOKyQUsp61jv2vkpQk0qlQodcM9O
HMstqz0HXMO3D1Z9M2JQroN3CtaDAujIYl4jd34Xf6jR4t4tIIiLkdF/z0K/hub4
zqrvonI025k6HxfyFAMNVrR9uStlXAiQBRl0pLErXR2iA07mguU0Pf4cBnGMQ1c7
Yv2VAWyK9/5ZmA4AcL8qqZPZQ6i5j0h+i4fYPJV5GZGp6zFLB78SnbNDAc96Go+G
2SfOxGV0t60cukMfVDOUGoqDSW5KSSD8taN3Dv8Qr4NoI+0HSWKuWiKYyUgweYMo
4PFSUmSoEgQxj8dDGr88tp2gy8mtqGmMjas1zXmpxkf6iyDGbyFSIiRGn4JhJXQD
8G1qLgEDZ7rmQ+8GhqJogsHITX/F24grH9QQoxZY7wEKkorq2KoCD1s0RcY7YqBp
iHql8GZlMHTe+aRMKuvEg5810OurW5pqVSal1qTfXS3/MsQ5PDe44ZCgic3rCZTz
SKP82qarbXXkUMCIoT3ImVlrmEdTezGE+RtJzDhAkaL3WrQkn+2i5y+986YeIveL
cc9/3NlxJhyD/TjIp8dClpQhJhQK/dtzHQvPKzmx97Gd8VN2RNpX8K9UsPbffDzJ
srBEU8h8uyufo5ZuDrMaPCLRj4UP4A3FmD0efPV9mN+fZPhweCGNc6FbXbysceoJ
nf+CvgmBTsM6iOsN1sDemPl6cpBPVGuOeoJr6jDezwrDbZ+SLdeG+qw8QeHZ7hKK
k8/psyzmTqC0QYtOjAwuvzt9VRAe7GLa4A6PqX9E4GHtnD/RPgLdU92wEHdiAV87
vPFEqsPUdmfyv7PC00Yi6K47wWuJXw1gsdUvvIAiatMUz/CrP68QgY7tmrY1/AN/
Ml02NaPK3Uqi3tGQ9es0UsGZr0ki92Bd55LNyXpmK3Y82EDcR6QOXOB0icQlwEHZ
C2/8wvF1GVdvWcoUo0kA6m9uA/jTUG79m+4w7+40LP8v6iE2XEOtKhtsUJ1taDH4
nK+686h5Y57OiH5mwDPBSd1ywyIw2Oot4ZeWXwnwyqZ9scaU6/VOxKsmLTl4PhH+
C8anQNkbKoc66IE6j8T9vjRYJ0ncrj3yhKWnwJos7niWE9/OUA1arKBsq4ORGZMB
gYTCb536C39BSD1rt6zYE6KZf4i+JXVUeXpDpJD7u/S2fvM+686UDzgFdbfDnXKu
`pragma protect end_protected

//pragma protect end


`timescale 1 ns / 1 ns
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
oBC1JdAyL3G9dogmZ8wm5xXsy+1ioPaKz++j7wgPFk2PEGJ8+C9pci2xMUFllzjU
Q3IPMgJpybU05yLUEGdzgz7C5cjXNg1ELtNPy667iOfNDVXoaey4/ZE7GXFs0tXI
HsLD6WMTm872awF70y8Lhcg/YJQUnK3RdmJU9e8QPJm2ZIkXU+hBRe8lnWcSS7fa
A8jBmPGBs4Z3KZz1tiZT+wXr++poyS5UF3DufpSJZ24n7rgWULIub4rZ2OgGGTv7
zqIIQ8vt5QB4WIp6sNL+EdUMpKLNl8wqwCPcbVqMDTSG8fB+w6Y86/StB4/0VnzG
oWhXFCpM5SWSb3h7w2Zklg==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 3408 )
`pragma protect data_block
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bzD3LnGc/rZwTZY/hpX+Tsltp0nCBL6AWIrTe7JLdTOaOHKknK6mSUai2J99eK6m
Y4qIUFuLLgjubE59/7J8MAGGF81cpYLSylHWcibf6FAjg5Dvxi7l0Ygsb2xPpbHW
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QUGFx+yIZ1Ouq868yh2YzzmP5gOOblWezUaFWpXVDwyGFRfRhv5xe4I2Nsz+4maZ
G20XdrCkkF/ips7ykp09jugHy69TArBt3y2wIutXdCWucbWdng0Siq3UxrY7aoK6
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90rvQ3qkC9wp0ECV62kdZRfRettsYQ8ar4qJ4mQvyQYnMZVMXcuOLhQQHo1M/TgG
aUGON6ygqgr7DJYsVyAt52OsXlh0UTFyKAQqElqkuU88QsMDiRhrxIr60j5wEnQU
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JTetsg3T8J/eyfGmXC75curFkVzLAU18Je2UeMPYmZKfHtINr9c8uYCkXBUicpnt
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157htNeTM6uFPk19+9L/92hZE19+atuiplk1/I0/BMSdhd1l+ZK9Xscoad7y25Gh
gm/RRze4bpkSVO0nmXT2tlcYVyqwo88UfMleiKvLBrUfLpE93PDfQVJ273DHZ9QJ
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dW+mCkQxWDciXQL7/iFMdnE5Wk38Zaf+mzdZeGFLY+Ojko7vUKfeiQkTRhodnK3h
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AKY6pv9Z2tPMYqsw55YG7Jxc3XkLMOUajUsgzSgbeXou5ZKLHA3wleL9EGjWG45x
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f/gJQejf410TBJ0728N9T8UNJH0imK6LxYXhWjWCgG2P8gSvYIeu+LPYkaAxrUkX
C+l3W84nVVSx88BS0b8Pg9F9ASuAqIHojjKjhiGpmjmlK8tTD5Y8MMGNcZl6CIXw
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iemU40OnAOUrltVkFGAtV2N5x4SNzHwkcbOX4XsyAZnrsTZvOeZrW3Dpk+ORtilo
`pragma protect end_protected

//pragma protect end


`timescale 1 ns / 1 ns
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
SZ/cX4PWnj7/W6jbGkuVhAtVuayCxRBZUQNYEIFFzgvsEXNZ8gKM3PzVdD1nb2rO
1eXlZAsj6Vxj4c1S7YdO/FRhktkICaC2znr5voi3hZok11yoofb+x6nSBWyjaYhG
Az8nKAHG4j/NnK2dZyW2VrW2M8MaRXKejAtsK7RfJrskd330aSx4AMD68vgejH0X
hmDsRakS2UQjs99fZRlBGT32+W5fCtvvZtb7Klb6z6vfJWDSC8f0dtyaI84mriiE
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FMj8c1C/yWOsFjKtOYeEYg==
`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 22400 )
`pragma protect data_block
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N1otEOjKPQoRPNsz3N3vzBBKK12Y5e45Z+vCYGqRa70x26qnawobhRNGB+tfMLO4
oGFCcDHVFn4y1tUoF15Y1AyXVSyUgeQlDAwR7DPCck7gJC/QjAK37R90po2yFUx2
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`pragma protect end_protected

//pragma protect end


`timescale 1 ns / 1 ns
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 17520 )
`pragma protect data_block
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`pragma protect end_protected

//pragma protect end


`timescale 1 ns / 1 ns
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 19456 )
`pragma protect data_block
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`pragma protect end_protected

//pragma protect end


`timescale 1 ns / 1 ns
//pragma protect
//pragma protect begin

/* Encryption Envelope */

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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`pragma protect data_method = "aes256-cbc"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4160 )
`pragma protect data_block
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BBq3G8mPW7u0HAcr50lSX2/vzrEGy2yU8STGU+pT4zoVw6hODXi+yPZWnAMwSzch
3phcAJyyBDfqgGAx7jkINbynwf55+xPWgMKVLSbQKF5zbRYglATZsuIx5uhvj3Fb
fv1bM5h1DyDTGC7gSqF76qqGphD2V8kb54UlIPNuoNy5KlJFs+3TStHNsIpF7HBo
YVMY35ucJRk6uQMZ1cTpr+kcvvJ+ueTiG9juC+Xt9E9PToJ3szW8SfIYie2UDr3a
FCqM5vLOZayg/JxvOzrA9JNW2we+LA6JJ3xJPxqs4LH9MyKpUOeHBlHM/I+pQaMF
jT3qd1tEK0SYsiJL5wz9hv9ImGLqYnAQdoMoVbfJALhsX2E3leesZnDtedBFgL0B
HTvWuEIAcNBfVkWlwQbxAVlGP0eu/bM+36zXKKdoBrnegfiziJFSF9yMFFjPRgmk
YR1Kb4riPiLe5HZ0GpFKMeaZZZ1tZILdto8PaoJZHa0UX+ZUbh5ANB+FIF7NyHLC
bDuBYYLPdNrb4zeofNU3hIhpAFGSu95agFijCXfuIe3AVvYVfcqfXePO4ucAFNs7
zSq6x7Hu5GFKkGKwH2zOJ9ms2gOaQ2NvQUJwHC9cTrbr1RHa7bfBgeRAnZDG/1wB
pTg0Kh7VsM+fqRoHx6AvH2qCdCbAo8CZfy44uzR9Z6o=
`pragma protect end_protected

//pragma protect end


`timescale 1 ns / 1 ns
module mii_if_4baff3c4bcd643d4ace07f79d93bbfaa
(
//Globle Signals
input                           tx_mac_aclk,
output  reg                     tx_mac_aclk_en,
input                           tx_reset,
output  wire                    rx_mac_aclk,
output  reg                     rx_mac_aclk_en,
input                           rx_reset,
//Configuration Signals
input           [2:0]           eth_speed,
//GMII Interface
output  reg     [7:0]           gm_rx_d,
output  reg                     gm_rx_dv,
output  reg                     gm_rx_err,
input           [7:0]           gm_tx_d,
input                           gm_tx_en,
input                           gm_tx_err,
//MII Interface
input                           mii_txc,
output  reg     [3:0]           mii_txd,
output  reg                     mii_tx_dv,
output  reg                     mii_tx_err,

input                           mii_rxc,
input           [3:0]           mii_rxd,
input                           mii_rx_dv,
input                           mii_rx_err

//Status and  Error Signals
);
// Parameter Define 
//localparam                      SPEED_100M_DIV = (TX_REFCLK == 125) ? 10 : 2;
//localparam                      SPEED_10M_DIV  = SPEED_100M_DIV*10;
//localparam                      SPEED_CLK_DIV = (TX_REFCLK == 125) ? SPEED_100M_DIV/2 + 1 : 0 ;
// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [3:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg                             rx_dv_pre;
reg                             rx_dv_dl1;
reg     [3:0]                   rxd_pre;
reg     [3:0]                   rxd_dl1;
reg                             rx_odd_data_ptr;
reg     [3:0]                   rxd;
reg                             rx_dv;
reg                             rx_er;
reg     [3:0]                   gm_tx_d_h;
reg     [7:0]                   gm_tx_d_r;
reg                             gm_tx_en_r;
reg                             gm_tx_err_r;
reg				preamble_flg;
reg     [1:0]			cur_st;
reg     [1:0]			nxt_st;
reg				add_preamble;

// Wire Define

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- Tx Region ----------------------------*/

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        tx_mac_aclk_en <= 1'b0;
    else
        tx_mac_aclk_en <= ~tx_mac_aclk_en;
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        gm_tx_d_r <= 8'h0;
    else if((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
        gm_tx_d_r <= gm_tx_d;
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        gm_tx_en_r <= 1'b0;
    else if(tx_mac_aclk_en == 1'b1)
        gm_tx_en_r <= gm_tx_en;
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        gm_tx_err_r <= 1'b0;
    else if(tx_mac_aclk_en == 1'b1)
        gm_tx_err_r <= gm_tx_err;
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txd <= 4'h0;
    else if(gm_tx_en_r == 1'b1) 
        begin
            if(tx_mac_aclk_en == 1'b0)
                txd <= gm_tx_d_r[3:0];
            else
                txd <= gm_tx_d_r[7:4];
        end
    else;    
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        tx_en <= 1'b0;
    else 
        tx_en <= gm_tx_en_r;
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        tx_er <= 1'b0;
    else 
        tx_er <= gm_tx_err_r;
end

always @(posedge mii_txc)
begin 
    mii_tx_dv  <= tx_en;
    mii_txd    <= txd[3:0];
    mii_tx_err <= tx_er;
end
/*----------------------- Rx Region ----------------------------*/
always @(posedge mii_rxc)
begin
   if(mii_rxd==4'hd && mii_rx_dv && !mii_rx_err && cur_st==2'b01 && preamble_flg)
   begin
      rxd   <= 4'h5;
      rx_dv <= 1'b1;
   end
   else if(add_preamble)
   begin
      rxd <= rxd_pre;
      rx_dv <= rx_dv_pre;
   end
   else
   begin
      rxd   <= mii_rxd;
      rx_dv <= mii_rx_dv;
      rx_er <= mii_rx_err;
   end
end

assign rx_mac_aclk = mii_rxc;

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
	begin
	rxd_pre <= 4'h0;
	rx_dv_pre <= 1'b0;
	end
    else if((mii_rxd==4'hd && mii_rx_dv && !mii_rx_err && cur_st==2'b01 && preamble_flg) || add_preamble)
	begin
	rxd_pre <= mii_rxd;
	rx_dv_pre <= mii_rx_dv;
	end
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
	add_preamble <= 1'b0;
    else if(mii_rxd==4'hd && mii_rx_dv && !mii_rx_err && cur_st==2'b01 && preamble_flg)
	add_preamble <= 1'b1;
     else if(!mii_rx_dv)
	add_preamble <= 1'b0;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_mac_aclk_en <= 1'b0;
    else
        rx_mac_aclk_en <= ~rx_mac_aclk_en;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
	begin
		cur_st <= 2'b00;
	end
     else
	begin
		cur_st <= nxt_st;
	end
end

always @*
begin
case(cur_st)
2'b00: begin
	if(mii_rxd==4'h5 && mii_rx_dv && !mii_rx_err)	
	nxt_st <= 2'b01;
	else
	nxt_st <= 2'b00;
       end
2'b01: begin
	if(mii_rxd==4'hd && mii_rx_dv && !mii_rx_err)
	nxt_st <= 2'b10;
	else if (mii_rxd==4'h5 && mii_rx_dv && !mii_rx_err)
	nxt_st <= 2'b01;
	else 
	nxt_st <= 2'b00;
	end
2'b10: begin
	if(mii_rx_dv) 
	nxt_st <= 2'b10;
	else
	nxt_st <= 2'b00;
	end
default: nxt_st <= 2'b00;
endcase
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        begin
            preamble_flg <= 1'b0;
	end
    else if(mii_rxd==4'h5 && mii_rx_dv && !mii_rx_err && cur_st==2'b01)
	begin
	    preamble_flg <= ~preamble_flg;
	end
    else begin
	    preamble_flg <= 1'b0;
	end
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        begin
            rx_dv_dl1 <= 1'b0;
            rxd_dl1 <= 4'h0;
        end
    else
        begin
            rx_dv_dl1 <= rx_dv;
            rxd_dl1 <= rxd;
        end
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_dv <= 1'b0;
    else
        gm_rx_dv <= rx_dv_dl1;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_odd_data_ptr <= 1'b0;
    else if(rx_dv == 1'b0)
        rx_odd_data_ptr <= 1'b0;
    else
        rx_odd_data_ptr <= ~rx_odd_data_ptr;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_d <= 8'h0;
    else if((rx_dv == 1'b1) && (rx_odd_data_ptr == 1'b1))
        gm_rx_d <= {rxd[3:0],rxd_dl1[3:0]};
    else;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_err <= 1'b0;
    else
        begin
            if(rx_er == 1'b1)
                gm_rx_err <= 1'b1;
            else if(rx_mac_aclk_en == 1'b1)
                gm_rx_err <= 1'b0;
        end
end


endmodule



//////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// ********************************
// Revisions:
// 1.0 Initial rev 
//
// *******************************

`timescale 1 ns / 1 ns
module `IP_MODULE_NAME(tsemac) #(
    parameter    VERSION = 32'h10,
    parameter    RXFIFO_EN = 1,
    parameter    RXFIFO_DTH = 2048,
    parameter    TXFIFO_EN = 1,
    parameter    TXFIFO_DTH = 2048,
    parameter    PHY_INTF_MODE = 0,  //0-rgmii_4baff3c4bcd643d4ace07f79d93bbfaa, 1-mii, 2-rmii, 3-gmii
    parameter    AXIS_DW = 8,  // 8, 16, or 32
    parameter    RGMII_RXC_EDGE = 1,
    parameter 	 RGMII_TXC_DLY = 1,
    parameter    SIP600 = 1'b0  // For Internal-use
)
(
//Globle Signals
input                           mac_reset,//Globle Reset
input                           proto_reset,//Tx & Rx Reset
input                           tx_mac_aclk,//125M 
output  wire                    rx_mac_aclk,
output  wire    [2:0]           eth_speed,
//Receive AXI4-Stream Interface
input                           rx_axis_clk,
output  wire    [AXIS_DW-1:0]   rx_axis_mac_tdata,
output  wire                    rx_axis_mac_tvalid,
output  wire                    rx_axis_mac_tlast,
output  wire    [AXIS_DW/8-1:0] rx_axis_mac_tstrb,
output  wire                    rx_axis_mac_tuser,
input                           rx_axis_mac_tready,
//Transmit AXI4-Stream Interface
input                           tx_axis_clk,
input           [AXIS_DW-1:0]   tx_axis_mac_tdata,
input                           tx_axis_mac_tvalid,
input                           tx_axis_mac_tlast,
input           [AXIS_DW/8-1:0] tx_axis_mac_tstrb,
input                           tx_axis_mac_tuser,
output  wire                    tx_axis_mac_tready,
//AXI4-Lite Interface
input                           s_axi_aclk,//AXI Bus Clock.
input           [9:0]           s_axi_awaddr,//Write Address. byte address.
input                           s_axi_awvalid,//Write address valid.
output  wire                    s_axi_awready,//Write address ready.
input           [31:0]          s_axi_wdata,//Write data bus.
input                           s_axi_wvalid,//Write valid.
output  wire                    s_axi_wready,//Write ready.
output  wire    [1:0]           s_axi_bresp,//Write response.
output  wire                    s_axi_bvalid,//Write response valid.
input                           s_axi_bready,//Response ready.
input           [9:0]           s_axi_araddr,//Read address. byte address.
input                           s_axi_arvalid,//Read address valid.
output  wire                    s_axi_arready,//Read address ready.
output  wire    [1:0]           s_axi_rresp,//Read response.
output  wire    [31:0]          s_axi_rdata,//Read data.
output  wire                    s_axi_rvalid,//Read valid.
input                           s_axi_rready,//Read ready.              
//MDIO Interface
output  wire                    Mdo,//MII Management Data Output
output  wire                    MdoEn,//MII Management Data Output Enable
input                           Mdi,//MII Management Data Input
output  wire                    Mdc,//MII Management Data Clock 

//RGMII Interface
output  wire    [3:0]           rgmii_txd_HI,
output  wire    [3:0]           rgmii_txd_LO,
output  wire                    rgmii_tx_ctl_HI,
output  wire                    rgmii_tx_ctl_LO,
output  wire                    rgmii_txc_HI,
output  wire                    rgmii_txc_LO,
input           [3:0]           rgmii_rxd_HI,
input           [3:0]           rgmii_rxd_LO,
input                           rgmii_rx_ctl_HI,
input                           rgmii_rx_ctl_LO,
input                           rgmii_rxc,

//MII Interface
input                           mii_txc,
output  wire    [3:0]           mii_txd,
output  wire                    mii_tx_dv,
output  wire                    mii_tx_err,
input                           mii_rxc,
input           [3:0]           mii_rxd,
input                           mii_rx_dv,
input                           mii_rx_err,

//RMII Interface
input                           rmii_clk_ref,
output  wire    [1:0]           rmii_txd,
output  wire                    rmii_tx_en,
input           [1:0]           rmii_rxd,
input                           rmii_crs_dv,
input                           rmii_rx_err,

//GMII Interface
input                           gm_rx_c,
input           [7:0]           gm_rx_d,
input                           gm_rx_dv,
input                           gm_rx_err,
output  wire                    gm_tx_c,
output  wire    [7:0]           gm_tx_d,
output  wire                    gm_tx_en,
output  wire                    gm_tx_err
);

// Parameter Define 

// Register Define 

// Wire Define 
wire                    tx_mac_aclk_en;
wire                    rx_mac_aclk_en;
wire                    tx_mac_aclk_int;

//GMII Interface
wire    [7:0]           gm_rx_d_int;
wire                    gm_rx_dv_int;
wire                    gm_rx_err_int;
wire    [7:0]           gm_tx_d_int;
wire                    gm_tx_en_int;
wire                    gm_tx_err_int;

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/
generate if (PHY_INTF_MODE == 0) begin
    assign tx_mac_aclk_int = tx_mac_aclk;
end
else if (PHY_INTF_MODE == 1) begin
    assign tx_mac_aclk_int = mii_txc;
end
else if (PHY_INTF_MODE == 2) begin
    assign tx_mac_aclk_int = rmii_clk_ref;
end
else begin
    assign tx_mac_aclk_int = tx_mac_aclk;
end
endgenerate


/*----------------------- The Tri-mode Ethernet MAC core -----------------------*/
`IP_MODULE_NAME(tsemac_core) #(
    .VERSION    (10),
    .RXFIFO_EN  (RXFIFO_EN),
    .RXFIFO_DTH (RXFIFO_DTH),    
    .TXFIFO_EN  (TXFIFO_EN),
    .TXFIFO_DTH (TXFIFO_DTH),
    .AXIS_DW    (AXIS_DW),
    .SIP600     (SIP600) 
)
u_tse_mac
(
//Globle Signals
    .mac_reset                          (mac_reset                          ),
    .proto_reset                        (proto_reset                        ),
    .tx_mac_aclk                        (tx_mac_aclk_int                    ),
    .rx_mac_aclk                        (rx_mac_aclk                        ),
    .tx_mac_aclk_en                     (tx_mac_aclk_en                     ),
    .rx_mac_aclk_en                     (rx_mac_aclk_en                     ),
    .eth_speed                          (eth_speed                          ),
//Receive AXI4-Stream Interface 
    .rx_axis_clk                        (rx_axis_clk                        ),
    .rx_axis_mac_tdata                  (rx_axis_mac_tdata                  ),
    .rx_axis_mac_tvalid                 (rx_axis_mac_tvalid                 ),
    .rx_axis_mac_tlast                  (rx_axis_mac_tlast                  ),
    .rx_axis_mac_tstrb                  (rx_axis_mac_tstrb                  ),    
    .rx_axis_mac_tuser                  (rx_axis_mac_tuser                  ),
    .rx_axis_mac_tready                 (rx_axis_mac_tready                 ),
//Transmit AXI4-Stream Interface
    .tx_axis_clk                        (tx_axis_clk                        ),
    .tx_axis_mac_tdata                  (tx_axis_mac_tdata                  ),
    .tx_axis_mac_tvalid                 (tx_axis_mac_tvalid                 ),
    .tx_axis_mac_tlast                  (tx_axis_mac_tlast                  ),
    .tx_axis_mac_tstrb                  (tx_axis_mac_tstrb                  ),    
    .tx_axis_mac_tuser                  (tx_axis_mac_tuser                  ),
    .tx_axis_mac_tready                 (tx_axis_mac_tready                 ),
//GMII Interface
    .gm_rx_d                            (gm_rx_d_int                        ),
    .gm_rx_dv                           (gm_rx_dv_int                       ),
    .gm_rx_err                          (gm_rx_err_int                      ),
    .gm_tx_d                            (gm_tx_d_int                        ),
    .gm_tx_en                           (gm_tx_en_int                       ),
    .gm_tx_err                          (gm_tx_err_int                      ),
//AXI4-Lite Interface
    .s_axi_aclk                         (s_axi_aclk                         ),
    .s_axi_awaddr                       (s_axi_awaddr                       ),
    .s_axi_awvalid                      (s_axi_awvalid                      ),
    .s_axi_awready                      (s_axi_awready                      ),
    .s_axi_wdata                        (s_axi_wdata                        ),
    .s_axi_wvalid                       (s_axi_wvalid                       ),
    .s_axi_wready                       (s_axi_wready                       ),
    .s_axi_bresp                        (s_axi_bresp                        ),
    .s_axi_bvalid                       (s_axi_bvalid                       ),
    .s_axi_bready                       (s_axi_bready                       ),
    .s_axi_araddr                       (s_axi_araddr                       ),
    .s_axi_arvalid                      (s_axi_arvalid                      ),
    .s_axi_arready                      (s_axi_arready                      ),
    .s_axi_rresp                        (s_axi_rresp                        ),
    .s_axi_rdata                        (s_axi_rdata                        ),
    .s_axi_rvalid                       (s_axi_rvalid                       ),
    .s_axi_rready                       (s_axi_rready                       ),
//MDIO Interface
    .Mdo                                (Mdo                                ),
    .MdoEn                              (MdoEn                              ),
    .Mdi                                (Mdi                                ),
    .Mdc                                (Mdc                                )
);

/*----------------------- Physical Interface Region ----------------------------*/
generate 
if (PHY_INTF_MODE == 0) begin
    rgmii_if_4baff3c4bcd643d4ace07f79d93bbfaa u_rgmii_if
    (
    //Globle Signals
        .tx_mac_aclk                        (tx_mac_aclk                        ),
        .tx_mac_aclk_en                     (tx_mac_aclk_en                     ),
        .tx_reset                           (mac_reset || proto_reset           ),
        .rx_mac_aclk                        (rx_mac_aclk                        ),
        .rx_mac_aclk_en                     (rx_mac_aclk_en                     ),
        .rx_reset                           (mac_reset || proto_reset           ),
    //Configuration Signals                                                     
        .eth_speed                          (eth_speed                          ),
        .rgmii_rxc_edge                     (RGMII_RXC_EDGE                     ),
        .rgmii_txc_dly                      (RGMII_TXC_DLY                      ),
    //GMII Interface                                                            
        .gm_rx_d                            (gm_rx_d_int                        ),
        .gm_rx_dv                           (gm_rx_dv_int                       ),
        .gm_rx_err                          (gm_rx_err_int                      ),
        .gm_tx_d                            (gm_tx_d_int                        ),
        .gm_tx_en                           (gm_tx_en_int                       ),
        .gm_tx_err                          (gm_tx_err_int                      ),
    //RGMII Interface                                                           
        .rgmii_txd_HI                       (rgmii_txd_HI                       ),
        .rgmii_txd_LO                       (rgmii_txd_LO                       ),
        .rgmii_tx_ctl_HI                    (rgmii_tx_ctl_HI                    ),
        .rgmii_tx_ctl_LO                    (rgmii_tx_ctl_LO                    ),
        .rgmii_txc_HI                       (rgmii_txc_HI                       ),
        .rgmii_txc_LO                       (rgmii_txc_LO                       ),
        .rgmii_rxd_HI                       (rgmii_rxd_HI                       ),
        .rgmii_rxd_LO                       (rgmii_rxd_LO                       ),
        .rgmii_rx_ctl_HI                    (rgmii_rx_ctl_HI                    ),
        .rgmii_rx_ctl_LO                    (rgmii_rx_ctl_LO                    ),
        .rgmii_rxc                          (rgmii_rxc                          )
    );
end
else if (PHY_INTF_MODE == 1) begin
    mii_if_4baff3c4bcd643d4ace07f79d93bbfaa u_mii_if
    (
    //Globle Signals
        .tx_mac_aclk                        (mii_txc                            ),
        .tx_mac_aclk_en                     (tx_mac_aclk_en                     ),
        .tx_reset                           (mac_reset || proto_reset           ),
        .rx_mac_aclk                        (rx_mac_aclk                        ),
        .rx_mac_aclk_en                     (rx_mac_aclk_en                     ),
        .rx_reset                           (mac_reset || proto_reset           ),
    //Configuration Signals                                                     
        .eth_speed                          (eth_speed                          ),
    //GMII Interface                                                            
        .gm_rx_d                            (gm_rx_d_int                        ),
        .gm_rx_dv                           (gm_rx_dv_int                       ),
        .gm_rx_err                          (gm_rx_err_int                      ),
        .gm_tx_d                            (gm_tx_d_int                        ),
        .gm_tx_en                           (gm_tx_en_int                       ),
        .gm_tx_err                          (gm_tx_err_int                      ),
    //MII Interface                                                           
        .mii_txc                            (mii_txc                       ),
        .mii_txd                            (mii_txd                       ),
        .mii_tx_dv                          (mii_tx_dv                     ),
        .mii_tx_err                         (mii_tx_err                    ),
        .mii_rxc                            (mii_rxc                       ),
        .mii_rxd                            (mii_rxd                       ),
        .mii_rx_dv                          (mii_rx_dv                     ),
        .mii_rx_err                         (mii_rx_err                    )
    );
end
else if (PHY_INTF_MODE == 2) begin
    rmii_if_4baff3c4bcd643d4ace07f79d93bbfaa u_rmii_if
    (
    //Globle Signals
        .tx_mac_aclk                        (rmii_clk_ref                       ),
        .tx_mac_aclk_en                     (tx_mac_aclk_en                     ),
        .tx_reset                           (mac_reset || proto_reset           ),
        .rx_mac_aclk                        (rx_mac_aclk                        ),
        .rx_mac_aclk_en                     (rx_mac_aclk_en                     ),
        .rx_reset                           (mac_reset || proto_reset           ),
    //Configuration Signals                                                     
        .eth_speed                          (eth_speed                          ),
    //GMII Interface   
        .gm_rx_d                            (gm_rx_d_int                        ),
        .gm_rx_dv                           (gm_rx_dv_int                       ),
        .gm_rx_err                          (gm_rx_err_int                      ),
        .gm_tx_d                            (gm_tx_d_int                        ),
        .gm_tx_en                           (gm_tx_en_int                       ),
        .gm_tx_err                          (gm_tx_err_int                      ),
    //MII Interface                                                           
        .rmii_clk_ref                       (rmii_clk_ref                      ),
        .rmii_txd                           (rmii_txd                          ),
        .rmii_tx_en                         (rmii_tx_en                        ),
        .rmii_rxd                           (rmii_rxd                          ),
        .rmii_crs_dv                        (rmii_crs_dv                       ),
        .rmii_rx_err                        (rmii_rx_err                       )
    );
end
else if (PHY_INTF_MODE == 3) begin
    wire g_reset;
    reg rx_mac_aclk_en_int, tx_mac_aclk_en_int;
    
    assign rx_mac_aclk = gm_rx_c;
    assign g_reset = mac_reset || proto_reset;
    assign rx_mac_aclk_en = rx_mac_aclk_en_int;
    assign tx_mac_aclk_en = tx_mac_aclk_en_int;

    always @(posedge rx_mac_aclk or posedge g_reset)
    begin
        if(g_reset == 1'b1)
            rx_mac_aclk_en_int <= 1'b0;
        else
            rx_mac_aclk_en_int <= 1'b1;
    end
    
    always @(posedge tx_mac_aclk or posedge g_reset)
    begin
        if(g_reset == 1'b1)
            tx_mac_aclk_en_int <= 1'b0;
        else
            tx_mac_aclk_en_int <= 1'b1;
    end
    
    assign gm_rx_d_int   = gm_rx_d;
    assign gm_rx_dv_int  = gm_rx_dv;
    assign gm_rx_err_int = gm_rx_err;
    assign gm_tx_d       = gm_tx_d_int;
    assign gm_tx_en      = gm_tx_en_int;
    assign gm_tx_err     = gm_tx_err_int;
    assign gm_tx_c       = tx_mac_aclk;
end
endgenerate 

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

`timescale 1 ns / 1 ns
module rgmii_if_4baff3c4bcd643d4ace07f79d93bbfaa#(
    parameter                       RGMII_SYNC_EN = 1
)
(
//Globle Signals
input                           tx_mac_aclk,
output  reg                     tx_mac_aclk_en,
input                           tx_reset,
output  wire                    rx_mac_aclk,
output  reg                     rx_mac_aclk_en,
input                           rx_reset,
//Configuration Signals
input           [2:0]           eth_speed,
input                           rgmii_rxc_edge,//0:DDIO Rising Edge; 1:DDIO Falling Edge; 
input                           rgmii_txc_dly,//0:rgmii_4baff3c4bcd643d4ace07f79d93bbfaa tx clock delay disable; 1:rgmii_4baff3c4bcd643d4ace07f79d93bbfaa tx clock delay enable;
//GMII Interface
output  reg     [7:0]           gm_rx_d,
output  reg                     gm_rx_dv,
output  reg                     gm_rx_err,
input           [7:0]           gm_tx_d,
input                           gm_tx_en,
input                           gm_tx_err,
//RGMII Interface
output  wire    [3:0]           rgmii_txd_HI,
output  wire    [3:0]           rgmii_txd_LO,
output  wire                    rgmii_tx_ctl_HI,
output  wire                    rgmii_tx_ctl_LO,
output  wire                    rgmii_txc_HI,//if rgmii_txc_dly set 0, used clk_125m clock. if rgmii_txc_dly set 1, used clk_125m_90deg clock.
output  wire                    rgmii_txc_LO,
input           [3:0]           rgmii_rxd_HI,
input           [3:0]           rgmii_rxd_LO,
input                           rgmii_rx_ctl_HI,
input                           rgmii_rx_ctl_LO,
input                           rgmii_rxc
//Status and  Error Signals
);

// Parameter Define 

// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [7:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg     [1:0]                   txc;
reg                             rx_dv_dl1;
reg     [7:0]                   rxd_dl1;
reg                             rx_odd_data_ptr;

// Wire Define
wire                            rx_dv;
wire    [7:0]                   rxd;
wire                            rx_er;

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- Tx Region ----------------------------*/
always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        aclk_en_cnt <= 7'd0;
    else if((eth_speed == 3'h4) ||
            ((eth_speed == 3'h2) && (aclk_en_cnt == 7'd9)) ||
            ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd99)))
        aclk_en_cnt <= 7'd0;
    else
        aclk_en_cnt <= aclk_en_cnt + 1'b1;
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        tx_mac_aclk_en <= 1'b0;
    else if(aclk_en_cnt == 7'd0)
        tx_mac_aclk_en <= 1'b1;
    else
        tx_mac_aclk_en <= 1'b0;
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txd[7:4] <= 4'h0;
    else if((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
        txd[7:4] <= gm_tx_d[7:4];
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txd[3:0] <= 4'h0;
    else if((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
        txd[3:0] <= gm_tx_d[3:0];
    else if(((eth_speed == 3'h2) && (aclk_en_cnt == 7'd6)) ||
            ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd51)))
        txd[3:0] <= txd[7:4];
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        tx_en <= 1'b0;
    else if(tx_mac_aclk_en == 1'b1)
        tx_en <= gm_tx_en;
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        tx_er <= 1'b0;
    else if(tx_mac_aclk_en == 1'b1)
        tx_er <= gm_tx_err;
end
/*
always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txc <= 2'b0;
    else
        case(eth_speed)
        3'h4 :
            txc <= 2'b01;
        3'h2 :
            case(rgmii_txc_dly)
            1'b0 ://rgmii_4baff3c4bcd643d4ace07f79d93bbfaa tx clock delay disable.
                if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd3) || (aclk_en_cnt == 7'd8))
                    txc <= 2'b00;
            1'b1 ://rgmii_4baff3c4bcd643d4ace07f79d93bbfaa tx clock delay enable.
                if((aclk_en_cnt == 7'd2) || (aclk_en_cnt == 7'd7))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                    txc <= 2'b00;
            endcase
        3'h1 :
            case(rgmii_txc_dly)
            1'b0 ://rgmii_4baff3c4bcd643d4ace07f79d93bbfaa tx clock delay disable.
                if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd50))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd25) || (aclk_en_cnt == 7'd75))
                    txc <= 2'b00;
            1'b1 ://rgmii_4baff3c4bcd643d4ace07f79d93bbfaa tx clock delay enable.
                if((aclk_en_cnt == 7'd13) || (aclk_en_cnt == 7'd63))
                    txc <= 2'b11;
                else if((aclk_en_cnt == 7'd38) || (aclk_en_cnt == 7'd88))
                    txc <= 2'b00;
            endcase
        default :
            txc <= 2'b0;
        endcase
end

*/
reg [1:0]    txc_100m_r;
reg [1:0]    txc_10m_r;

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txc_100m_r <= 2'b0;
    else
        case(rgmii_txc_dly)
        1'b0 ://rgmii_4baff3c4bcd643d4ace07f79d93bbfaa tx clock delay disable.
            if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                txc_100m_r <= 2'b11;
            else if((aclk_en_cnt == 7'd3) || (aclk_en_cnt == 7'd8))
                txc_100m_r <= 2'b00;
        1'b1 ://rgmii_4baff3c4bcd643d4ace07f79d93bbfaa tx clock delay enable.
            if((aclk_en_cnt == 7'd2) || (aclk_en_cnt == 7'd7))
                txc_100m_r <= 2'b11;
            else if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd5))
                txc_100m_r <= 2'b00;
        endcase
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txc_10m_r <= 2'b0;
    else
        case(rgmii_txc_dly)
        1'b0 ://rgmii_4baff3c4bcd643d4ace07f79d93bbfaa tx clock delay disable.
            if((aclk_en_cnt == 7'd0) || (aclk_en_cnt == 7'd50))
                txc_10m_r <= 2'b11;
            else if((aclk_en_cnt == 7'd25) || (aclk_en_cnt == 7'd75))
                txc_10m_r <= 2'b00;
        1'b1 ://rgmii_4baff3c4bcd643d4ace07f79d93bbfaa tx clock delay enable.
            if((aclk_en_cnt == 7'd13) || (aclk_en_cnt == 7'd63))
                txc_10m_r <= 2'b11;
            else if((aclk_en_cnt == 7'd38) || (aclk_en_cnt == 7'd88))
                txc_10m_r <= 2'b00;
        endcase
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txc <= 2'b0;
    else
        case(eth_speed)
            3'h4 :
                txc <= 2'b01;
            3'h2 :
                txc <= txc_100m_r;
            3'h1 :
                txc <= txc_10m_r;
            default :
                txc <= 2'b0;
        endcase
end

/*----------------------- Rx Region ----------------------------*/
assign rx_mac_aclk = rgmii_rxc;

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_mac_aclk_en <= 1'b0;
    else if(eth_speed[2] == 1'b1)
        rx_mac_aclk_en <= 1'b1;
    else
        rx_mac_aclk_en <= ~rx_mac_aclk_en;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        begin
            rx_dv_dl1 <= 1'b0;
            rxd_dl1 <= 8'h0;
        end
    else
        begin
            rx_dv_dl1 <= rx_dv;
            rxd_dl1 <= rxd;
        end
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_dv <= 1'b0;
    else
        gm_rx_dv <= rx_dv_dl1;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_odd_data_ptr <= 1'b0;
    else if(rx_dv == 1'b0)
        rx_odd_data_ptr <= 1'b0;
    else
        rx_odd_data_ptr <= ~rx_odd_data_ptr;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_d <= 8'h0;
    else
        begin
            //if((eth_speed[2] == 1'b1) && (rx_dv_dl1 == 1'b1))
            if((eth_speed[2] == 1'b1))
                gm_rx_d <= rxd_dl1;
            else if((rx_dv == 1'b1) && (rx_odd_data_ptr == 1'b1))
                gm_rx_d <= {rxd[3:0],rxd_dl1[3:0]};
        end
end

reg rx_er_dl1;
always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
	rx_er_dl1 <= 1'b0;
    else
	rx_er_dl1 <= rx_er;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_err <= 1'b0;
    else
        begin
//            if(rx_er == 1'b1)
            if(rx_er_dl1 == 1'b1)
                gm_rx_err <= 1'b1;
            else if(rx_mac_aclk_en == 1'b1)
                gm_rx_err <= 1'b0;
        end
end

/*----------------------- PHY Interface ----------------------------*/
rgmii_4baff3c4bcd643d4ace07f79d93bbfaa #(
    .RGMII_SYNC_EN                      (RGMII_SYNC_EN                      )
)
u_rgmii
(
//Globle Signals
    .tx_mac_aclk                        (tx_mac_aclk                        ),
//Configuration Signals
    .eth_speed                          (eth_speed                          ),
    .rgmii_rxc_edge                     (rgmii_rxc_edge                     ),
//Phy Interface
    .txd                                (txd                                ),
    .tx_en                              (tx_en                              ),
    .tx_er                              (tx_er                              ),
    .txc                                (txc                                ),
    .rxd                                (rxd                                ),
    .rx_dv                              (rx_dv                              ),
    .rx_er                              (rx_er                              ),
//RGMII Interface
    .rgmii_txd_HI                       (rgmii_txd_HI                       ),
    .rgmii_txd_LO                       (rgmii_txd_LO                       ),
    .rgmii_tx_ctl_HI                    (rgmii_tx_ctl_HI                    ),
    .rgmii_tx_ctl_LO                    (rgmii_tx_ctl_LO                    ),
    .rgmii_txc_HI                       (rgmii_txc_HI                       ),
    .rgmii_txc_LO                       (rgmii_txc_LO                       ),
    .rgmii_rxd_HI                       (rgmii_rxd_HI                       ),
    .rgmii_rxd_LO                       (rgmii_rxd_LO                       ),
    .rgmii_rx_ctl_HI                    (rgmii_rx_ctl_HI                    ),
    .rgmii_rx_ctl_LO                    (rgmii_rx_ctl_LO                    ),
    .rgmii_rxc                          (rgmii_rxc                          )
);

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module rgmii_sync_4baff3c4bcd643d4ace07f79d93bbfaa
(
//Globle Signals
input                           rgmii_rxc,
input           [2:0]           eth_speed,
//RGMII Rx Interface Input
input           [3:0]           rgmii_rxd_HI_i,
input           [3:0]           rgmii_rxd_LO_i,
input                           rgmii_rx_ctl_HI_i,
input                           rgmii_rx_ctl_LO_i,
//RGMII Rx Interface Output
output  reg     [3:0]           rgmii_rxd_HI_o,
output  reg     [3:0]           rgmii_rxd_LO_o,
output  reg                     rgmii_rx_ctl_HI_o,
output  reg                     rgmii_rx_ctl_LO_o
);


// Parameter Define 
parameter State_idle     = 2'd0;
parameter State_preamble = 2'd1;
parameter State_data_dl1 = 2'd2;
parameter State_data_dl2 = 2'd3;


// Register Define 
reg     [1:0]                   cur_state;
reg     [1:0]                   next_state;
reg                             preamble_odd;
reg     [7:0]                   rx_d_dl1;
reg                             rx_dv_dl1;
reg     [7:0]                   rx_d_dl2;
reg                             rx_dv_dl2;

// Wire Define

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

always @(posedge rgmii_rxc)
begin
    rx_d_dl1[7:4] <= rgmii_rxd_HI_i;
    rx_d_dl1[3:0] <= rgmii_rxd_LO_i;
    rx_dv_dl1 <= rgmii_rx_ctl_HI_i;
    rx_d_dl2 <= rx_d_dl1;
    rx_dv_dl2 <= rx_dv_dl1;
end

/*----------------------- FSM Region ----------------------------*/
always @(posedge rgmii_rxc)
begin
	cur_state <= next_state;
end

always @(*)
begin
	case(cur_state)
    State_idle :
        if((rx_dv_dl1 == 1'b1) && (rx_d_dl1[3:0] == 4'h5))
            next_state = State_preamble;
        else
            next_state = State_idle;

    State_preamble : 
        if(rx_dv_dl1 == 1'b0)
            next_state = State_idle;
        else if((rx_d_dl1[3:0] == 4'hd) && (preamble_odd == 1'b0))
            next_state = State_data_dl1;
        else if((rx_d_dl1[3:0] == 4'hd) && (preamble_odd == 1'b1))
            next_state = State_data_dl2;
        else if(rx_d_dl1[3:0] != 4'h5)
            next_state = State_idle;
        else
            next_state = State_preamble;
        
    State_data_dl1 :
        if(rx_dv_dl1 == 1'b0)
            next_state = State_idle;
        else
            next_state = State_data_dl1;

    State_data_dl2 :
        if(rx_dv_dl2 == 1'b0)
            next_state = State_idle;
        else
            next_state = State_data_dl2;

    default :
        next_state = State_idle;
    endcase
end

always @(posedge rgmii_rxc)
begin
    if(cur_state == State_preamble)
        preamble_odd <= ~preamble_odd;
    else
        preamble_odd <= 1'b0;
end

/*----------------------- Sync Output Region ----------------------------*/

always @(posedge rgmii_rxc)
begin
    if(eth_speed[2] == 1'b1)
        rgmii_rxd_LO_o <= rgmii_rxd_LO_i;
    else if((cur_state == State_preamble) && (rx_d_dl1[3:0] == 4'hd) && (preamble_odd == 1'b1))
        rgmii_rxd_LO_o <= 4'h5;
    else if(cur_state == State_data_dl2)
        rgmii_rxd_LO_o <= rx_d_dl2[3:0];
    else
        rgmii_rxd_LO_o <= rx_d_dl1[3:0];
end

always @(posedge rgmii_rxc)
begin
    if(eth_speed[2] == 1'b1)
        rgmii_rxd_HI_o <= rgmii_rxd_HI_i;
    else
        rgmii_rxd_HI_o <= 4'h0;
end

always @(posedge rgmii_rxc)
begin
    if(eth_speed[2] == 1'b1)
        rgmii_rx_ctl_HI_o <= rgmii_rx_ctl_HI_i;
    else if((cur_state == State_preamble) && (rx_d_dl1[3:0] == 4'hd) && (preamble_odd == 1'b1))
        rgmii_rx_ctl_HI_o <= 1'b1;
    else if(cur_state == State_data_dl2)
        rgmii_rx_ctl_HI_o <= rx_dv_dl2;
    else
        rgmii_rx_ctl_HI_o <= rx_dv_dl1;
end

always @(posedge rgmii_rxc)
begin
    if(eth_speed[2] == 1'b1)
        rgmii_rx_ctl_LO_o <= rgmii_rx_ctl_LO_i;
    else if((cur_state == State_preamble) && (rx_d_dl1[3:0] == 4'hd) && (preamble_odd == 1'b1))
        rgmii_rx_ctl_LO_o <= 1'b1;
    else if(cur_state == State_data_dl2)
        rgmii_rx_ctl_LO_o <= rx_dv_dl2;
    else
        rgmii_rx_ctl_LO_o <= rx_dv_dl1;
end

endmodule


/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************

`timescale 1 ns / 1 ns
module rgmii_4baff3c4bcd643d4ace07f79d93bbfaa #(
    parameter                       RGMII_SYNC_EN = 1
)
(
//Globle Signals
input                           tx_mac_aclk,
//Configuration Signals
input           [2:0]           eth_speed,
input                           rgmii_rxc_edge,//0:DDIO Rising Edge; 1:DDIO Falling Edge; 
//Phy Interface
input           [7:0]           txd,
input                           tx_en,
input                           tx_er,
input           [1:0]           txc,//if rgmii_txc_dly set 0, used clk_125m clock. if rgmii_txc_dly set 1, used clk_125m_90deg clock.
output  reg     [7:0]           rxd,
output  reg                     rx_dv,
output  reg                     rx_er,
//RGMII Interface
output  reg     [3:0]           rgmii_txd_HI,
output  reg     [3:0]           rgmii_txd_LO,
output  reg                     rgmii_tx_ctl_HI,
output  reg                     rgmii_tx_ctl_LO,
output  reg                     rgmii_txc_HI,
output  reg                     rgmii_txc_LO,
input           [3:0]           rgmii_rxd_HI,
input           [3:0]           rgmii_rxd_LO,
input                           rgmii_rx_ctl_HI,
input                           rgmii_rx_ctl_LO,
input                           rgmii_rxc
//Status and  Error Signals
);
// Parameter Define 

// Register Define 
reg     [3:0]                   rgmii_rxd_HI_d1;
reg                             rgmii_rx_ctl_HI_d1;
reg     [3:0]                   rgmii_txd_HI_r;
reg     [3:0]                   rgmii_txd_LO_r;
reg                             rgmii_tx_ctl_HI_r;
reg                             rgmii_tx_ctl_LO_r;
reg                             rgmii_txc_HI_r;
reg                             rgmii_txc_LO_r;
// Wire Define
wire                            tx_en_to_ddr;
wire                            rgmii_tx_ctl_int;
wire    [3:0]                   txd_falling;
/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- RGMII Tx Region ----------------------------*/
assign tx_en_to_ddr = (eth_speed[2] == 1'b1) ? tx_en : tx_en && (!tx_er);
assign rgmii_tx_ctl_int = tx_en ^ tx_er;

assign txd_falling = (eth_speed[2] == 1'b1) ? txd[7:4] : txd[3:0];

always @(posedge tx_mac_aclk)
begin
    rgmii_txc_HI_r    <= txc[0];
    rgmii_txc_LO_r    <= txc[1];     
    rgmii_tx_ctl_HI_r <= tx_en_to_ddr;
    rgmii_tx_ctl_LO_r <= rgmii_tx_ctl_int;
    rgmii_txd_HI_r    <= txd[3:0];
    rgmii_txd_LO_r    <= txd_falling;
end

always @(posedge tx_mac_aclk)
begin
    rgmii_txc_HI    <= rgmii_txc_HI_r   ;
    rgmii_txc_LO    <= rgmii_txc_LO_r   ;
    rgmii_tx_ctl_HI <= rgmii_tx_ctl_HI_r;
    rgmii_tx_ctl_LO <= rgmii_tx_ctl_LO_r;
    rgmii_txd_HI    <= rgmii_txd_HI_r   ;
    rgmii_txd_LO    <= rgmii_txd_LO_r   ;
end

/*----------------------- RGMII Rx Region ----------------------------*/
//rgmii_rxd & rgmii_rx_ctl
always @(posedge rgmii_rxc)
begin
	rgmii_rxd_HI_d1 <= rgmii_rxd_HI;
	rgmii_rx_ctl_HI_d1 <= rgmii_rx_ctl_HI;
end

generate
if(RGMII_SYNC_EN == 0)
begin

always @(posedge rgmii_rxc)
begin
    if(eth_speed[2] == 1'b1)//1000M
        begin
            if(rgmii_rxc_edge == 1'b0)//0:DDIO Rising Edge
                begin
	                rxd[7:4] <= rgmii_rxd_LO;
	                rxd[3:0] <= rgmii_rxd_HI_d1;
                    rx_dv <= rgmii_rx_ctl_HI_d1;
                    rx_er <= rgmii_rx_ctl_HI_d1^rgmii_rx_ctl_LO;
                end
            else//1:DDIO Falling Edge
                begin
        	        rxd[7:4] <= rgmii_rxd_HI;
        	        rxd[3:0] <= rgmii_rxd_LO;
                    rx_dv <= rgmii_rx_ctl_LO;
                    rx_er <= rgmii_rx_ctl_LO^rgmii_rx_ctl_HI;
                end
        end
    else//100M or 10M
        begin
        	rxd[7:4] <= 4'b0;
        	rxd[3:0] <= rgmii_rxd_LO;
            rx_dv <= rgmii_rx_ctl_LO;
            rx_er <= rgmii_rx_ctl_LO^rgmii_rx_ctl_HI_d1;
        end
end

end
else
begin

reg     [3:0]                   rgmii_rxd_HI_i;
reg     [3:0]                   rgmii_rxd_LO_i;
reg                             rgmii_rx_ctl_HI_i;
reg                             rgmii_rx_ctl_LO_i;
wire    [3:0]                   rgmii_rxd_HI_sync;
wire    [3:0]                   rgmii_rxd_LO_sync;
wire                            rgmii_rx_ctl_HI_sync;
wire                            rgmii_rx_ctl_LO_sync;

always @(posedge rgmii_rxc)
begin
    if(eth_speed[2] == 1'b1)//1000M
        begin
            if(rgmii_rxc_edge == 1'b0)//0:DDIO Rising Edge
                begin
	                rgmii_rxd_HI_i <= rgmii_rxd_LO;
	                rgmii_rxd_LO_i <= rgmii_rxd_HI_d1;
                    rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_HI_d1;
                    rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_LO;
                end
            else//1:DDIO Falling Edge
                begin
	                rgmii_rxd_HI_i <= rgmii_rxd_HI;
	                rgmii_rxd_LO_i <= rgmii_rxd_LO;
                    rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_HI;
                    rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_LO;
                end
        end        
    else//100M or 10M
        begin
            rgmii_rxd_HI_i <= rgmii_rxd_HI_d1;
	        rgmii_rxd_LO_i <= rgmii_rxd_LO;
            rgmii_rx_ctl_HI_i <= rgmii_rx_ctl_LO;
            rgmii_rx_ctl_LO_i <= rgmii_rx_ctl_HI_d1;
        end
end

always @(posedge rgmii_rxc)
begin
	rxd[7:4] <= rgmii_rxd_HI_sync;
	rxd[3:0] <= rgmii_rxd_LO_sync;
    rx_dv <= rgmii_rx_ctl_HI_sync;
    rx_er <= rgmii_rx_ctl_HI_sync^rgmii_rx_ctl_LO_sync;
end

/*----------------------- RGMII Rx Sync Module -----------------------*/
rgmii_sync_4baff3c4bcd643d4ace07f79d93bbfaa u_rgmii_sync
(
//Globle Signals
    .rgmii_rxc                  (rgmii_rxc                  ),
    .eth_speed                  (eth_speed                  ),
//RGMII Rx Interface Input
    .rgmii_rxd_HI_i             (rgmii_rxd_HI_i             ),
    .rgmii_rxd_LO_i             (rgmii_rxd_LO_i             ),
    .rgmii_rx_ctl_HI_i          (rgmii_rx_ctl_HI_i          ),
    .rgmii_rx_ctl_LO_i          (rgmii_rx_ctl_LO_i          ),
//RGMII Rx Interface Output
    .rgmii_rxd_HI_o             (rgmii_rxd_HI_sync          ),
    .rgmii_rxd_LO_o             (rgmii_rxd_LO_sync          ),
    .rgmii_rx_ctl_HI_o          (rgmii_rx_ctl_HI_sync       ),
    .rgmii_rx_ctl_LO_o          (rgmii_rx_ctl_LO_sync       )
);

end
endgenerate


endmodule


`timescale 1 ns / 1 ns
module rmii_if_4baff3c4bcd643d4ace07f79d93bbfaa
(
//Globle Signals
input                           tx_mac_aclk,
output  reg                     tx_mac_aclk_en,
input                           tx_reset,
output  wire                    rx_mac_aclk,
output  reg                     rx_mac_aclk_en,
input                           rx_reset,
//Configuration Signals
input           [2:0]           eth_speed,
//GMII Interface
output  reg     [7:0]           gm_rx_d,
output  reg                     gm_rx_dv,
output  reg                     gm_rx_err,
input           [7:0]           gm_tx_d,
input                           gm_tx_en,
input                           gm_tx_err,
//RGMII Interface
input                           rmii_clk_ref,
output  reg     [1:0]           rmii_txd,
output  reg                     rmii_tx_en,

input           [1:0]           rmii_rxd,
input                           rmii_crs_dv,
input                           rmii_rx_err

//Status and  Error Signals
);
// Parameter Define 

// Register Define 
reg     [6:0]                   aclk_en_cnt;
reg     [6:0]                   rx_aclk_en_cnt;
reg     [1:0]                   txd;
reg                             tx_en;
reg                             tx_er;
reg                             rx_err_dl1;
reg                             rx_dv_dl1;
reg     [7:0]                   rxd_dl1;
reg     [6:0]                   rx_odd_data_ptr;
reg     [3:0]                   rxd;
reg                             rx_dv;
reg                             rx_er;
reg     [7:0]                   gm_tx_d_temp;
reg                             tx_en_temp;
reg     [6:0]                   txbit_cnt;
reg                             rx_dv_compensate;
reg                             rx_err_compensate;
reg     [7:0]                   rx_d_compensate;
reg     [6:0]                   rx_compensate_cnt;
// Wire Define

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- Tx Region ----------------------------*/
always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        aclk_en_cnt <= 7'd0;
    else if(((eth_speed == 3'h2) && (aclk_en_cnt == 7'd3)) ||
            ((eth_speed == 3'h1) && (aclk_en_cnt == 7'd39)))
        aclk_en_cnt <= 7'd0;
    else
        aclk_en_cnt <= aclk_en_cnt + 1'b1;
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        tx_mac_aclk_en <= 1'b0;
    else if(aclk_en_cnt == 7'd0)
        tx_mac_aclk_en <= 1'b1;
    else
        tx_mac_aclk_en <= 1'b0;
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        gm_tx_d_temp <= 8'h0;
    else if((gm_tx_en == 1'b1) && (tx_mac_aclk_en == 1'b1))
        gm_tx_d_temp <= gm_tx_d;
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        tx_en_temp <= 1'b0;
    else if(tx_mac_aclk_en == 1'b1)
        tx_en_temp <= gm_tx_en;
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txbit_cnt <= 7'd0;
    else if(((eth_speed == 3'h2) && (txbit_cnt == 7'd3)) ||
            ((eth_speed == 3'h1) && (txbit_cnt == 7'd39)))
        txbit_cnt <= 7'd0;
    else if(tx_en_temp == 1'b1)
        txbit_cnt <= txbit_cnt + 1'b1;
    else
        txbit_cnt <= 7'd0; 
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        txd <= 2'h0;
    else if(eth_speed == 3'h2)
        begin
            case(txbit_cnt[1:0])
                2'b00: txd <= gm_tx_d_temp[1:0];
                2'b01: txd <= gm_tx_d_temp[3:2];
                2'b10: txd <= gm_tx_d_temp[5:4];
                2'b11: txd <= gm_tx_d_temp[7:6];
                default; 
            endcase 
        end 
    else if(eth_speed == 3'h1)
        begin
            case(txbit_cnt[5:0])
                6'd00: txd <= gm_tx_d_temp[1:0];
                6'd10: txd <= gm_tx_d_temp[3:2];
                6'd20: txd <= gm_tx_d_temp[5:4];
                6'd30: txd <= gm_tx_d_temp[7:6];
                default; 
            endcase 
        end
    else;    
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        tx_en <= 1'b0;
    else 
        tx_en <= tx_en_temp;
end

always @(posedge tx_mac_aclk or posedge tx_reset)
begin
    if(tx_reset == 1'b1)
        tx_er <= 1'b0;
    else if(tx_mac_aclk_en == 1'b1)
        tx_er <= gm_tx_err;
end

always @(posedge rmii_clk_ref)
begin 
    rmii_tx_en  <= tx_en;
    rmii_txd    <= txd[1:0];
//    rmii_tx_err <= tx_er;
end

/*----------------------- Rx Region ----------------------------*/
always @(posedge rmii_clk_ref)
begin
	rxd   <= rmii_rxd;
    rx_dv <= rmii_crs_dv;
    rx_er <= rmii_rx_err;
end

assign rx_mac_aclk = rmii_clk_ref;

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_aclk_en_cnt <= 7'd0;
    else if(((eth_speed == 3'h2) && (rx_aclk_en_cnt == 7'd3)) ||
            ((eth_speed == 3'h1) && (rx_aclk_en_cnt == 7'd39)))
        rx_aclk_en_cnt <= 7'd0;
    else
        rx_aclk_en_cnt <= rx_aclk_en_cnt + 1'b1;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_mac_aclk_en <= 1'b0;
    else if(rx_aclk_en_cnt == 7'd0)
        rx_mac_aclk_en <= 1'b1;
    else
        rx_mac_aclk_en <= 1'b0;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_odd_data_ptr <= 7'd0;
    else if(((eth_speed == 3'h2) && (rx_odd_data_ptr == 7'd3)) ||
            ((eth_speed == 3'h1) && (rx_odd_data_ptr == 7'd39)) || (rx_dv == 1'b0))
        rx_odd_data_ptr <= 7'd0;
    else 
        rx_odd_data_ptr <= rx_odd_data_ptr + 1'b1;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_dv_dl1 <= 1'b0;
    else 
        rx_dv_dl1 <= rx_dv; 
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_err_dl1 <= 1'b0;
    else 
        rx_err_dl1 <= rx_er; 
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rxd_dl1 <= 8'h0;
    else if(eth_speed == 3'h2)
        begin
            case(rx_odd_data_ptr[1:0])
                2'b00: rxd_dl1[1:0] <= rxd;
                2'b01: rxd_dl1[3:2] <= rxd;
                2'b10: rxd_dl1[5:4] <= rxd;
                2'b11: rxd_dl1[7:6] <= rxd;
                default; 
            endcase 
        end 
    else if(eth_speed == 3'h1)
        begin
            case(rx_odd_data_ptr[5:0])
                6'd00: rxd_dl1[1:0] <= rxd;
                6'd10: rxd_dl1[3:2] <= rxd;
                6'd20: rxd_dl1[5:4] <= rxd;
                6'd30: rxd_dl1[7:6] <= rxd;
                default; 
            endcase 
        end
    else;    
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_compensate_cnt <= 7'b0;
    else if(rx_dv_dl1 == 1'b1)
        rx_compensate_cnt <= 7'b0;
    else if(((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
            ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
        rx_compensate_cnt <= rx_compensate_cnt;
    else
        rx_compensate_cnt <= rx_compensate_cnt + 1;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_dv_compensate <= 1'b0;
    else if(((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
            ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
        rx_dv_compensate <= 1'b0;
    else if((rx_dv_dl1 == 1'b1) && rx_odd_data_ptr == 7'd0)
        rx_dv_compensate <= 1'b1;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_err_compensate <= 1'b0;
    else if(((eth_speed == 3'h2) && (rx_compensate_cnt == 7'd3)) ||
            ((eth_speed == 3'h1) && (rx_compensate_cnt == 7'd39)))
        rx_err_compensate <= 1'b0;
    else if((rx_dv_dl1 == 1'b1) && (rx_err_dl1 == 1'b1) && rx_odd_data_ptr == 7'd0)
        rx_err_compensate <= 1'b1;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        rx_d_compensate <= 8'h0;
    else if((rx_dv_dl1 == 1'b1) && rx_odd_data_ptr == 7'd0)
        rx_d_compensate <= rxd_dl1;
    else;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_dv <= 1'b0;
    else if(rx_mac_aclk_en == 1'b1)
        gm_rx_dv <= rx_dv_compensate;
end


always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_d <= 8'h0;
    else if(rx_mac_aclk_en == 1'b1)
        gm_rx_d <= rx_d_compensate;
    else;
end

always @(posedge rx_mac_aclk or posedge rx_reset)
begin
    if(rx_reset == 1'b1)
        gm_rx_err <= 1'b0;
    else if(rx_mac_aclk_en == 1'b1)
        gm_rx_err <= rx_err_compensate;
end

endmodule


`undef IP_UUID
`undef IP_NAME_CONCAT
`undef IP_MODULE_NAME
