-- =============================================================================
-- Generated by efx_ipmgr
-- Version: 2025.1.110.3.16
-- IP Version: 1.2.15
-- =============================================================================

--------------------------------------------------------------------------------
-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved.              
--
-- This   document  contains  proprietary information  which   is        
-- protected by  copyright. All rights  are reserved.  This notice       
-- refers to original work by Efinix, Inc. which may be derivitive       
-- of other work distributed under license of the authors.  In the       
-- case of derivative work, nothing in this notice overrides the         
-- original author's license agreement.  Where applicable, the           
-- original license agreement is included in it's original               
-- unmodified form immediately below this header.                        
--                                                                       
-- WARRANTY DISCLAIMER.                                                  
--     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
--     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
--     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
--     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
--     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
--     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
--     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
--                                                                       
-- LIMITATION OF LIABILITY.                                              
--     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
--     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
--     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
--     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
--     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
--     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
--     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
--     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
--     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
--     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
--     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
--     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
--     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
--     APPLY TO LICENSEE.                                                
--
--------------------------------------------------------------------------------

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity Vsp_core is
port (
    aresetn : in std_logic;
    aclk : in std_logic;
    pixrxclk : in std_logic;
    memclk : in std_logic;
    resetnMemclk : out std_logic;
    apuAXIL_araddr : in std_logic_vector(31 downto 0);
    apuAXIL_arprot : in std_logic_vector(2 downto 0);
    apuAXIL_arready : out std_logic;
    apuAXIL_arvalid : in std_logic;
    apuAXIL_rdata : out std_logic_vector(31 downto 0);
    apuAXIL_rready : in std_logic;
    apuAXIL_rresp : out std_logic_vector(1 downto 0);
    apuAXIL_rvalid : out std_logic;
    apuAXIL_rlast : out std_logic;
    apuAXIL_awaddr : in std_logic_vector(31 downto 0);
    apuAXIL_awprot : in std_logic_vector(2 downto 0);
    apuAXIL_awready : out std_logic;
    apuAXIL_awvalid : in std_logic;
    apuAXIL_wdata : in std_logic_vector(31 downto 0);
    apuAXIL_wready : out std_logic;
    apuAXIL_wstrb : in std_logic_vector(3 downto 0);
    apuAXIL_wvalid : in std_logic;
    apuAXIL_bready : in std_logic;
    apuAXIL_bresp : out std_logic_vector(1 downto 0);
    apuAXIL_bvalid : out std_logic;
    ddrAXI_rready : out std_logic;
    ddrAXI_wvalid : out std_logic;
    probe : out std_logic_vector(5 downto 0);
    sda_in : in std_logic;
    sda_out : out std_logic;
    mipirx_RESET_N : out std_logic;
    mipirx_RST0_N : out std_logic;
    mipirx_ERR_CONTROL_LAN0 : in std_logic;
    mipirx_ERR_CONTROL_LAN1 : in std_logic;
    mipirx_ERR_CONTROL_LAN2 : in std_logic;
    mipirx_ERR_CONTROL_LAN3 : in std_logic;
    mipirx_ERR_ESC_LAN0 : in std_logic;
    mipirx_ERR_ESC_LAN1 : in std_logic;
    mipirx_ERR_ESC_LAN2 : in std_logic;
    mipirx_ERR_ESC_LAN3 : in std_logic;
    mipirx_ERR_SOT_SYNC_HS_LAN0 : in std_logic;
    mipirx_ERR_SOT_SYNC_HS_LAN1 : in std_logic;
    mipirx_ERR_SOT_SYNC_HS_LAN2 : in std_logic;
    mipirx_ERR_SOT_SYNC_HS_LAN3 : in std_logic;
    mipirx_ESC_CLK_LAN0 : in std_logic;
    mipirx_ESC_CLK_LAN1 : in std_logic;
    mipirx_ESC_CLK_LAN2 : in std_logic;
    mipirx_ESC_CLK_LAN3 : in std_logic;
    mipirx_RX_DATA_HS_LAN0 : in std_logic_vector(15 downto 0);
    mipirx_RX_DATA_HS_LAN1 : in std_logic_vector(15 downto 0);
    mipirx_RX_DATA_HS_LAN2 : in std_logic_vector(15 downto 0);
    mipirx_RX_DATA_HS_LAN3 : in std_logic_vector(15 downto 0);
    mipirx_RX_SKEW_CAL_HS_LAN0 : in std_logic;
    mipirx_RX_SKEW_CAL_HS_LAN1 : in std_logic;
    mipirx_RX_SKEW_CAL_HS_LAN2 : in std_logic;
    mipirx_RX_SKEW_CAL_HS_LAN3 : in std_logic;
    mipirx_RX_SYNC_HS_LAN0 : in std_logic;
    mipirx_RX_SYNC_HS_LAN1 : in std_logic;
    mipirx_RX_SYNC_HS_LAN2 : in std_logic;
    mipirx_RX_SYNC_HS_LAN3 : in std_logic;
    mipirx_RX_ULPS_ACTIVE_CLK_NOT : in std_logic;
    mipirx_RX_ULPS_ACTIVE_NOT_LAN0 : in std_logic;
    mipirx_RX_ULPS_ACTIVE_NOT_LAN1 : in std_logic;
    mipirx_RX_ULPS_ACTIVE_NOT_LAN2 : in std_logic;
    mipirx_RX_ULPS_ACTIVE_NOT_LAN3 : in std_logic;
    mipirx_RX_ULPS_CLK_NOT : in std_logic;
    mipirx_RX_ULPS_ESC_LAN0 : in std_logic;
    mipirx_RX_ULPS_ESC_LAN1 : in std_logic;
    mipirx_RX_ULPS_ESC_LAN2 : in std_logic;
    mipirx_RX_ULPS_ESC_LAN3 : in std_logic;
    mipirx_RX_VALID_HS_LAN0 : in std_logic;
    mipirx_RX_VALID_HS_LAN1 : in std_logic;
    mipirx_RX_VALID_HS_LAN2 : in std_logic;
    mipirx_RX_VALID_HS_LAN3 : in std_logic;
    mipirx_STOPSTATE_LAN0 : in std_logic;
    mipirx_STOPSTATE_LAN1 : in std_logic;
    mipirx_STOPSTATE_LAN2 : in std_logic;
    mipirx_STOPSTATE_LAN3 : in std_logic;
    scl_in : in std_logic;
    scl_out : out std_logic;
    scl_tri : out std_logic;
    sda_tri : out std_logic;
    clk_byte_HS : in std_logic;
    ddrAXI_arid : out std_logic_vector(5 downto 0);
    ddrAXI_araddr : out std_logic_vector(32 downto 0);
    ddrAXI_arburst : out std_logic_vector(1 downto 0);
    ddrAXI_arcache : out std_logic_vector(3 downto 0);
    ddrAXI_arlen : out std_logic_vector(7 downto 0);
    ddrAXI_arlock : out std_logic_vector(0 to 0);
    ddrAXI_arprot : out std_logic_vector(2 downto 0);
    ddrAXI_arqos : out std_logic_vector(3 downto 0);
    ddrAXI_arready : in std_logic;
    ddrAXI_arregion : out std_logic_vector(3 downto 0);
    ddrAXI_arsize : out std_logic_vector(2 downto 0);
    ddrAXI_arvalid : out std_logic;
    ddrAXI_rid : in std_logic_vector(5 downto 0);
    ddrAXI_rdata : in std_logic_vector(511 downto 0);
    ddrAXI_rlast : in std_logic;
    ddrAXI_rresp : in std_logic_vector(1 downto 0);
    ddrAXI_rvalid : in std_logic;
    ddrAXI_awid : out std_logic_vector(5 downto 0);
    ddrAXI_awaddr : out std_logic_vector(32 downto 0);
    ddrAXI_awburst : out std_logic_vector(1 downto 0);
    ddrAXI_awcache : out std_logic_vector(3 downto 0);
    ddrAXI_awlen : out std_logic_vector(7 downto 0);
    ddrAXI_awlock : out std_logic_vector(0 to 0);
    ddrAXI_awprot : out std_logic_vector(2 downto 0);
    ddrAXI_awqos : out std_logic_vector(3 downto 0);
    ddrAXI_awready : in std_logic;
    ddrAXI_awregion : out std_logic_vector(3 downto 0);
    ddrAXI_awsize : out std_logic_vector(2 downto 0);
    ddrAXI_awvalid : out std_logic;
    ddrAXI_wdata : out std_logic_vector(511 downto 0);
    ddrAXI_wlast : out std_logic;
    ddrAXI_wready : in std_logic;
    ddrAXI_wstrb : out std_logic_vector(63 downto 0);
    ddrAXI_bid : in std_logic_vector(5 downto 0);
    ddrAXI_bready : out std_logic;
    ddrAXI_bresp : in std_logic_vector(1 downto 0);
    ddrAXI_bvalid : in std_logic;
    cs : out std_logic;
    sclk : out std_logic;
    mosi : out std_logic;
    rgb0_r : out std_logic;
    rgb0_g : out std_logic;
    rgb0_b : out std_logic;
    rgb1_r : out std_logic;
    rgb1_g : out std_logic;
    rgb1_b : out std_logic;
    nslp : out std_logic;
    m0 : out std_logic;
    m0z : out std_logic;
    m1 : out std_logic;
    m1z : out std_logic;
    dir : out std_logic;
    step : out std_logic
);
end entity Vsp_core;
architecture rtl of Vsp_core is
component vsp_core_8c100ea18901433eb4f7c0fdbf115e06 is
port (
    aresetn : in std_logic;
    aclk : in std_logic;
    pixrxclk : in std_logic;
    memclk : in std_logic;
    resetnMemclk : out std_logic;
    apuAXIL_araddr : in std_logic_vector(31 downto 0);
    apuAXIL_arprot : in std_logic_vector(2 downto 0);
    apuAXIL_arready : out std_logic;
    apuAXIL_arvalid : in std_logic;
    apuAXIL_rdata : out std_logic_vector(31 downto 0);
    apuAXIL_rready : in std_logic;
    apuAXIL_rresp : out std_logic_vector(1 downto 0);
    apuAXIL_rvalid : out std_logic;
    apuAXIL_rlast : out std_logic;
    apuAXIL_awaddr : in std_logic_vector(31 downto 0);
    apuAXIL_awprot : in std_logic_vector(2 downto 0);
    apuAXIL_awready : out std_logic;
    apuAXIL_awvalid : in std_logic;
    apuAXIL_wdata : in std_logic_vector(31 downto 0);
    apuAXIL_wready : out std_logic;
    apuAXIL_wstrb : in std_logic_vector(3 downto 0);
    apuAXIL_wvalid : in std_logic;
    apuAXIL_bready : in std_logic;
    apuAXIL_bresp : out std_logic_vector(1 downto 0);
    apuAXIL_bvalid : out std_logic;
    ddrAXI_rready : out std_logic;
    ddrAXI_wvalid : out std_logic;
    probe : out std_logic_vector(5 downto 0);
    sda_in : in std_logic;
    sda_out : out std_logic;
    mipirx_RESET_N : out std_logic;
    mipirx_RST0_N : out std_logic;
    mipirx_ERR_CONTROL_LAN0 : in std_logic;
    mipirx_ERR_CONTROL_LAN1 : in std_logic;
    mipirx_ERR_CONTROL_LAN2 : in std_logic;
    mipirx_ERR_CONTROL_LAN3 : in std_logic;
    mipirx_ERR_ESC_LAN0 : in std_logic;
    mipirx_ERR_ESC_LAN1 : in std_logic;
    mipirx_ERR_ESC_LAN2 : in std_logic;
    mipirx_ERR_ESC_LAN3 : in std_logic;
    mipirx_ERR_SOT_SYNC_HS_LAN0 : in std_logic;
    mipirx_ERR_SOT_SYNC_HS_LAN1 : in std_logic;
    mipirx_ERR_SOT_SYNC_HS_LAN2 : in std_logic;
    mipirx_ERR_SOT_SYNC_HS_LAN3 : in std_logic;
    mipirx_ESC_CLK_LAN0 : in std_logic;
    mipirx_ESC_CLK_LAN1 : in std_logic;
    mipirx_ESC_CLK_LAN2 : in std_logic;
    mipirx_ESC_CLK_LAN3 : in std_logic;
    mipirx_RX_DATA_HS_LAN0 : in std_logic_vector(15 downto 0);
    mipirx_RX_DATA_HS_LAN1 : in std_logic_vector(15 downto 0);
    mipirx_RX_DATA_HS_LAN2 : in std_logic_vector(15 downto 0);
    mipirx_RX_DATA_HS_LAN3 : in std_logic_vector(15 downto 0);
    mipirx_RX_SKEW_CAL_HS_LAN0 : in std_logic;
    mipirx_RX_SKEW_CAL_HS_LAN1 : in std_logic;
    mipirx_RX_SKEW_CAL_HS_LAN2 : in std_logic;
    mipirx_RX_SKEW_CAL_HS_LAN3 : in std_logic;
    mipirx_RX_SYNC_HS_LAN0 : in std_logic;
    mipirx_RX_SYNC_HS_LAN1 : in std_logic;
    mipirx_RX_SYNC_HS_LAN2 : in std_logic;
    mipirx_RX_SYNC_HS_LAN3 : in std_logic;
    mipirx_RX_ULPS_ACTIVE_CLK_NOT : in std_logic;
    mipirx_RX_ULPS_ACTIVE_NOT_LAN0 : in std_logic;
    mipirx_RX_ULPS_ACTIVE_NOT_LAN1 : in std_logic;
    mipirx_RX_ULPS_ACTIVE_NOT_LAN2 : in std_logic;
    mipirx_RX_ULPS_ACTIVE_NOT_LAN3 : in std_logic;
    mipirx_RX_ULPS_CLK_NOT : in std_logic;
    mipirx_RX_ULPS_ESC_LAN0 : in std_logic;
    mipirx_RX_ULPS_ESC_LAN1 : in std_logic;
    mipirx_RX_ULPS_ESC_LAN2 : in std_logic;
    mipirx_RX_ULPS_ESC_LAN3 : in std_logic;
    mipirx_RX_VALID_HS_LAN0 : in std_logic;
    mipirx_RX_VALID_HS_LAN1 : in std_logic;
    mipirx_RX_VALID_HS_LAN2 : in std_logic;
    mipirx_RX_VALID_HS_LAN3 : in std_logic;
    mipirx_STOPSTATE_LAN0 : in std_logic;
    mipirx_STOPSTATE_LAN1 : in std_logic;
    mipirx_STOPSTATE_LAN2 : in std_logic;
    mipirx_STOPSTATE_LAN3 : in std_logic;
    scl_in : in std_logic;
    scl_out : out std_logic;
    scl_tri : out std_logic;
    sda_tri : out std_logic;
    clk_byte_HS : in std_logic;
    ddrAXI_arid : out std_logic_vector(5 downto 0);
    ddrAXI_araddr : out std_logic_vector(32 downto 0);
    ddrAXI_arburst : out std_logic_vector(1 downto 0);
    ddrAXI_arcache : out std_logic_vector(3 downto 0);
    ddrAXI_arlen : out std_logic_vector(7 downto 0);
    ddrAXI_arlock : out std_logic_vector(0 to 0);
    ddrAXI_arprot : out std_logic_vector(2 downto 0);
    ddrAXI_arqos : out std_logic_vector(3 downto 0);
    ddrAXI_arready : in std_logic;
    ddrAXI_arregion : out std_logic_vector(3 downto 0);
    ddrAXI_arsize : out std_logic_vector(2 downto 0);
    ddrAXI_arvalid : out std_logic;
    ddrAXI_rid : in std_logic_vector(5 downto 0);
    ddrAXI_rdata : in std_logic_vector(511 downto 0);
    ddrAXI_rlast : in std_logic;
    ddrAXI_rresp : in std_logic_vector(1 downto 0);
    ddrAXI_rvalid : in std_logic;
    ddrAXI_awid : out std_logic_vector(5 downto 0);
    ddrAXI_awaddr : out std_logic_vector(32 downto 0);
    ddrAXI_awburst : out std_logic_vector(1 downto 0);
    ddrAXI_awcache : out std_logic_vector(3 downto 0);
    ddrAXI_awlen : out std_logic_vector(7 downto 0);
    ddrAXI_awlock : out std_logic_vector(0 to 0);
    ddrAXI_awprot : out std_logic_vector(2 downto 0);
    ddrAXI_awqos : out std_logic_vector(3 downto 0);
    ddrAXI_awready : in std_logic;
    ddrAXI_awregion : out std_logic_vector(3 downto 0);
    ddrAXI_awsize : out std_logic_vector(2 downto 0);
    ddrAXI_awvalid : out std_logic;
    ddrAXI_wdata : out std_logic_vector(511 downto 0);
    ddrAXI_wlast : out std_logic;
    ddrAXI_wready : in std_logic;
    ddrAXI_wstrb : out std_logic_vector(63 downto 0);
    ddrAXI_bid : in std_logic_vector(5 downto 0);
    ddrAXI_bready : out std_logic;
    ddrAXI_bresp : in std_logic_vector(1 downto 0);
    ddrAXI_bvalid : in std_logic;
    cs : out std_logic;
    sclk : out std_logic;
    mosi : out std_logic;
    rgb0_r : out std_logic;
    rgb0_g : out std_logic;
    rgb0_b : out std_logic;
    rgb1_r : out std_logic;
    rgb1_g : out std_logic;
    rgb1_b : out std_logic;
    nslp : out std_logic;
    m0 : out std_logic;
    m0z : out std_logic;
    m1 : out std_logic;
    m1z : out std_logic;
    dir : out std_logic;
    step : out std_logic
);
end component vsp_core_8c100ea18901433eb4f7c0fdbf115e06;
begin
u_vsp_core : vsp_core_8c100ea18901433eb4f7c0fdbf115e06
port map (
    aresetn => aresetn,
    aclk => aclk,
    pixrxclk => pixrxclk,
    memclk => memclk,
    resetnMemclk => resetnMemclk,
    apuAXIL_araddr => apuAXIL_araddr,
    apuAXIL_arprot => apuAXIL_arprot,
    apuAXIL_arready => apuAXIL_arready,
    apuAXIL_arvalid => apuAXIL_arvalid,
    apuAXIL_rdata => apuAXIL_rdata,
    apuAXIL_rready => apuAXIL_rready,
    apuAXIL_rresp => apuAXIL_rresp,
    apuAXIL_rvalid => apuAXIL_rvalid,
    apuAXIL_rlast => apuAXIL_rlast,
    apuAXIL_awaddr => apuAXIL_awaddr,
    apuAXIL_awprot => apuAXIL_awprot,
    apuAXIL_awready => apuAXIL_awready,
    apuAXIL_awvalid => apuAXIL_awvalid,
    apuAXIL_wdata => apuAXIL_wdata,
    apuAXIL_wready => apuAXIL_wready,
    apuAXIL_wstrb => apuAXIL_wstrb,
    apuAXIL_wvalid => apuAXIL_wvalid,
    apuAXIL_bready => apuAXIL_bready,
    apuAXIL_bresp => apuAXIL_bresp,
    apuAXIL_bvalid => apuAXIL_bvalid,
    ddrAXI_rready => ddrAXI_rready,
    ddrAXI_wvalid => ddrAXI_wvalid,
    probe => probe,
    sda_in => sda_in,
    sda_out => sda_out,
    mipirx_RESET_N => mipirx_RESET_N,
    mipirx_RST0_N => mipirx_RST0_N,
    mipirx_ERR_CONTROL_LAN0 => mipirx_ERR_CONTROL_LAN0,
    mipirx_ERR_CONTROL_LAN1 => mipirx_ERR_CONTROL_LAN1,
    mipirx_ERR_CONTROL_LAN2 => mipirx_ERR_CONTROL_LAN2,
    mipirx_ERR_CONTROL_LAN3 => mipirx_ERR_CONTROL_LAN3,
    mipirx_ERR_ESC_LAN0 => mipirx_ERR_ESC_LAN0,
    mipirx_ERR_ESC_LAN1 => mipirx_ERR_ESC_LAN1,
    mipirx_ERR_ESC_LAN2 => mipirx_ERR_ESC_LAN2,
    mipirx_ERR_ESC_LAN3 => mipirx_ERR_ESC_LAN3,
    mipirx_ERR_SOT_SYNC_HS_LAN0 => mipirx_ERR_SOT_SYNC_HS_LAN0,
    mipirx_ERR_SOT_SYNC_HS_LAN1 => mipirx_ERR_SOT_SYNC_HS_LAN1,
    mipirx_ERR_SOT_SYNC_HS_LAN2 => mipirx_ERR_SOT_SYNC_HS_LAN2,
    mipirx_ERR_SOT_SYNC_HS_LAN3 => mipirx_ERR_SOT_SYNC_HS_LAN3,
    mipirx_ESC_CLK_LAN0 => mipirx_ESC_CLK_LAN0,
    mipirx_ESC_CLK_LAN1 => mipirx_ESC_CLK_LAN1,
    mipirx_ESC_CLK_LAN2 => mipirx_ESC_CLK_LAN2,
    mipirx_ESC_CLK_LAN3 => mipirx_ESC_CLK_LAN3,
    mipirx_RX_DATA_HS_LAN0 => mipirx_RX_DATA_HS_LAN0,
    mipirx_RX_DATA_HS_LAN1 => mipirx_RX_DATA_HS_LAN1,
    mipirx_RX_DATA_HS_LAN2 => mipirx_RX_DATA_HS_LAN2,
    mipirx_RX_DATA_HS_LAN3 => mipirx_RX_DATA_HS_LAN3,
    mipirx_RX_SKEW_CAL_HS_LAN0 => mipirx_RX_SKEW_CAL_HS_LAN0,
    mipirx_RX_SKEW_CAL_HS_LAN1 => mipirx_RX_SKEW_CAL_HS_LAN1,
    mipirx_RX_SKEW_CAL_HS_LAN2 => mipirx_RX_SKEW_CAL_HS_LAN2,
    mipirx_RX_SKEW_CAL_HS_LAN3 => mipirx_RX_SKEW_CAL_HS_LAN3,
    mipirx_RX_SYNC_HS_LAN0 => mipirx_RX_SYNC_HS_LAN0,
    mipirx_RX_SYNC_HS_LAN1 => mipirx_RX_SYNC_HS_LAN1,
    mipirx_RX_SYNC_HS_LAN2 => mipirx_RX_SYNC_HS_LAN2,
    mipirx_RX_SYNC_HS_LAN3 => mipirx_RX_SYNC_HS_LAN3,
    mipirx_RX_ULPS_ACTIVE_CLK_NOT => mipirx_RX_ULPS_ACTIVE_CLK_NOT,
    mipirx_RX_ULPS_ACTIVE_NOT_LAN0 => mipirx_RX_ULPS_ACTIVE_NOT_LAN0,
    mipirx_RX_ULPS_ACTIVE_NOT_LAN1 => mipirx_RX_ULPS_ACTIVE_NOT_LAN1,
    mipirx_RX_ULPS_ACTIVE_NOT_LAN2 => mipirx_RX_ULPS_ACTIVE_NOT_LAN2,
    mipirx_RX_ULPS_ACTIVE_NOT_LAN3 => mipirx_RX_ULPS_ACTIVE_NOT_LAN3,
    mipirx_RX_ULPS_CLK_NOT => mipirx_RX_ULPS_CLK_NOT,
    mipirx_RX_ULPS_ESC_LAN0 => mipirx_RX_ULPS_ESC_LAN0,
    mipirx_RX_ULPS_ESC_LAN1 => mipirx_RX_ULPS_ESC_LAN1,
    mipirx_RX_ULPS_ESC_LAN2 => mipirx_RX_ULPS_ESC_LAN2,
    mipirx_RX_ULPS_ESC_LAN3 => mipirx_RX_ULPS_ESC_LAN3,
    mipirx_RX_VALID_HS_LAN0 => mipirx_RX_VALID_HS_LAN0,
    mipirx_RX_VALID_HS_LAN1 => mipirx_RX_VALID_HS_LAN1,
    mipirx_RX_VALID_HS_LAN2 => mipirx_RX_VALID_HS_LAN2,
    mipirx_RX_VALID_HS_LAN3 => mipirx_RX_VALID_HS_LAN3,
    mipirx_STOPSTATE_LAN0 => mipirx_STOPSTATE_LAN0,
    mipirx_STOPSTATE_LAN1 => mipirx_STOPSTATE_LAN1,
    mipirx_STOPSTATE_LAN2 => mipirx_STOPSTATE_LAN2,
    mipirx_STOPSTATE_LAN3 => mipirx_STOPSTATE_LAN3,
    scl_in => scl_in,
    scl_out => scl_out,
    scl_tri => scl_tri,
    sda_tri => sda_tri,
    clk_byte_HS => clk_byte_HS,
    ddrAXI_arid => ddrAXI_arid,
    ddrAXI_araddr => ddrAXI_araddr,
    ddrAXI_arburst => ddrAXI_arburst,
    ddrAXI_arcache => ddrAXI_arcache,
    ddrAXI_arlen => ddrAXI_arlen,
    ddrAXI_arlock => ddrAXI_arlock,
    ddrAXI_arprot => ddrAXI_arprot,
    ddrAXI_arqos => ddrAXI_arqos,
    ddrAXI_arready => ddrAXI_arready,
    ddrAXI_arregion => ddrAXI_arregion,
    ddrAXI_arsize => ddrAXI_arsize,
    ddrAXI_arvalid => ddrAXI_arvalid,
    ddrAXI_rid => ddrAXI_rid,
    ddrAXI_rdata => ddrAXI_rdata,
    ddrAXI_rlast => ddrAXI_rlast,
    ddrAXI_rresp => ddrAXI_rresp,
    ddrAXI_rvalid => ddrAXI_rvalid,
    ddrAXI_awid => ddrAXI_awid,
    ddrAXI_awaddr => ddrAXI_awaddr,
    ddrAXI_awburst => ddrAXI_awburst,
    ddrAXI_awcache => ddrAXI_awcache,
    ddrAXI_awlen => ddrAXI_awlen,
    ddrAXI_awlock => ddrAXI_awlock,
    ddrAXI_awprot => ddrAXI_awprot,
    ddrAXI_awqos => ddrAXI_awqos,
    ddrAXI_awready => ddrAXI_awready,
    ddrAXI_awregion => ddrAXI_awregion,
    ddrAXI_awsize => ddrAXI_awsize,
    ddrAXI_awvalid => ddrAXI_awvalid,
    ddrAXI_wdata => ddrAXI_wdata,
    ddrAXI_wlast => ddrAXI_wlast,
    ddrAXI_wready => ddrAXI_wready,
    ddrAXI_wstrb => ddrAXI_wstrb,
    ddrAXI_bid => ddrAXI_bid,
    ddrAXI_bready => ddrAXI_bready,
    ddrAXI_bresp => ddrAXI_bresp,
    ddrAXI_bvalid => ddrAXI_bvalid,
    cs => cs,
    sclk => sclk,
    mosi => mosi,
    rgb0_r => rgb0_r,
    rgb0_g => rgb0_g,
    rgb0_b => rgb0_b,
    rgb1_r => rgb1_r,
    rgb1_g => rgb1_g,
    rgb1_b => rgb1_b,
    nslp => nslp,
    m0 => m0,
    m0z => m0z,
    m1 => m1,
    m1z => m1z,
    dir => dir,
    step => step
);
end architecture rtl;

-- file Vsp_core_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Vsp_core_8c100ea18901433eb4f7c0fdbf115e06 top_v1_0 top implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

-- module parameters:
-- aresetNNotP (external reset polarity): true
-- fAclk (root clock frequency [kHz]): 200000
-- aclkDiffNotSng (root clock endedness): false
-- clks (design clocks): mclk;pixrxclk;memclk
-- fClks (design clock frequencies [kHz]): 200000;100000;250000
-- clkIntNotExts (design clock origins): true;false;false
-- clkDiffNotSngs (design clock endednesses): false;false;false
-- aclkIntNotExt (root clock origin): false

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library efxphysicallib;
use efxphysicallib.efxcomponents.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Vsp_core_8c100ea18901433eb4f7c0fdbf115e06 is
	generic (
		fAclk: natural := 200000;
		fMclk: natural := 200000;
		fPixrxclk: natural := 100000;
		fMemclk: natural := 250000
	);
	port (
		aresetn: in std_logic;
		aclk: in std_logic;
		pixrxclk: in std_logic;
		memclk: in std_logic;
		resetnMemclk: out std_logic;
		probe: out std_logic_vector(5 downto 0);
		clk_byte_HS: in std_logic;
		cs: out std_logic;
		sclk: out std_logic;
		mosi: out std_logic;
		rgb0_r: out std_logic;
		rgb0_g: out std_logic;
		rgb0_b: out std_logic;
		rgb1_r: out std_logic;
		rgb1_g: out std_logic;
		rgb1_b: out std_logic;
		nslp: out std_logic;
		m0: out std_logic;
		m0z: out std_logic;
		m1: out std_logic;
		m1z: out std_logic;
		dir: out std_logic;
		step: out std_logic;

		apuAXIL_araddr: in std_logic_vector(31 downto 0);
		apuAXIL_arprot: in std_logic_vector(2 downto 0);
		apuAXIL_arready: out std_logic;
		apuAXIL_arvalid: in std_logic;

		apuAXIL_rdata: out std_logic_vector(31 downto 0);
		apuAXIL_rready: in std_logic;
		apuAXIL_rresp: out std_logic_vector(1 downto 0);
		apuAXIL_rvalid: out std_logic;
		apuAXIL_rlast: out std_logic;

		apuAXIL_awaddr: in std_logic_vector(31 downto 0);
		apuAXIL_awprot: in std_logic_vector(2 downto 0);
		apuAXIL_awready: out std_logic;
		apuAXIL_awvalid: in std_logic;

		apuAXIL_wdata: in std_logic_vector(31 downto 0);
		apuAXIL_wready: out std_logic;
		apuAXIL_wstrb: in std_logic_vector(3 downto 0);
		apuAXIL_wvalid: in std_logic;

		apuAXIL_bready: in std_logic;
		apuAXIL_bresp: out std_logic_vector(1 downto 0);
		apuAXIL_bvalid: out std_logic;

		ddrAXI_rready: out std_logic;
		ddrAXI_wvalid: out std_logic;

		mipirx_RESET_N: out std_logic;
		mipirx_RST0_N: out std_logic;
		mipirx_ERR_CONTROL_LAN0: in std_logic;
		mipirx_ERR_CONTROL_LAN1: in std_logic;
		mipirx_ERR_CONTROL_LAN2: in std_logic;
		mipirx_ERR_CONTROL_LAN3: in std_logic;
		mipirx_ERR_ESC_LAN0: in std_logic;
		mipirx_ERR_ESC_LAN1: in std_logic;
		mipirx_ERR_ESC_LAN2: in std_logic;
		mipirx_ERR_ESC_LAN3: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN0: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN1: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN2: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN3: in std_logic;
		mipirx_ESC_CLK_LAN0: in std_logic;
		mipirx_ESC_CLK_LAN1: in std_logic;
		mipirx_ESC_CLK_LAN2: in std_logic;
		mipirx_ESC_CLK_LAN3: in std_logic;
		mipirx_RX_DATA_HS_LAN0: in std_logic_vector(15 downto 0);
		mipirx_RX_DATA_HS_LAN1: in std_logic_vector(15 downto 0);
		mipirx_RX_DATA_HS_LAN2: in std_logic_vector(15 downto 0);
		mipirx_RX_DATA_HS_LAN3: in std_logic_vector(15 downto 0);
		mipirx_RX_SKEW_CAL_HS_LAN0: in std_logic;
		mipirx_RX_SKEW_CAL_HS_LAN1: in std_logic;
		mipirx_RX_SKEW_CAL_HS_LAN2: in std_logic;
		mipirx_RX_SKEW_CAL_HS_LAN3: in std_logic;
		mipirx_RX_SYNC_HS_LAN0: in std_logic;
		mipirx_RX_SYNC_HS_LAN1: in std_logic;
		mipirx_RX_SYNC_HS_LAN2: in std_logic;
		mipirx_RX_SYNC_HS_LAN3: in std_logic;
		mipirx_RX_ULPS_ACTIVE_CLK_NOT: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN0: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN1: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN2: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN3: in std_logic;
		mipirx_RX_ULPS_CLK_NOT: in std_logic;
		mipirx_RX_ULPS_ESC_LAN0: in std_logic;
		mipirx_RX_ULPS_ESC_LAN1: in std_logic;
		mipirx_RX_ULPS_ESC_LAN2: in std_logic;
		mipirx_RX_ULPS_ESC_LAN3: in std_logic;
		mipirx_RX_VALID_HS_LAN0: in std_logic;
		mipirx_RX_VALID_HS_LAN1: in std_logic;
		mipirx_RX_VALID_HS_LAN2: in std_logic;
		mipirx_RX_VALID_HS_LAN3: in std_logic;
		mipirx_STOPSTATE_LAN0: in std_logic;
		mipirx_STOPSTATE_LAN1: in std_logic;
		mipirx_STOPSTATE_LAN2: in std_logic;
		mipirx_STOPSTATE_LAN3: in std_logic;

		scl_in: in std_logic;
		scl_out: out std_logic;
		scl_tri: out std_logic;

		sda_in: in std_logic;
		sda_out: out std_logic;
		sda_tri: out std_logic;

		ddrAXI_arid: out std_logic_vector(5 downto 0);
		ddrAXI_araddr: out std_logic_vector(32 downto 0);
		ddrAXI_arburst: out std_logic_vector(1 downto 0);
		ddrAXI_arcache: out std_logic_vector(3 downto 0);
		ddrAXI_arlen: out std_logic_vector(7 downto 0);
		ddrAXI_arlock: out std_logic_vector(0 downto 0);
		ddrAXI_arprot: out std_logic_vector(2 downto 0);
		ddrAXI_arqos: out std_logic_vector(3 downto 0);
		ddrAXI_arready: in std_logic;
		ddrAXI_arregion: out std_logic_vector(3 downto 0);
		ddrAXI_arsize: out std_logic_vector(2 downto 0);
		ddrAXI_arvalid: out std_logic;

		ddrAXI_rid: in std_logic_vector(5 downto 0);
		ddrAXI_rdata: in std_logic_vector(511 downto 0);
		ddrAXI_rlast: in std_logic;
		ddrAXI_rresp: in std_logic_vector(1 downto 0);
		ddrAXI_rvalid: in std_logic;

		ddrAXI_awid: out std_logic_vector(5 downto 0);
		ddrAXI_awaddr: out std_logic_vector(32 downto 0);
		ddrAXI_awburst: out std_logic_vector(1 downto 0);
		ddrAXI_awcache: out std_logic_vector(3 downto 0);
		ddrAXI_awlen: out std_logic_vector(7 downto 0);
		ddrAXI_awlock: out std_logic_vector(0 downto 0);
		ddrAXI_awprot: out std_logic_vector(2 downto 0);
		ddrAXI_awqos: out std_logic_vector(3 downto 0);
		ddrAXI_awready: in std_logic;
		ddrAXI_awregion: out std_logic_vector(3 downto 0);
		ddrAXI_awsize: out std_logic_vector(2 downto 0);
		ddrAXI_awvalid: out std_logic;

		ddrAXI_wdata: out std_logic_vector(511 downto 0);
		ddrAXI_wlast: out std_logic;
		ddrAXI_wready: in std_logic;
		ddrAXI_wstrb: out std_logic_vector(63 downto 0);

		ddrAXI_bid: in std_logic_vector(5 downto 0);
		ddrAXI_bready: out std_logic;
		ddrAXI_bresp: in std_logic_vector(1 downto 0);
		ddrAXI_bvalid: in std_logic
	);
end Vsp_core_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Vsp_core_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Camif_8c100ea18901433eb4f7c0fdbf115e06 is
		generic (
			fMclk: natural
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;
			resetPixrxclk: in std_logic;
			pixrxclk: in std_logic;
			tkclk: in std_logic;

			NRowRaw: in std_logic_vector(11 downto 0);
			NCol: in std_logic_vector(10 downto 0);

			toVideoinAXIS_tready: in std_logic;
			toVideoinAXIS_tvalid: out std_logic;
			toVideoinAXIS_tdata: out std_logic_vector(23 downto 0);
			toVideoinAXIS_tlast: out std_logic;

			reqInvConfig: in std_logic;
			ackInvConfig: out std_logic;

			configHdrNotFix: in std_logic_vector(7 downto 0);
			configSynthNotLive: in std_logic_vector(7 downto 0);

			reqInvConfigSynth: in std_logic;
			ackInvConfigSynth: out std_logic;

			configSynthTixVSynthmode: in std_logic_vector(7 downto 0);
			configSynthTFramepad: in std_logic_vector(15 downto 0);
			configSynthTLinepad: in std_logic_vector(7 downto 0);

			reqInvSetReg: in std_logic;
			ackInvSetReg: out std_logic;

			setRegAddr: in std_logic_vector(15 downto 0);
			setRegVal: in std_logic_vector(7 downto 0);

			reqInvGetReg: in std_logic;
			ackInvGetReg: out std_logic;

			getRegAddr: in std_logic_vector(15 downto 0);
			getRegVal: out std_logic_vector(7 downto 0);

			reqInvModReg: in std_logic;
			ackInvModReg: out std_logic;

			modRegAddr: in std_logic_vector(15 downto 0);
			modRegMask: in std_logic_vector(7 downto 0);
			modRegVal: in std_logic_vector(7 downto 0);

			reqInvSetCorereg: in std_logic;
			ackInvSetCorereg: out std_logic;

			setCoreregAddr: in std_logic_vector(7 downto 0);
			setCoreregVal: in std_logic_vector(31 downto 0);

			reqInvGetCorereg: in std_logic;
			ackInvGetCorereg: out std_logic;

			getCoreregAddr: in std_logic_vector(7 downto 0);
			getCoreregVal: out std_logic_vector(31 downto 0);

			rng: in std_logic;

			vsync: out std_logic;
			ixTExp: out std_logic_vector(3 downto 0);

			clk_byte_HS: in std_logic;

			mipirx_RESET_N: out std_logic;
			mipirx_RST0_N: out std_logic;
			mipirx_ERR_CONTROL_LAN0: in std_logic;
			mipirx_ERR_CONTROL_LAN1: in std_logic;
			mipirx_ERR_CONTROL_LAN2: in std_logic;
			mipirx_ERR_CONTROL_LAN3: in std_logic;
			mipirx_ERR_ESC_LAN0: in std_logic;
			mipirx_ERR_ESC_LAN1: in std_logic;
			mipirx_ERR_ESC_LAN2: in std_logic;
			mipirx_ERR_ESC_LAN3: in std_logic;
			mipirx_ERR_SOT_SYNC_HS_LAN0: in std_logic;
			mipirx_ERR_SOT_SYNC_HS_LAN1: in std_logic;
			mipirx_ERR_SOT_SYNC_HS_LAN2: in std_logic;
			mipirx_ERR_SOT_SYNC_HS_LAN3: in std_logic;
			mipirx_ESC_CLK_LAN0: in std_logic;
			mipirx_ESC_CLK_LAN1: in std_logic;
			mipirx_ESC_CLK_LAN2: in std_logic;
			mipirx_ESC_CLK_LAN3: in std_logic;
			mipirx_RX_DATA_HS_LAN0: in std_logic_vector(15 downto 0);
			mipirx_RX_DATA_HS_LAN1: in std_logic_vector(15 downto 0);
			mipirx_RX_DATA_HS_LAN2: in std_logic_vector(15 downto 0);
			mipirx_RX_DATA_HS_LAN3: in std_logic_vector(15 downto 0);
			mipirx_RX_SKEW_CAL_HS_LAN0: in std_logic;
			mipirx_RX_SKEW_CAL_HS_LAN1: in std_logic;
			mipirx_RX_SKEW_CAL_HS_LAN2: in std_logic;
			mipirx_RX_SKEW_CAL_HS_LAN3: in std_logic;
			mipirx_RX_SYNC_HS_LAN0: in std_logic;
			mipirx_RX_SYNC_HS_LAN1: in std_logic;
			mipirx_RX_SYNC_HS_LAN2: in std_logic;
			mipirx_RX_SYNC_HS_LAN3: in std_logic;
			mipirx_RX_ULPS_ACTIVE_CLK_NOT: in std_logic;
			mipirx_RX_ULPS_ACTIVE_NOT_LAN0: in std_logic;
			mipirx_RX_ULPS_ACTIVE_NOT_LAN1: in std_logic;
			mipirx_RX_ULPS_ACTIVE_NOT_LAN2: in std_logic;
			mipirx_RX_ULPS_ACTIVE_NOT_LAN3: in std_logic;
			mipirx_RX_ULPS_CLK_NOT: in std_logic;
			mipirx_RX_ULPS_ESC_LAN0: in std_logic;
			mipirx_RX_ULPS_ESC_LAN1: in std_logic;
			mipirx_RX_ULPS_ESC_LAN2: in std_logic;
			mipirx_RX_ULPS_ESC_LAN3: in std_logic;
			mipirx_RX_VALID_HS_LAN0: in std_logic;
			mipirx_RX_VALID_HS_LAN1: in std_logic;
			mipirx_RX_VALID_HS_LAN2: in std_logic;
			mipirx_RX_VALID_HS_LAN3: in std_logic;
			mipirx_STOPSTATE_LAN0: in std_logic;
			mipirx_STOPSTATE_LAN1: in std_logic;
			mipirx_STOPSTATE_LAN2: in std_logic;
			mipirx_STOPSTATE_LAN3: in std_logic;

			scl_in: in std_logic;
			scl_out: out std_logic;
			scl_tri: out std_logic;

			sda_in: in std_logic;
			sda_out: out std_logic;
			sda_tri: out std_logic;

			RxDataHS0: in std_logic_vector(15 downto 0);
			RxDataHS1: in std_logic_vector(15 downto 0);
			RxDataHS2: in std_logic_vector(15 downto 0);
			RxDataHS3: in std_logic_vector(15 downto 0);

			datatype_dbg: out std_logic_vector(5 downto 0);
			mipiAXIS_dbg: out std_logic_vector(3 downto 0);
			video_out_dbg: out std_logic_vector(3 downto 0);

			stateConfig_dbg: out std_logic_vector(7 downto 0)
		);
	end component;

	component Corner_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			vsync: in std_logic;
			NRow: in std_logic_vector(10 downto 0);
			NCol: in std_logic_vector(10 downto 0);

			grayFromVideoinAXIS_tready: out std_logic;
			grayFromVideoinAXIS_tvalid: in std_logic;
			grayFromVideoinAXIS_tdata: in std_logic_vector(71 downto 0);
			grayFromVideoinAXIS_tlast: in std_logic;

			reqInvAcquire: in std_logic;
			ackInvAcquire: out std_logic;

			reqInvConfig: in std_logic;
			ackInvConfig: out std_logic;

			configLinNotLog: in std_logic_vector(7 downto 0);
			configThd: in std_logic_vector(7 downto 0);
			configRow0: in std_logic_vector(15 downto 0);
			configRow1: in std_logic_vector(15 downto 0);
			configCol0: in std_logic_vector(15 downto 0);
			configCol1: in std_logic_vector(15 downto 0);

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTkst: out std_logic_vector(31 downto 0);
			getInfoScoreMin: out std_logic_vector(7 downto 0);
			getInfoScoreMax: out std_logic_vector(7 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);

			reqInvUnlock: in std_logic;
			ackInvUnlock: out std_logic;

			tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0);

			reqCoobufToHostif: in std_logic;
			ackCoobufToHostif: out std_logic;
			dneCoobufToHostif: in std_logic;
			avllenCoobufToHostif: out std_logic_vector(31 downto 0);

			coobufToHostifAXIS_tready: in std_logic;
			coobufToHostifAXIS_tvalid: out std_logic;
			coobufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			coobufToHostifAXIS_tlast: out std_logic
		);
	end component;

	component Cputrack_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			trigA: in std_logic;
			trigB: in std_logic;
			trigC: in std_logic;
			trigD: in std_logic;

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTCapt: out std_logic_vector(31 downto 0);
			getInfoPtr0Seqbuf: out std_logic_vector(15 downto 0);

			reqInvSelect: in std_logic;
			ackInvSelect: out std_logic;

			selectTixVCapture: in std_logic_vector(7 downto 0);
			selectStaTixVTrigger: in std_logic_vector(7 downto 0);
			selectStaFallingNotRising: in std_logic_vector(7 downto 0);
			selectStoTixVTrigger: in std_logic_vector(7 downto 0);
			selectStoFallingNotRising: in std_logic_vector(7 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);
			setTCaptMax: in std_logic_vector(31 downto 0);

			reqSeqbufToHostif: in std_logic;
			ackSeqbufToHostif: out std_logic;
			dneSeqbufToHostif: in std_logic;
			avllenSeqbufToHostif: out std_logic_vector(31 downto 0);

			seqbufToHostifAXIS_tready: in std_logic;
			seqbufToHostifAXIS_tvalid: out std_logic;
			seqbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			seqbufToHostifAXIS_tlast: out std_logic;

			hostifStateOp: in std_logic_vector(7 downto 0)
		);
	end component;

	component Ddrif_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			resetMemclk: in std_logic;
			memclk: in std_logic;

			tkclk: in std_logic;

			getStatsNRdA: out std_logic_vector(31 downto 0);
			getStatsNRdB: out std_logic_vector(31 downto 0);
			getStatsNWrA: out std_logic_vector(31 downto 0);
			getStatsNWrB: out std_logic_vector(31 downto 0);

			reqRdA: in std_logic;
			ackRdA: out std_logic;

			rdAAXI_araddr: in std_logic_vector(17 downto 0);
			rdAAXI_arready: out std_logic;
			rdAAXI_arvalid: in std_logic;
			rdAAXI_rdata: out std_logic_vector(127 downto 0);
			rdAAXI_rlast: out std_logic;
			rdAAXI_rready: in std_logic;
			rdAAXI_rresp: out std_logic_vector(1 downto 0);
			rdAAXI_rvalid: out std_logic;

			reqRdB: in std_logic;
			ackRdB: out std_logic;

			rdBAXI_araddr: in std_logic_vector(17 downto 0);
			rdBAXI_arready: out std_logic;
			rdBAXI_arvalid: in std_logic;
			rdBAXI_rdata: out std_logic_vector(127 downto 0);
			rdBAXI_rlast: out std_logic;
			rdBAXI_rready: in std_logic;
			rdBAXI_rresp: out std_logic_vector(1 downto 0);
			rdBAXI_rvalid: out std_logic;

			reqWrA: in std_logic;
			ackWrA: out std_logic;

			wrAAXI_awaddr: in std_logic_vector(17 downto 0);
			wrAAXI_awready: out std_logic;
			wrAAXI_awvalid: in std_logic;
			wrAAXI_wdata: in std_logic_vector(127 downto 0);
			wrAAXI_wlast: in std_logic;
			wrAAXI_wready: out std_logic;
			wrAAXI_wvalid: in std_logic;

			reqWrB: in std_logic;
			ackWrB: out std_logic;

			wrBAXI_awaddr: in std_logic_vector(17 downto 0);
			wrBAXI_awready: out std_logic;
			wrBAXI_awvalid: in std_logic;
			wrBAXI_wdata: in std_logic_vector(127 downto 0);
			wrBAXI_wlast: in std_logic;
			wrBAXI_wready: out std_logic;
			wrBAXI_wvalid: in std_logic;

			ddrAXI_arid: out std_logic_vector(5 downto 0);
			ddrAXI_araddr: out std_logic_vector(32 downto 0);
			ddrAXI_arburst: out std_logic_vector(1 downto 0);
			ddrAXI_arcache: out std_logic_vector(3 downto 0);
			ddrAXI_arlen: out std_logic_vector(7 downto 0);
			ddrAXI_arlock: out std_logic_vector(0 downto 0);
			ddrAXI_arprot: out std_logic_vector(2 downto 0);
			ddrAXI_arqos: out std_logic_vector(3 downto 0);
			ddrAXI_arready: in std_logic;
			ddrAXI_arregion: out std_logic_vector(3 downto 0);
			ddrAXI_arsize: out std_logic_vector(2 downto 0);
			ddrAXI_arvalid: out std_logic;

			ddrAXI_rid: in std_logic_vector(5 downto 0);
			ddrAXI_rdata: in std_logic_vector(511 downto 0);
			ddrAXI_rlast: in std_logic;
			ddrAXI_rready: out std_logic;
			ddrAXI_rresp: in std_logic_vector(1 downto 0);
			ddrAXI_rvalid: in std_logic;

			ddrAXI_awid: out std_logic_vector(5 downto 0);
			ddrAXI_awaddr: out std_logic_vector(32 downto 0);
			ddrAXI_awburst: out std_logic_vector(1 downto 0);
			ddrAXI_awcache: out std_logic_vector(3 downto 0);
			ddrAXI_awlen: out std_logic_vector(7 downto 0);
			ddrAXI_awlock: out std_logic_vector(0 downto 0);
			ddrAXI_awprot: out std_logic_vector(2 downto 0);
			ddrAXI_awqos: out std_logic_vector(3 downto 0);
			ddrAXI_awready: in std_logic;
			ddrAXI_awregion: out std_logic_vector(3 downto 0);
			ddrAXI_awsize: out std_logic_vector(2 downto 0);
			ddrAXI_awvalid: out std_logic;

			ddrAXI_wdata: out std_logic_vector(511 downto 0);
			ddrAXI_wlast: out std_logic;
			ddrAXI_wready: in std_logic;
			ddrAXI_wstrb: out std_logic_vector(63 downto 0);
			ddrAXI_wvalid: out std_logic;

			ddrAXI_bid: in std_logic_vector(5 downto 0);
			ddrAXI_bready: out std_logic;
			ddrAXI_bresp: in std_logic_vector(1 downto 0);
			ddrAXI_bvalid: in std_logic
		);
	end component;

	component Decim_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			vsync: in std_logic;
			ixTExp: in std_logic_vector(3 downto 0);

			NRow: in std_logic_vector(10 downto 0);
			NCol: in std_logic_vector(10 downto 0);

			grayFromVideoinAXIS_tready: out std_logic;
			grayFromVideoinAXIS_tvalid: in std_logic;
			grayFromVideoinAXIS_tdata: in std_logic_vector(71 downto 0);
			grayFromVideoinAXIS_tlast: in std_logic;

			rgbFromVideoinAXIS_tready: out std_logic;
			rgbFromVideoinAXIS_tvalid: in std_logic;
			rgbFromVideoinAXIS_tdata: in std_logic_vector(35 downto 0);
			rgbFromVideoinAXIS_tlast: in std_logic;

			reqInvAcquire: in std_logic;
			ackInvAcquire: out std_logic;

			acquireIxTExp: in std_logic_vector(7 downto 0);

			reqInvConfig: in std_logic;
			ackInvConfig: out std_logic;

			configRgbNotGray: in std_logic_vector(7 downto 0);
			configEdge: in std_logic_vector(7 downto 0);
			configEdge2: in std_logic_vector(15 downto 0);
			configNDecim: in std_logic_vector(15 downto 0);

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTkst: out std_logic_vector(31 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);

			reqInvUnlock: in std_logic;
			ackInvUnlock: out std_logic;

			tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0);

			reqPvwbufToHostif: in std_logic;
			ackPvwbufToHostif: out std_logic;
			dnePvwbufToHostif: in std_logic;
			avllenPvwbufToHostif: out std_logic_vector(31 downto 0);

			pvwbufToHostifAXIS_tready: in std_logic;
			pvwbufToHostifAXIS_tvalid: out std_logic;
			pvwbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			pvwbufToHostifAXIS_tlast: out std_logic;

			stateStore_dbg: out std_logic_vector(7 downto 0);
			stateStream_dbg: out std_logic_vector(7 downto 0)
		);
	end component;

	component Director_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			NRowRaw: out std_logic_vector(11 downto 0);
			NColRaw: out std_logic_vector(11 downto 0);

			rng: out std_logic;

			reqInvConfig: in std_logic;
			ackInvConfig: out std_logic;

			configNRowRaw: in std_logic_vector(15 downto 0);
			configNColRaw: in std_logic_vector(15 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0)
		);
	end component;

	component Freqprobe_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
		generic (
			fMclk: natural := 50000
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;
			bcdNotHex: in std_logic;
			capt: in std_logic_vector(15 downto 0);
			freq: out std_logic
		);
	end component;

	component Hdreng_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			resetMemclk: in std_logic;
			memclk: in std_logic;

			hdrmemAXI_awaddr: out std_logic_vector(17 downto 0);
			hdrmemAXI_awready: in std_logic;
			hdrmemAXI_awvalid: out std_logic;
			hdrmemAXI_bready: out std_logic;
			hdrmemAXI_bresp: in std_logic_vector(1 downto 0);
			hdrmemAXI_bvalid: in std_logic;
			hdrmemAXI_wdata: out std_logic_vector(127 downto 0);
			hdrmemAXI_wlast: out std_logic;
			hdrmemAXI_wready: in std_logic;
			hdrmemAXI_wvalid: out std_logic;

			reqToDdrifWr: out std_logic;
			ackToDdrifWr: in std_logic;

			hdrmemAXI_araddr: out std_logic_vector(17 downto 0);
			hdrmemAXI_arready: in std_logic;
			hdrmemAXI_arvalid: out std_logic;
			hdrmemAXI_rdata: in std_logic_vector(127 downto 0);
			hdrmemAXI_rlast: in std_logic;
			hdrmemAXI_rready: out std_logic;
			hdrmemAXI_rresp: in std_logic_vector(1 downto 0);
			hdrmemAXI_rvalid: in std_logic;

			reqToDdrifRd: out std_logic;
			ackToDdrifRd: in std_logic;

			vsync: in std_logic;
			ixTExp: in std_logic_vector(3 downto 0);

			NRow: in std_logic_vector(10 downto 0);
			NCol: in std_logic_vector(10 downto 0);

			rgbFromVideoinAXIS_tready: out std_logic;
			rgbFromVideoinAXIS_tvalid: in std_logic;
			rgbFromVideoinAXIS_tdata: in std_logic_vector(35 downto 0);
			rgbFromVideoinAXIS_tlast: in std_logic;

			reqInvAssign: in std_logic;
			ackInvAssign: out std_logic;

			assignIxMem: in std_logic_vector(7 downto 0);

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTkst: out std_logic_vector(31 downto 0);
			getInfoIxMem: out std_logic_vector(7 downto 0);
			getInfoIxMemAcq: out std_logic_vector(7 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);

			tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0)
		);
	end component;

	component Hostif_8c100ea18901433eb4f7c0fdbf115e06 is
		generic (
			fMclk: natural := 50000
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;
			tkclk: in std_logic;
			commok: out std_logic;
			reqReset: out std_logic;

			identGetUnt: in std_logic_vector(95 downto 0);
			identGetVer: in std_logic_vector(63 downto 0);
			identGetHash: in std_logic_vector(63 downto 0);
			identGetWho: in std_logic_vector(63 downto 0);

			identGetCfgFMclk: in std_logic_vector(31 downto 0);
			identGetCfgFMemclk: in std_logic_vector(31 downto 0);

			reqInvCamifConfig: out std_logic;
			ackInvCamifConfig: in std_logic;

			camifConfigHdrNotFix: out std_logic_vector(7 downto 0);
			camifConfigSynthNotLive: out std_logic_vector(7 downto 0);

			reqInvCamifConfigSynth: out std_logic;
			ackInvCamifConfigSynth: in std_logic;

			camifConfigSynthTixVSynthmode: out std_logic_vector(7 downto 0);
			camifConfigSynthTFramepad: out std_logic_vector(15 downto 0);
			camifConfigSynthTLinepad: out std_logic_vector(7 downto 0);

			reqInvCamifSetReg: out std_logic;
			ackInvCamifSetReg: in std_logic;

			camifSetRegAddr: out std_logic_vector(15 downto 0);
			camifSetRegVal: out std_logic_vector(7 downto 0);

			reqInvCamifGetReg: out std_logic;
			ackInvCamifGetReg: in std_logic;

			camifGetRegAddr: out std_logic_vector(15 downto 0);
			camifGetRegVal: in std_logic_vector(7 downto 0);

			reqInvCamifModReg: out std_logic;
			ackInvCamifModReg: in std_logic;

			camifModRegAddr: out std_logic_vector(15 downto 0);
			camifModRegMask: out std_logic_vector(7 downto 0);
			camifModRegVal: out std_logic_vector(7 downto 0);

			reqInvCamifSetCorereg: out std_logic;
			ackInvCamifSetCorereg: in std_logic;

			camifSetCoreregAddr: out std_logic_vector(7 downto 0);
			camifSetCoreregVal: out std_logic_vector(31 downto 0);

			reqInvCamifGetCorereg: out std_logic;
			ackInvCamifGetCorereg: in std_logic;

			camifGetCoreregAddr: out std_logic_vector(7 downto 0);
			camifGetCoreregVal: in std_logic_vector(31 downto 0);

			reqInvCornerAcquire: out std_logic;
			ackInvCornerAcquire: in std_logic;

			reqInvCornerConfig: out std_logic;
			ackInvCornerConfig: in std_logic;

			cornerConfigLinNotLog: out std_logic_vector(7 downto 0);
			cornerConfigThd: out std_logic_vector(7 downto 0);
			cornerConfigRow0: out std_logic_vector(15 downto 0);
			cornerConfigRow1: out std_logic_vector(15 downto 0);
			cornerConfigCol0: out std_logic_vector(15 downto 0);
			cornerConfigCol1: out std_logic_vector(15 downto 0);

			cornerGetInfoTixVState: in std_logic_vector(7 downto 0);
			cornerGetInfoTkst: in std_logic_vector(31 downto 0);
			cornerGetInfoScoreMin: in std_logic_vector(7 downto 0);
			cornerGetInfoScoreMax: in std_logic_vector(7 downto 0);

			reqInvCornerSet: out std_logic;
			ackInvCornerSet: in std_logic;

			cornerSetRng: out std_logic_vector(7 downto 0);

			reqInvCornerUnlock: out std_logic;
			ackInvCornerUnlock: in std_logic;

			ddrifGetStatsNRdA: in std_logic_vector(31 downto 0);
			ddrifGetStatsNRdB: in std_logic_vector(31 downto 0);
			ddrifGetStatsNWrA: in std_logic_vector(31 downto 0);
			ddrifGetStatsNWrB: in std_logic_vector(31 downto 0);

			reqInvDecimAcquire: out std_logic;
			ackInvDecimAcquire: in std_logic;

			decimAcquireIxTExp: out std_logic_vector(7 downto 0);

			reqInvDecimConfig: out std_logic;
			ackInvDecimConfig: in std_logic;

			decimConfigRgbNotGray: out std_logic_vector(7 downto 0);
			decimConfigEdge: out std_logic_vector(7 downto 0);
			decimConfigEdge2: out std_logic_vector(15 downto 0);
			decimConfigNDecim: out std_logic_vector(15 downto 0);

			decimGetInfoTixVState: in std_logic_vector(7 downto 0);
			decimGetInfoTkst: in std_logic_vector(31 downto 0);

			reqInvDecimSet: out std_logic;
			ackInvDecimSet: in std_logic;

			decimSetRng: out std_logic_vector(7 downto 0);

			reqInvDecimUnlock: out std_logic;
			ackInvDecimUnlock: in std_logic;

			reqInvDirectorConfig: out std_logic;
			ackInvDirectorConfig: in std_logic;

			directorConfigNRowRaw: out std_logic_vector(15 downto 0);
			directorConfigNColRaw: out std_logic_vector(15 downto 0);

			reqInvDirectorSet: out std_logic;
			ackInvDirectorSet: in std_logic;

			directorSetRng: out std_logic_vector(7 downto 0);

			reqInvHdrengAssign: out std_logic;
			ackInvHdrengAssign: in std_logic;

			hdrengAssignIxMem: out std_logic_vector(7 downto 0);

			hdrengGetInfoTixVState: in std_logic_vector(7 downto 0);
			hdrengGetInfoTkst: in std_logic_vector(31 downto 0);
			hdrengGetInfoIxMem: in std_logic_vector(7 downto 0);
			hdrengGetInfoIxMemAcq: in std_logic_vector(7 downto 0);

			reqInvHdrengSet: out std_logic;
			ackInvHdrengSet: in std_logic;

			hdrengSetRng: out std_logic_vector(7 downto 0);

			reqInvLaserSet: out std_logic;
			ackInvLaserSet: in std_logic;

			laserSetL: out std_logic_vector(15 downto 0);
			laserSetR: out std_logic_vector(15 downto 0);

			reqInvRotaryConfig: out std_logic;
			ackInvRotaryConfig: in std_logic;

			rotaryConfigTixVStepmode: out std_logic_vector(7 downto 0);
			rotaryConfigTStep: out std_logic_vector(7 downto 0);

			rotaryGetInfoTixVState: in std_logic_vector(7 downto 0);
			rotaryGetInfoAngle: in std_logic_vector(15 downto 0);

			reqInvRotaryMoveto: out std_logic;
			ackInvRotaryMoveto: in std_logic;

			rotaryMovetoAngle: out std_logic_vector(15 downto 0);

			hshktrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);

			reqInvRotarySet: out std_logic;

			hshktrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);

			ackInvRotarySet: in std_logic;

			hshktrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);

			rotarySetRng: out std_logic_vector(7 downto 0);

			hshktrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

			rotarySetCcwNotCw: out std_logic_vector(7 downto 0);

			reqInvHshktrackSet: out std_logic;

			reqInvRotaryZero: out std_logic;

			ackInvHshktrackSet: in std_logic;

			ackInvRotaryZero: in std_logic;

			hshktrackSetRng: out std_logic_vector(7 downto 0);

			reqInvStepmuxSet: out std_logic;

			hshktrackSetTCaptMax: out std_logic_vector(31 downto 0);

			ackInvStepmuxSet: in std_logic;

			reqInvHshktrackSetMask: out std_logic;

			stepmuxSetLinNotRot: out std_logic_vector(7 downto 0);

			ackInvHshktrackSetMask: in std_logic;

			tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0);

			hshktrackSetMaskTixVCapture: out std_logic_vector(7 downto 0);

			reqInvTkclksrcSetTkst: out std_logic;

			reqInvMemtrackClearMask: out std_logic;

			ackInvTkclksrcSetTkst: in std_logic;

			ackInvMemtrackClearMask: in std_logic;

			tkclksrcSetTkstTkst: out std_logic_vector(31 downto 0);

			memtrackGetInfoTixVState: in std_logic_vector(7 downto 0);

			reqInvTraceAcquire: out std_logic;

			memtrackGetInfoTCapt: in std_logic_vector(31 downto 0);

			ackInvTraceAcquire: in std_logic;

			memtrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

			reqInvTraceConfig: out std_logic;

			reqInvMemtrackSelect: out std_logic;

			ackInvTraceConfig: in std_logic;

			ackInvMemtrackSelect: in std_logic;

			traceConfigTixVOrient: out std_logic_vector(7 downto 0);

			memtrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);

			traceConfigRow0: out std_logic_vector(15 downto 0);

			memtrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);

			traceConfigCol0: out std_logic_vector(15 downto 0);

			memtrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);

			traceGetInfoTixVState: in std_logic_vector(7 downto 0);

			memtrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

			traceGetInfoTkst: in std_logic_vector(31 downto 0);

			reqInvMemtrackSet: out std_logic;

			reqInvTraceUnlock: out std_logic;

			ackInvMemtrackSet: in std_logic;

			ackInvTraceUnlock: in std_logic;

			memtrackSetRng: out std_logic_vector(7 downto 0);

			cputrackGetInfoTixVState: in std_logic_vector(7 downto 0);

			memtrackSetTCaptMax: out std_logic_vector(31 downto 0);

			cputrackGetInfoTCapt: in std_logic_vector(31 downto 0);

			reqInvMemtrackSetMask: out std_logic;

			cputrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

			ackInvMemtrackSetMask: in std_logic;

			reqInvCputrackSelect: out std_logic;

			memtrackSetMaskTixVCapture: out std_logic_vector(7 downto 0);

			ackInvCputrackSelect: in std_logic;

			vidtrackGetInfoTixVState: in std_logic_vector(7 downto 0);

			cputrackSelectTixVCapture: out std_logic_vector(7 downto 0);

			vidtrackGetInfoTCapt: in std_logic_vector(31 downto 0);

			cputrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);

			vidtrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

			cputrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);

			reqInvVidtrackSelect: out std_logic;

			cputrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);

			ackInvVidtrackSelect: in std_logic;

			cputrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

			vidtrackSelectTixVCapture: out std_logic_vector(7 downto 0);

			reqInvCputrackSet: out std_logic;

			vidtrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);

			ackInvCputrackSet: in std_logic;

			vidtrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);

			cputrackSetRng: out std_logic_vector(7 downto 0);

			vidtrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);

			cputrackSetTCaptMax: out std_logic_vector(31 downto 0);

			vidtrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

			reqInvHshktrackClearMask: out std_logic;

			reqInvVidtrackSet: out std_logic;

			ackInvHshktrackClearMask: in std_logic;

			ackInvVidtrackSet: in std_logic;

			hshktrackGetInfoTixVState: in std_logic_vector(7 downto 0);

			vidtrackSetRng: out std_logic_vector(7 downto 0);

			hshktrackGetInfoTCapt: in std_logic_vector(31 downto 0);

			vidtrackSetTCaptMax: out std_logic_vector(31 downto 0);

			hshktrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

			reqInvHshktrackSelect: out std_logic;
			ackInvHshktrackSelect: in std_logic;

			reqPvwbufFromDecim: out std_logic;
			ackPvwbufFromDecim: in std_logic;
			dnePvwbufFromDecim: out std_logic;
			avllenPvwbufFromDecim: in std_logic_vector(31 downto 0);

			pvwbufFromDecimAXIS_tready: out std_logic;
			pvwbufFromDecimAXIS_tvalid: in std_logic;
			pvwbufFromDecimAXIS_tdata: in std_logic_vector(31 downto 0);
			pvwbufFromDecimAXIS_tlast: in std_logic;

			reqCoobufFromCorner: out std_logic;
			ackCoobufFromCorner: in std_logic;
			dneCoobufFromCorner: out std_logic;
			avllenCoobufFromCorner: in std_logic_vector(31 downto 0);

			reqFlgbufFromTrace: out std_logic;
			ackFlgbufFromTrace: in std_logic;

			coobufFromCornerAXIS_tready: out std_logic;
			coobufFromCornerAXIS_tvalid: in std_logic;
			coobufFromCornerAXIS_tdata: in std_logic_vector(31 downto 0);
			coobufFromCornerAXIS_tlast: in std_logic;

			dneFlgbufFromTrace: out std_logic;
			avllenFlgbufFromTrace: in std_logic_vector(31 downto 0);

			flgbufFromTraceAXIS_tready: out std_logic;
			flgbufFromTraceAXIS_tvalid: in std_logic;
			flgbufFromTraceAXIS_tdata: in std_logic_vector(31 downto 0);
			flgbufFromTraceAXIS_tlast: in std_logic;

			reqSeqbufFromCputrack: out std_logic;
			ackSeqbufFromCputrack: in std_logic;
			dneSeqbufFromCputrack: out std_logic;
			avllenSeqbufFromCputrack: in std_logic_vector(31 downto 0);

			seqbufFromCputrackAXIS_tready: out std_logic;
			seqbufFromCputrackAXIS_tvalid: in std_logic;
			seqbufFromCputrackAXIS_tdata: in std_logic_vector(31 downto 0);
			seqbufFromCputrackAXIS_tlast: in std_logic;

			reqSeqbufFromHshktrack: out std_logic;
			ackSeqbufFromHshktrack: in std_logic;
			dneSeqbufFromHshktrack: out std_logic;
			avllenSeqbufFromHshktrack: in std_logic_vector(31 downto 0);

			reqSeqbufFromMemtrack: out std_logic;
			ackSeqbufFromMemtrack: in std_logic;
			dneSeqbufFromMemtrack: out std_logic;
			avllenSeqbufFromMemtrack: in std_logic_vector(31 downto 0);

			seqbufFromHshktrackAXIS_tready: out std_logic;
			seqbufFromHshktrackAXIS_tvalid: in std_logic;
			seqbufFromHshktrackAXIS_tdata: in std_logic_vector(31 downto 0);
			seqbufFromHshktrackAXIS_tlast: in std_logic;

			seqbufFromMemtrackAXIS_tready: out std_logic;

			reqSeqbufFromVidtrack: out std_logic;
			ackSeqbufFromVidtrack: in std_logic;
			dneSeqbufFromVidtrack: out std_logic;
			avllenSeqbufFromVidtrack: in std_logic_vector(31 downto 0);

			seqbufFromMemtrackAXIS_tvalid: in std_logic;
			seqbufFromMemtrackAXIS_tdata: in std_logic_vector(31 downto 0);
			seqbufFromMemtrackAXIS_tlast: in std_logic;

			seqbufFromVidtrackAXIS_tready: out std_logic;
			seqbufFromVidtrackAXIS_tvalid: in std_logic;
			seqbufFromVidtrackAXIS_tdata: in std_logic_vector(31 downto 0);
			seqbufFromVidtrackAXIS_tlast: in std_logic;

			AXIL_araddr: in std_logic_vector(31 downto 0);
			AXIL_arprot: in std_logic_vector(2 downto 0);
			AXIL_arready: out std_logic;
			AXIL_arvalid: in std_logic;
			AXIL_rdata: out std_logic_vector(31 downto 0);
			AXIL_rready: in std_logic;
			AXIL_rresp: out std_logic_vector(1 downto 0);
			AXIL_rvalid: out std_logic;
			AXIL_rlast: out std_logic;
			AXIL_awaddr: in std_logic_vector(31 downto 0);
			AXIL_awprot: in std_logic_vector(2 downto 0);
			AXIL_awready: out std_logic;
			AXIL_awvalid: in std_logic;
			AXIL_wdata: in std_logic_vector(31 downto 0);
			AXIL_wready: out std_logic;
			AXIL_wstrb: in std_logic_vector(3 downto 0);
			AXIL_wvalid: in std_logic;
			AXIL_bready: in std_logic;
			AXIL_bresp: out std_logic_vector(1 downto 0);
			AXIL_bvalid: out std_logic;

			stateOp_dbg: out std_logic_vector(7 downto 0)
		);
	end component;

	component Hshktrack_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			trigA: in std_logic;
			trigB: in std_logic;
			trigC: in std_logic;
			trigD: in std_logic;

			reqInvClearMask: in std_logic;
			ackInvClearMask: out std_logic;

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTCapt: out std_logic_vector(31 downto 0);
			getInfoPtr0Seqbuf: out std_logic_vector(15 downto 0);

			reqInvSelect: in std_logic;
			ackInvSelect: out std_logic;

			selectStaTixVTrigger: in std_logic_vector(7 downto 0);
			selectStaFallingNotRising: in std_logic_vector(7 downto 0);
			selectStoTixVTrigger: in std_logic_vector(7 downto 0);
			selectStoFallingNotRising: in std_logic_vector(7 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);
			setTCaptMax: in std_logic_vector(31 downto 0);

			reqInvSetMask: in std_logic;
			ackInvSetMask: out std_logic;

			setMaskTixVCapture: in std_logic_vector(7 downto 0);

			reqSeqbufToHostif: in std_logic;
			ackSeqbufToHostif: out std_logic;
			dneSeqbufToHostif: in std_logic;
			avllenSeqbufToHostif: out std_logic_vector(31 downto 0);

			seqbufToHostifAXIS_tready: in std_logic;
			seqbufToHostifAXIS_tvalid: out std_logic;
			seqbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			seqbufToHostifAXIS_tlast: out std_logic;

			vsync: in std_logic;
			cornerGetInfoTixVState: in std_logic_vector(1 downto 0);
			reqInvRotarySet: in std_logic;
			rotaryToStepmuxStep: in std_logic
		);
	end component;

	component Ident_8c100ea18901433eb4f7c0fdbf115e06 is
		generic (
			fMclk: natural := 0;
			fMemclk: natural := 0
		);
		port (
			getUnt: out std_logic_vector(95 downto 0);
			getVer: out std_logic_vector(63 downto 0);
			getHash: out std_logic_vector(63 downto 0);
			getWho: out std_logic_vector(63 downto 0);

			getCfgFMclk: out std_logic_vector(31 downto 0);
			getCfgFMemclk: out std_logic_vector(31 downto 0)
		);
	end component;

	component Laser_8c100ea18901433eb4f7c0fdbf115e06 is
		generic (
			fMclk: natural := 50000
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setL: in std_logic_vector(15 downto 0);
			setR: in std_logic_vector(15 downto 0);

			nss: out std_logic;
			sclk: out std_logic;
			mosi: out std_logic
		);
	end component;

	component Linear_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;
			toStepmuxNslp: out std_logic;
			toStepmuxM0: out std_logic;
			toStepmuxM0z: out std_logic;
			toStepmuxM1: out std_logic;
			toStepmuxDir: out std_logic;
			toStepmuxStep: out std_logic
		);
	end component;

	component Memtrack_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			resetMemclk: in std_logic;
			memclk: in std_logic;

			vsync: in std_logic;
			rgbVideoinToManyAXIS_tlast: in std_logic;

			reqInvClearMask: in std_logic;
			ackInvClearMask: out std_logic;

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTCapt: out std_logic_vector(31 downto 0);
			getInfoPtr0Seqbuf: out std_logic_vector(15 downto 0);

			reqInvSelect: in std_logic;
			ackInvSelect: out std_logic;

			selectStaTixVTrigger: in std_logic_vector(7 downto 0);
			selectStaFallingNotRising: in std_logic_vector(7 downto 0);
			selectStoTixVTrigger: in std_logic_vector(7 downto 0);
			selectStoFallingNotRising: in std_logic_vector(7 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);
			setTCaptMax: in std_logic_vector(31 downto 0);

			reqInvSetMask: in std_logic;
			ackInvSetMask: out std_logic;

			setMaskTixVCapture: in std_logic_vector(7 downto 0);

			reqSeqbufToHostif: in std_logic;
			ackSeqbufToHostif: out std_logic;
			dneSeqbufToHostif: in std_logic;
			avllenSeqbufToHostif: out std_logic_vector(31 downto 0);

			seqbufToHostifAXIS_tready: in std_logic;
			seqbufToHostifAXIS_tvalid: out std_logic;
			seqbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			seqbufToHostifAXIS_tlast: out std_logic;

			reqHdrengToDdrifRd: in std_logic;
			ackHdrengToDdrifRd: in std_logic;
			reqHdrengToDdrifWr: in std_logic;
			ackHdrengToDdrifWr: in std_logic;
			ddrAXI_rvalid: in std_logic;
			ddrAXI_rready_sig: in std_logic;
			ddrAXI_wready: in std_logic;
			ddrAXI_bvalid: in std_logic;
			ddrAXI_wvalid_sig: in std_logic
		);
	end component;

	component Render_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			resetMemclk: in std_logic;
			memclk: in std_logic;

			rndmemAXI_awaddr: out std_logic_vector(17 downto 0);
			rndmemAXI_awready: in std_logic;
			rndmemAXI_awvalid: out std_logic;
			rndmemAXI_wdata: out std_logic_vector(127 downto 0);
			rndmemAXI_wlast: out std_logic;
			rndmemAXI_wready: in std_logic;
			rndmemAXI_wvalid: out std_logic;

			reqToDdrifWr: out std_logic;
			ackToDdrifWr: in std_logic;

			rndmemAXI_araddr: out std_logic_vector(17 downto 0);
			rndmemAXI_arready: in std_logic;
			rndmemAXI_arvalid: out std_logic;
			rndmemAXI_rdata: in std_logic_vector(127 downto 0);
			rndmemAXI_rlast: in std_logic;
			rndmemAXI_rready: out std_logic;
			rndmemAXI_rresp: in std_logic_vector(1 downto 0);
			rndmemAXI_rvalid: in std_logic;

			reqToDdrifRd: out std_logic;
			ackToDdrifRd: in std_logic
		);
	end component;

	component Rgbled_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
		generic (
			fMclk: natural := 50000
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;
			rgb: in std_logic_vector(23 downto 0);

			r: out std_logic;
			g: out std_logic;
			b: out std_logic
		);
	end component;

	component Rotary_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;
			tkclk: in std_logic;

			toStepmuxNslp: out std_logic;
			toStepmuxM0: out std_logic;
			toStepmuxM0z: out std_logic;
			toStepmuxM1: out std_logic;
			toStepmuxDir: out std_logic;
			toStepmuxStep: out std_logic;

			reqInvConfig: in std_logic;
			ackInvConfig: out std_logic;

			configTixVStepmode: in std_logic_vector(7 downto 0);
			configTStep: in std_logic_vector(7 downto 0);

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoAngle: out std_logic_vector(15 downto 0);

			reqInvMoveto: in std_logic;
			ackInvMoveto: out std_logic;

			movetoAngle: in std_logic_vector(15 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);
			setCcwNotCw: in std_logic_vector(7 downto 0);

			reqInvZero: in std_logic;
			ackInvZero: out std_logic
		);
	end component;

	component State_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;
			tkclk: in std_logic;
			commok: in std_logic;
			rng: in std_logic;
			rgb: out std_logic_vector(23 downto 0)
		);
	end component;

	component Stepmux_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			fromLinearNslp: in std_logic;
			fromLinearM0: in std_logic;
			fromLinearM0z: in std_logic;
			fromLinearM1: in std_logic;
			fromLinearDir: in std_logic;
			fromLinearStep: in std_logic;

			fromRotaryNslp: in std_logic;
			fromRotaryM0: in std_logic;
			fromRotaryM0z: in std_logic;
			fromRotaryM1: in std_logic;
			fromRotaryDir: in std_logic;
			fromRotaryStep: in std_logic;

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setLinNotRot: in std_logic_vector(7 downto 0);

			nslp: out std_logic;

			m0: out std_logic;
			m0z: out std_logic;

			m1: out std_logic;
			m1z: out std_logic;

			dir: out std_logic;
			step: out std_logic
		);
	end component;

	component Tkclksrc_Easy_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
		generic (
			fMclk: natural := 50000
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;
			tkclk: out std_logic;

			getTkstTkst: out std_logic_vector(31 downto 0);

			reqInvSetTkst: in std_logic;
			ackInvSetTkst: out std_logic;

			setTkstTkst: in std_logic_vector(31 downto 0);

			stateOp_dbg: out std_logic_vector(7 downto 0)
		);
	end component;

	component Trace_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			vsync: in std_logic;
			ixTExp: in std_logic_vector(3 downto 0);

			NRow: in std_logic_vector(10 downto 0);
			NCol: in std_logic_vector(10 downto 0);

			rgbFromVideoinAXIS_tready: out std_logic;
			rgbFromVideoinAXIS_tvalid: in std_logic;
			rgbFromVideoinAXIS_tdata: in std_logic_vector(35 downto 0);
			rgbFromVideoinAXIS_tlast: in std_logic;

			tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0);

			reqInvAcquire: in std_logic;
			ackInvAcquire: out std_logic;

			reqInvConfig: in std_logic;
			ackInvConfig: out std_logic;

			configTixVOrient: in std_logic_vector(7 downto 0);
			configRow0: in std_logic_vector(15 downto 0);
			configCol0: in std_logic_vector(15 downto 0);

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTkst: out std_logic_vector(31 downto 0);

			reqInvUnlock: in std_logic;
			ackInvUnlock: out std_logic;

			reqFlgbufToHostif: in std_logic;
			ackFlgbufToHostif: out std_logic;
			dneFlgbufToHostif: in std_logic;
			avllenFlgbufToHostif: out std_logic_vector(31 downto 0);

			flgbufToHostifAXIS_tready: in std_logic;
			flgbufToHostifAXIS_tvalid: out std_logic;
			flgbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			flgbufToHostifAXIS_tlast: out std_logic
		);
	end component;

	component Vecrend_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic
		);
	end component;

	component Videoin_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			fromCamifAXIS_tready: out std_logic;
			fromCamifAXIS_tvalid: in std_logic;
			fromCamifAXIS_tdata: in std_logic_vector(23 downto 0);
			fromCamifAXIS_tlast: in std_logic;

			vsync: in std_logic;
			NCol: in std_logic_vector(10 downto 0);

			grayToManyAXIS_tready: in std_logic;
			grayToManyAXIS_tvalid: out std_logic;
			grayToManyAXIS_tdata: out std_logic_vector(71 downto 0);
			grayToManyAXIS_tlast: out std_logic;

			rgbToManyAXIS_tready: in std_logic;
			rgbToManyAXIS_tvalid: out std_logic;
			rgbToManyAXIS_tdata: out std_logic_vector(35 downto 0);
			rgbToManyAXIS_tlast: out std_logic;

			stateIgr_dbg: out std_logic_vector(7 downto 0);
			stateRgbegr_dbg: out std_logic_vector(7 downto 0)
		);
	end component;

	component Vidtrack_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			trigA: in std_logic;
			trigB: in std_logic;
			trigC: in std_logic;
			trigD: in std_logic;

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTCapt: out std_logic_vector(31 downto 0);
			getInfoPtr0Seqbuf: out std_logic_vector(15 downto 0);

			reqInvSelect: in std_logic;
			ackInvSelect: out std_logic;

			selectTixVCapture: in std_logic_vector(7 downto 0);
			selectStaTixVTrigger: in std_logic_vector(7 downto 0);
			selectStaFallingNotRising: in std_logic_vector(7 downto 0);
			selectStoTixVTrigger: in std_logic_vector(7 downto 0);
			selectStoFallingNotRising: in std_logic_vector(7 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);
			setTCaptMax: in std_logic_vector(31 downto 0);

			reqSeqbufToHostif: in std_logic;
			ackSeqbufToHostif: out std_logic;
			dneSeqbufToHostif: in std_logic;
			avllenSeqbufToHostif: out std_logic_vector(31 downto 0);

			seqbufToHostifAXIS_tready: in std_logic;
			seqbufToHostifAXIS_tvalid: out std_logic;
			seqbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			seqbufToHostifAXIS_tlast: out std_logic;

			videoinStateIgr: in std_logic_vector(7 downto 0);
			videoinStateRgbegr: in std_logic_vector(7 downto 0);
			decimStateStream: in std_logic_vector(7 downto 0);
			decimStateStore: in std_logic_vector(7 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- mclk wiring and reset (mclk)
	type stateMclk_t is (
		stateMclkReset,
		stateMclkRun
	);
	signal stateMclk: stateMclk_t;

	signal reset: std_logic;
	signal mclk: std_logic;

	-- IP sigs.mclk.cust --- INSERT

	---- memclk wiring and reset (memclk)
	type stateMemclk_t is (
		stateMemclkReset,
		stateMemclkRun
	);
	signal stateMemclk: stateMemclk_t;

	signal resetMemclk: std_logic;

	signal reset_memclk: std_logic;
	signal reset_to_memclkm1: std_logic;
	signal reset_to_memclkm2: std_logic;

	-- IP sigs.memclk.cust --- INSERT

	---- pixrxclk wiring and reset (pixrxclk)
	type statePixrxclk_t is (
		statePixrxclkReset,
		statePixrxclkRun
	);
	signal statePixrxclk: statePixrxclk_t;

	signal resetPixrxclk: std_logic;

	signal reset_pixrxclk: std_logic;
	signal reset_to_pixrxclkm1: std_logic;
	signal reset_to_pixrxclkm2: std_logic;

	-- IP sigs.pixrxclk.cust --- INSERT

	---- myCamif
	signal camifGetRegVal: std_logic_vector(7 downto 0);

	signal camifGetCoreregVal: std_logic_vector(31 downto 0);

	signal camifToVideoinAXIS_tvalid: std_logic;
	signal camifToVideoinAXIS_tdata: std_logic_vector(23 downto 0);
	signal camifToVideoinAXIS_tlast: std_logic;

	signal vsync: std_logic;
	signal ixTExp: std_logic_vector(3 downto 0);

	signal camifDatatype_dbg: std_logic_vector(5 downto 0);
	signal camifMipiAXIS_dbg: std_logic_vector(3 downto 0);
	signal camifVideo_out_dbg: std_logic_vector(3 downto 0);

	signal camifStateConfig_dbg: std_logic_vector(7 downto 0);

	---- myCorner
	signal avllenCoobufCornerToHostif: std_logic_vector(31 downto 0);

	signal coobufCornerToHostifAXIS_tvalid: std_logic;
	signal coobufCornerToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal coobufCornerToHostifAXIS_tlast: std_logic;

	signal cornerGetInfoTixVState: std_logic_vector(7 downto 0);
	signal cornerGetInfoTkst: std_logic_vector(31 downto 0);
	signal cornerGetInfoScoreMin: std_logic_vector(7 downto 0);
	signal cornerGetInfoScoreMax: std_logic_vector(7 downto 0);

	---- myCputrack
	signal avllenSeqbufCputrackToHostif: std_logic_vector(31 downto 0);

	signal seqbufCputrackToHostifAXIS_tvalid: std_logic;
	signal seqbufCputrackToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal seqbufCputrackToHostifAXIS_tlast: std_logic;

	signal cputrackGetInfoTixVState: std_logic_vector(7 downto 0);
	signal cputrackGetInfoTCapt: std_logic_vector(31 downto 0);
	signal cputrackGetInfoPtr0Seqbuf: std_logic_vector(15 downto 0);

	---- myDdrif
	signal hdrmemAXI_arready: std_logic;
	signal hdrmemAXI_rdata: std_logic_vector(127 downto 0);
	signal hdrmemAXI_rlast: std_logic;
	signal hdrmemAXI_rresp: std_logic_vector(1 downto 0);
	signal hdrmemAXI_rvalid: std_logic;

	signal hdrmemAXI_awready: std_logic;
	signal hdrmemAXI_bresp: std_logic_vector(1 downto 0);
	signal hdrmemAXI_bvalid: std_logic;
	signal hdrmemAXI_wready: std_logic;

	signal rndmemAXI_arready: std_logic;
	signal rndmemAXI_rdata: std_logic_vector(127 downto 0);
	signal rndmemAXI_rlast: std_logic;
	signal rndmemAXI_rresp: std_logic_vector(1 downto 0);
	signal rndmemAXI_rvalid: std_logic;

	signal rndmemAXI_awready: std_logic;
	signal rndmemAXI_bresp: std_logic_vector(1 downto 0);
	signal rndmemAXI_bvalid: std_logic;
	signal rndmemAXI_wready: std_logic;

	signal ddrifGetStatsNRdA: std_logic_vector(31 downto 0);
	signal ddrifGetStatsNRdB: std_logic_vector(31 downto 0);
	signal ddrifGetStatsNWrA: std_logic_vector(31 downto 0);
	signal ddrifGetStatsNWrB: std_logic_vector(31 downto 0);

	signal ddrAXI_rready_sig: std_logic;
	signal ddrAXI_wvalid_sig: std_logic;

	---- myDecim
	signal avllenPvwbufDecimToHostif: std_logic_vector(31 downto 0);

	signal pvwbufDecimToHostifAXIS_tvalid: std_logic;
	signal pvwbufDecimToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal pvwbufDecimToHostifAXIS_tlast: std_logic;

	signal decimGetInfoTixVState: std_logic_vector(7 downto 0);
	signal decimGetInfoTkst: std_logic_vector(31 downto 0);

	signal decimStateStore_dbg: std_logic_vector(7 downto 0);
	signal decimStateStream_dbg: std_logic_vector(7 downto 0);

	---- myDirector
	signal rng: std_logic;

	signal NRowRaw: std_logic_vector(11 downto 0);
	signal NColRaw: std_logic_vector(11 downto 0);

	---- myFreqprobeDbg0
	signal freqDbg0: std_logic;

	---- myFreqprobeDbg1
	signal freqDbg1: std_logic;

	---- myGbufceAclk
	signal aclk_sig: std_logic;

	---- myHdreng
	signal hdrmemAXI_araddr: std_logic_vector(17 downto 0);
	signal hdrmemAXI_arvalid: std_logic;
	signal hdrmemAXI_rready: std_logic;

	signal hdrmemAXI_awaddr: std_logic_vector(17 downto 0);
	signal hdrmemAXI_awvalid: std_logic;
	signal hdrmemAXI_bready: std_logic;
	signal hdrmemAXI_wdata: std_logic_vector(127 downto 0);
	signal hdrmemAXI_wlast: std_logic;
	signal hdrmemAXI_wvalid: std_logic;

	signal hdrengGetInfoTixVState: std_logic_vector(7 downto 0);
	signal hdrengGetInfoTkst: std_logic_vector(31 downto 0);
	signal hdrengGetInfoIxMem: std_logic_vector(7 downto 0);
	signal hdrengGetInfoIxMemAcq: std_logic_vector(7 downto 0);

	---- myHostif
	signal commok: std_logic;

	signal pvwbufDecimToHostifAXIS_tready: std_logic;

	signal coobufCornerToHostifAXIS_tready: std_logic;

	signal flgbufTraceToHostifAXIS_tready: std_logic;

	signal camifConfigHdrNotFix: std_logic_vector(7 downto 0);
	signal camifConfigSynthNotLive: std_logic_vector(7 downto 0);

	signal camifConfigSynthTixVSynthmode: std_logic_vector(7 downto 0);
	signal camifConfigSynthTFramepad: std_logic_vector(15 downto 0);
	signal camifConfigSynthTLinepad: std_logic_vector(7 downto 0);

	signal seqbufCputrackToHostifAXIS_tready: std_logic;

	signal camifSetRegAddr: std_logic_vector(15 downto 0);

	signal seqbufHshktrackToHostifAXIS_tready: std_logic;

	signal camifSetRegVal: std_logic_vector(7 downto 0);

	signal seqbufMemtrackToHostifAXIS_tready: std_logic;

	signal camifGetRegAddr: std_logic_vector(15 downto 0);

	signal camifModRegAddr: std_logic_vector(15 downto 0);
	signal camifModRegMask: std_logic_vector(7 downto 0);
	signal camifModRegVal: std_logic_vector(7 downto 0);

	signal seqbufVidtrackToHostifAXIS_tready: std_logic;

	signal camifSetCoreregAddr: std_logic_vector(7 downto 0);
	signal camifSetCoreregVal: std_logic_vector(31 downto 0);

	signal camifGetCoreregAddr: std_logic_vector(7 downto 0);

	signal cornerConfigLinNotLog: std_logic_vector(7 downto 0);
	signal cornerConfigThd: std_logic_vector(7 downto 0);
	signal cornerConfigRow0: std_logic_vector(15 downto 0);
	signal cornerConfigRow1: std_logic_vector(15 downto 0);
	signal cornerConfigCol0: std_logic_vector(15 downto 0);
	signal cornerConfigCol1: std_logic_vector(15 downto 0);

	signal cornerSetRng: std_logic_vector(7 downto 0);

	signal decimAcquireIxTExp: std_logic_vector(7 downto 0);

	signal decimConfigRgbNotGray: std_logic_vector(7 downto 0);
	signal decimConfigEdge: std_logic_vector(7 downto 0);
	signal decimConfigEdge2: std_logic_vector(15 downto 0);
	signal decimConfigNDecim: std_logic_vector(15 downto 0);

	signal decimSetRng: std_logic_vector(7 downto 0);

	signal directorConfigNRowRaw: std_logic_vector(15 downto 0);
	signal directorConfigNColRaw: std_logic_vector(15 downto 0);

	signal directorSetRng: std_logic_vector(7 downto 0);

	signal hdrengAssignIxMem: std_logic_vector(7 downto 0);

	signal hdrengSetRng: std_logic_vector(7 downto 0);

	signal laserSetL: std_logic_vector(15 downto 0);
	signal laserSetR: std_logic_vector(15 downto 0);

	signal rotaryConfigTixVStepmode: std_logic_vector(7 downto 0);
	signal rotaryConfigTStep: std_logic_vector(7 downto 0);

	signal rotaryMovetoAngle: std_logic_vector(15 downto 0);

	signal rotarySetRng: std_logic_vector(7 downto 0);
	signal rotarySetCcwNotCw: std_logic_vector(7 downto 0);

	signal stepmuxSetLinNotRot: std_logic_vector(7 downto 0);

	signal tkclksrcSetTkstTkst: std_logic_vector(31 downto 0);

	signal traceConfigTixVOrient: std_logic_vector(7 downto 0);
	signal traceConfigRow0: std_logic_vector(15 downto 0);
	signal traceConfigCol0: std_logic_vector(15 downto 0);

	signal cputrackSelectTixVCapture: std_logic_vector(7 downto 0);
	signal cputrackSelectStaTixVTrigger: std_logic_vector(7 downto 0);
	signal cputrackSelectStaFallingNotRising: std_logic_vector(7 downto 0);
	signal cputrackSelectStoTixVTrigger: std_logic_vector(7 downto 0);
	signal cputrackSelectStoFallingNotRising: std_logic_vector(7 downto 0);

	signal cputrackSetRng: std_logic_vector(7 downto 0);
	signal cputrackSetTCaptMax: std_logic_vector(31 downto 0);

	signal hshktrackSelectStaTixVTrigger: std_logic_vector(7 downto 0);
	signal hshktrackSelectStaFallingNotRising: std_logic_vector(7 downto 0);
	signal hshktrackSelectStoTixVTrigger: std_logic_vector(7 downto 0);
	signal hshktrackSelectStoFallingNotRising: std_logic_vector(7 downto 0);

	signal hshktrackSetRng: std_logic_vector(7 downto 0);
	signal hshktrackSetTCaptMax: std_logic_vector(31 downto 0);

	signal hshktrackSetMaskTixVCapture: std_logic_vector(7 downto 0);

	signal memtrackSelectStaTixVTrigger: std_logic_vector(7 downto 0);
	signal memtrackSelectStaFallingNotRising: std_logic_vector(7 downto 0);
	signal memtrackSelectStoTixVTrigger: std_logic_vector(7 downto 0);
	signal memtrackSelectStoFallingNotRising: std_logic_vector(7 downto 0);

	signal memtrackSetRng: std_logic_vector(7 downto 0);
	signal memtrackSetTCaptMax: std_logic_vector(31 downto 0);

	signal memtrackSetMaskTixVCapture: std_logic_vector(7 downto 0);

	signal vidtrackSelectTixVCapture: std_logic_vector(7 downto 0);
	signal vidtrackSelectStaTixVTrigger: std_logic_vector(7 downto 0);
	signal vidtrackSelectStaFallingNotRising: std_logic_vector(7 downto 0);
	signal vidtrackSelectStoTixVTrigger: std_logic_vector(7 downto 0);
	signal vidtrackSelectStoFallingNotRising: std_logic_vector(7 downto 0);

	signal vidtrackSetRng: std_logic_vector(7 downto 0);
	signal vidtrackSetTCaptMax: std_logic_vector(31 downto 0);

	signal hostifStateOp_dbg: std_logic_vector(7 downto 0);

	---- myHshktrack
	signal avllenSeqbufHshktrackToHostif: std_logic_vector(31 downto 0);

	signal seqbufHshktrackToHostifAXIS_tvalid: std_logic;
	signal seqbufHshktrackToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal seqbufHshktrackToHostifAXIS_tlast: std_logic;

	signal hshktrackGetInfoTixVState: std_logic_vector(7 downto 0);
	signal hshktrackGetInfoTCapt: std_logic_vector(31 downto 0);
	signal hshktrackGetInfoPtr0Seqbuf: std_logic_vector(15 downto 0);

	---- myIdent
	signal identGetUnt: std_logic_vector(95 downto 0);
	signal identGetVer: std_logic_vector(63 downto 0);
	signal identGetHash: std_logic_vector(63 downto 0);
	signal identGetWho: std_logic_vector(63 downto 0);

	signal identGetCfgFMclk: std_logic_vector(31 downto 0);
	signal identGetCfgFMemclk: std_logic_vector(31 downto 0);

	---- myLinear
	signal linearToStepmuxNslp: std_logic;
	signal linearToStepmuxM0: std_logic;
	signal linearToStepmuxM0z: std_logic;
	signal linearToStepmuxM1: std_logic;
	signal linearToStepmuxDir: std_logic;
	signal linearToStepmuxStep: std_logic;

	---- myMemtrack
	signal avllenSeqbufMemtrackToHostif: std_logic_vector(31 downto 0);

	signal seqbufMemtrackToHostifAXIS_tvalid: std_logic;
	signal seqbufMemtrackToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal seqbufMemtrackToHostifAXIS_tlast: std_logic;

	signal memtrackGetInfoTixVState: std_logic_vector(7 downto 0);
	signal memtrackGetInfoTCapt: std_logic_vector(31 downto 0);
	signal memtrackGetInfoPtr0Seqbuf: std_logic_vector(15 downto 0);

	---- myRender
	signal rndmemAXI_araddr: std_logic_vector(17 downto 0);
	signal rndmemAXI_arvalid: std_logic;
	signal rndmemAXI_rready: std_logic;

	signal rndmemAXI_awaddr: std_logic_vector(17 downto 0);
	signal rndmemAXI_awvalid: std_logic;
	signal rndmemAXI_bready: std_logic;
	signal rndmemAXI_wdata: std_logic_vector(127 downto 0);
	signal rndmemAXI_wlast: std_logic;
	signal rndmemAXI_wvalid: std_logic;

	---- myRotary
	signal rotaryToStepmuxNslp: std_logic;
	signal rotaryToStepmuxM0: std_logic;
	signal rotaryToStepmuxM0z: std_logic;
	signal rotaryToStepmuxM1: std_logic;
	signal rotaryToStepmuxDir: std_logic;
	signal rotaryToStepmuxStep: std_logic;

	signal rotaryGetInfoTixVState: std_logic_vector(7 downto 0);
	signal rotaryGetInfoAngle: std_logic_vector(15 downto 0);

	---- myState
	signal rgb0: std_logic_vector(23 downto 0);
	signal rgb1: std_logic_vector(23 downto 0);

	---- myTkclksrc
	signal tkclk: std_logic;

	signal tkclksrcGetTkstTkst: std_logic_vector(31 downto 0);

	signal tkclksrcStateOp_dbg: std_logic_vector(7 downto 0);

	---- myTrace
	signal avllenFlgbufTraceToHostif: std_logic_vector(31 downto 0);

	signal flgbufTraceToHostifAXIS_tvalid: std_logic;
	signal flgbufTraceToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal flgbufTraceToHostifAXIS_tlast: std_logic;

	signal traceGetInfoTixVState: std_logic_vector(7 downto 0);
	signal traceGetInfoTkst: std_logic_vector(31 downto 0);

	---- myVideoin
	signal camifToVideoinAXIS_tready: std_logic;

	signal grayVideoinToManyAXIS_tvalid: std_logic;
	signal grayVideoinToManyAXIS_tdata: std_logic_vector(71 downto 0);
	signal grayVideoinToManyAXIS_tlast: std_logic;

	signal rgbVideoinToManyAXIS_tvalid: std_logic;
	signal rgbVideoinToManyAXIS_tdata: std_logic_vector(35 downto 0);
	signal rgbVideoinToManyAXIS_tlast: std_logic;

	signal videoinStateIgr_dbg: std_logic_vector(7 downto 0);
	signal videoinStateRgbegr_dbg: std_logic_vector(7 downto 0);

	---- myVidtrack
	signal avllenSeqbufVidtrackToHostif: std_logic_vector(31 downto 0);

	signal seqbufVidtrackToHostifAXIS_tvalid: std_logic;
	signal seqbufVidtrackToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal seqbufVidtrackToHostifAXIS_tlast: std_logic;

	signal vidtrackGetInfoTixVState: std_logic_vector(7 downto 0);
	signal vidtrackGetInfoTCapt: std_logic_vector(31 downto 0);
	signal vidtrackGetInfoPtr0Seqbuf: std_logic_vector(15 downto 0);

	---- handshake
	-- myHostif to myDecim
	signal reqPvwbufDecimToHostif: std_logic;
	signal ackPvwbufDecimToHostif: std_logic;
	signal dnePvwbufDecimToHostif: std_logic;

	-- myHostif to myCorner
	signal reqCoobufCornerToHostif: std_logic;
	signal ackCoobufCornerToHostif: std_logic;
	signal dneCoobufCornerToHostif: std_logic;

	-- myHostif to myTrace
	signal reqFlgbufTraceToHostif: std_logic;
	signal ackFlgbufTraceToHostif: std_logic;
	signal dneFlgbufTraceToHostif: std_logic;

	-- myHostif to (many)
	signal reqResetFromHostif: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifConfig: std_logic;
	signal ackInvCamifConfig: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifConfigSynth: std_logic;
	signal ackInvCamifConfigSynth: std_logic;

	-- myHostif to myCputrack
	signal reqSeqbufCputrackToHostif: std_logic;
	signal ackSeqbufCputrackToHostif: std_logic;
	signal dneSeqbufCputrackToHostif: std_logic;

	-- myHostif to myHshktrack
	signal reqSeqbufHshktrackToHostif: std_logic;
	signal ackSeqbufHshktrackToHostif: std_logic;
	signal dneSeqbufHshktrackToHostif: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifSetReg: std_logic;
	signal ackInvCamifSetReg: std_logic;

	-- myHostif to myMemtrack
	signal reqSeqbufMemtrackToHostif: std_logic;
	signal ackSeqbufMemtrackToHostif: std_logic;
	signal dneSeqbufMemtrackToHostif: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifGetReg: std_logic;
	signal ackInvCamifGetReg: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifModReg: std_logic;
	signal ackInvCamifModReg: std_logic;

	-- myHostif to myVidtrack
	signal reqSeqbufVidtrackToHostif: std_logic;
	signal ackSeqbufVidtrackToHostif: std_logic;
	signal dneSeqbufVidtrackToHostif: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifSetCorereg: std_logic;
	signal ackInvCamifSetCorereg: std_logic;

	-- myRender to myDdrif
	signal reqRenderToDdrifWr: std_logic;
	signal ackRenderToDdrifWr: std_logic;

	-- myRender to myDdrif
	signal reqRenderToDdrifRd: std_logic;
	signal ackRenderToDdrifRd: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifGetCorereg: std_logic;
	signal ackInvCamifGetCorereg: std_logic;

	-- myHdreng to myDdrif
	signal reqHdrengToDdrifWr: std_logic;
	signal ackHdrengToDdrifWr: std_logic;

	-- myHdreng to myDdrif
	signal reqHdrengToDdrifRd: std_logic;
	signal ackHdrengToDdrifRd: std_logic;

	-- myHostif to myCorner
	signal reqInvCornerAcquire: std_logic;
	signal ackInvCornerAcquire: std_logic;

	-- myHostif to myCorner
	signal reqInvCornerConfig: std_logic;
	signal ackInvCornerConfig: std_logic;

	-- myHostif to myCorner
	signal reqInvCornerSet: std_logic;
	signal ackInvCornerSet: std_logic;

	-- myHostif to myCorner
	signal reqInvCornerUnlock: std_logic;
	signal ackInvCornerUnlock: std_logic;

	-- myHostif to myDecim
	signal reqInvDecimAcquire: std_logic;
	signal ackInvDecimAcquire: std_logic;

	-- myHostif to myDecim
	signal reqInvDecimConfig: std_logic;
	signal ackInvDecimConfig: std_logic;

	-- myHostif to myDecim
	signal reqInvDecimSet: std_logic;
	signal ackInvDecimSet: std_logic;

	-- myHostif to myDecim
	signal reqInvDecimUnlock: std_logic;
	signal ackInvDecimUnlock: std_logic;

	-- myHostif to myDirector
	signal reqInvDirectorConfig: std_logic;
	signal ackInvDirectorConfig: std_logic;

	-- myHostif to myDirector
	signal reqInvDirectorSet: std_logic;
	signal ackInvDirectorSet: std_logic;

	-- myHostif to myHdreng
	signal reqInvHdrengAssign: std_logic;
	signal ackInvHdrengAssign: std_logic;

	-- myHostif to myHdreng
	signal reqInvHdrengSet: std_logic;
	signal ackInvHdrengSet: std_logic;

	-- myHostif to myLaser
	signal reqInvLaserSet: std_logic;
	signal ackInvLaserSet: std_logic;

	-- myHostif to myRotary
	signal reqInvRotaryConfig: std_logic;
	signal ackInvRotaryConfig: std_logic;

	-- myHostif to myRotary
	signal reqInvRotaryMoveto: std_logic;
	signal ackInvRotaryMoveto: std_logic;

	-- myHostif to myRotary
	signal reqInvRotarySet: std_logic;
	signal ackInvRotarySet: std_logic;

	-- myHostif to myRotary
	signal reqInvRotaryZero: std_logic;
	signal ackInvRotaryZero: std_logic;

	-- myHostif to myStepmux
	signal reqInvStepmuxSet: std_logic;
	signal ackInvStepmuxSet: std_logic;

	-- myHostif to myTkclksrc
	signal reqInvTkclksrcSetTkst: std_logic;
	signal ackInvTkclksrcSetTkst: std_logic;

	-- myHostif to myTrace
	signal reqInvTraceAcquire: std_logic;
	signal ackInvTraceAcquire: std_logic;

	-- myHostif to myTrace
	signal reqInvTraceConfig: std_logic;
	signal ackInvTraceConfig: std_logic;

	-- myHostif to myTrace
	signal reqInvTraceUnlock: std_logic;
	signal ackInvTraceUnlock: std_logic;

	-- myHostif to myCputrack
	signal reqInvCputrackSelect: std_logic;
	signal ackInvCputrackSelect: std_logic;

	-- myHostif to myCputrack
	signal reqInvCputrackSet: std_logic;
	signal ackInvCputrackSet: std_logic;

	-- myHostif to myHshktrack
	signal reqInvHshktrackClearMask: std_logic;
	signal ackInvHshktrackClearMask: std_logic;

	-- myHostif to myHshktrack
	signal reqInvHshktrackSelect: std_logic;
	signal ackInvHshktrackSelect: std_logic;

	-- myHostif to myHshktrack
	signal reqInvHshktrackSet: std_logic;
	signal ackInvHshktrackSet: std_logic;

	-- myHostif to myHshktrack
	signal reqInvHshktrackSetMask: std_logic;
	signal ackInvHshktrackSetMask: std_logic;

	-- myHostif to myMemtrack
	signal reqInvMemtrackClearMask: std_logic;
	signal ackInvMemtrackClearMask: std_logic;

	-- myHostif to myMemtrack
	signal reqInvMemtrackSelect: std_logic;
	signal ackInvMemtrackSelect: std_logic;

	-- myHostif to myMemtrack
	signal reqInvMemtrackSet: std_logic;
	signal ackInvMemtrackSet: std_logic;

	-- myHostif to myMemtrack
	signal reqInvMemtrackSetMask: std_logic;
	signal ackInvMemtrackSetMask: std_logic;

	-- myHostif to myVidtrack
	signal reqInvVidtrackSelect: std_logic;
	signal ackInvVidtrackSelect: std_logic;

	-- myHostif to myVidtrack
	signal reqInvVidtrackSet: std_logic;
	signal ackInvVidtrackSet: std_logic;

	---- other
	signal grayVideoinToManyAXIS_tready: std_logic;

	signal rgbVideoinToManyAXIS_tready: std_logic;

	signal NRow: std_logic_vector(10 downto 0);
	signal NCol: std_logic_vector(10 downto 0);

	signal trigA: std_logic;
	signal trigB: std_logic;
	signal trigC: std_logic;
	signal trigD: std_logic;

	signal dbg0: std_logic_vector(15 downto 0);
	signal dbg1: std_logic_vector(15 downto 0);

	signal probe_sig: std_logic_vector(5 downto 0);
	-- IP sigs.oth.cust --- IBEGIN

	signal ddrAXI_awvalid_sig: std_logic;

	signal apuAXIL_awready_sig: std_logic;
	signal apuAXIL_wready_sig: std_logic;
	signal apuAXIL_bvalid_sig: std_logic;

	signal datatype_dbg: std_logic_vector(5 downto 0);

	signal mipiAXIS_dbg: std_logic_vector(3 downto 0);
	signal video_out_dbg: std_logic_vector(3 downto 0);
	-- IP sigs.oth.cust --- IEND

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myCamif : Camif_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			fMclk => fMclk -- in kHz
		)
		port map (
			reset => reset,
			mclk => mclk,
			resetPixrxclk => resetPixrxclk,
			pixrxclk => pixrxclk,
			tkclk => tkclk,

			NRowRaw => NRowRaw,
			NCol => NCol,

			toVideoinAXIS_tready => camifToVideoinAXIS_tready,
			toVideoinAXIS_tvalid => camifToVideoinAXIS_tvalid,
			toVideoinAXIS_tdata => camifToVideoinAXIS_tdata,
			toVideoinAXIS_tlast => camifToVideoinAXIS_tlast,

			reqInvConfig => reqInvCamifConfig,
			ackInvConfig => ackInvCamifConfig,

			configHdrNotFix => camifConfigHdrNotFix,
			configSynthNotLive => camifConfigSynthNotLive,

			reqInvConfigSynth => reqInvCamifConfigSynth,
			ackInvConfigSynth => ackInvCamifConfigSynth,

			configSynthTixVSynthmode => camifConfigSynthTixVSynthmode,
			configSynthTFramepad => camifConfigSynthTFramepad,
			configSynthTLinepad => camifConfigSynthTLinepad,

			reqInvSetReg => reqInvCamifSetReg,
			ackInvSetReg => ackInvCamifSetReg,

			setRegAddr => camifSetRegAddr,
			setRegVal => camifSetRegVal,

			reqInvGetReg => reqInvCamifGetReg,
			ackInvGetReg => ackInvCamifGetReg,

			getRegAddr => camifGetRegAddr,
			getRegVal => camifGetRegVal,

			reqInvModReg => reqInvCamifModReg,
			ackInvModReg => ackInvCamifModReg,

			modRegAddr => camifModRegAddr,
			modRegMask => camifModRegMask,
			modRegVal => camifModRegVal,

			reqInvSetCorereg => reqInvCamifSetCorereg,
			ackInvSetCorereg => ackInvCamifSetCorereg,

			setCoreregAddr => camifSetCoreregAddr,
			setCoreregVal => camifSetCoreregVal,

			reqInvGetCorereg => reqInvCamifGetCorereg,
			ackInvGetCorereg => ackInvCamifGetCorereg,

			getCoreregAddr => camifGetCoreregAddr,
			getCoreregVal => camifGetCoreregVal,

			rng => rng,

			vsync => vsync,
			ixTExp => ixTExp,

			clk_byte_HS => clk_byte_HS,

			mipirx_RESET_N => mipirx_RESET_N,
			mipirx_RST0_N => mipirx_RST0_N,
			mipirx_ERR_CONTROL_LAN0 => mipirx_ERR_CONTROL_LAN0,
			mipirx_ERR_CONTROL_LAN1 => mipirx_ERR_CONTROL_LAN1,
			mipirx_ERR_CONTROL_LAN2 => mipirx_ERR_CONTROL_LAN2,
			mipirx_ERR_CONTROL_LAN3 => mipirx_ERR_CONTROL_LAN3,
			mipirx_ERR_ESC_LAN0 => mipirx_ERR_ESC_LAN0,
			mipirx_ERR_ESC_LAN1 => mipirx_ERR_ESC_LAN1,
			mipirx_ERR_ESC_LAN2 => mipirx_ERR_ESC_LAN2,
			mipirx_ERR_ESC_LAN3 => mipirx_ERR_ESC_LAN3,
			mipirx_ERR_SOT_SYNC_HS_LAN0 => mipirx_ERR_SOT_SYNC_HS_LAN0,
			mipirx_ERR_SOT_SYNC_HS_LAN1 => mipirx_ERR_SOT_SYNC_HS_LAN1,
			mipirx_ERR_SOT_SYNC_HS_LAN2 => mipirx_ERR_SOT_SYNC_HS_LAN2,
			mipirx_ERR_SOT_SYNC_HS_LAN3 => mipirx_ERR_SOT_SYNC_HS_LAN3,
			mipirx_ESC_CLK_LAN0 => mipirx_ESC_CLK_LAN0,
			mipirx_ESC_CLK_LAN1 => mipirx_ESC_CLK_LAN1,
			mipirx_ESC_CLK_LAN2 => mipirx_ESC_CLK_LAN2,
			mipirx_ESC_CLK_LAN3 => mipirx_ESC_CLK_LAN3,
			mipirx_RX_DATA_HS_LAN0 => mipirx_RX_DATA_HS_LAN0,
			mipirx_RX_DATA_HS_LAN1 => mipirx_RX_DATA_HS_LAN1,
			mipirx_RX_DATA_HS_LAN2 => mipirx_RX_DATA_HS_LAN2,
			mipirx_RX_DATA_HS_LAN3 => mipirx_RX_DATA_HS_LAN3,
			mipirx_RX_SKEW_CAL_HS_LAN0 => mipirx_RX_SKEW_CAL_HS_LAN0,
			mipirx_RX_SKEW_CAL_HS_LAN1 => mipirx_RX_SKEW_CAL_HS_LAN1,
			mipirx_RX_SKEW_CAL_HS_LAN2 => mipirx_RX_SKEW_CAL_HS_LAN2,
			mipirx_RX_SKEW_CAL_HS_LAN3 => mipirx_RX_SKEW_CAL_HS_LAN3,
			mipirx_RX_SYNC_HS_LAN0 => mipirx_RX_SYNC_HS_LAN0,
			mipirx_RX_SYNC_HS_LAN1 => mipirx_RX_SYNC_HS_LAN1,
			mipirx_RX_SYNC_HS_LAN2 => mipirx_RX_SYNC_HS_LAN2,
			mipirx_RX_SYNC_HS_LAN3 => mipirx_RX_SYNC_HS_LAN3,
			mipirx_RX_ULPS_ACTIVE_CLK_NOT => mipirx_RX_ULPS_ACTIVE_CLK_NOT,
			mipirx_RX_ULPS_ACTIVE_NOT_LAN0 => mipirx_RX_ULPS_ACTIVE_NOT_LAN0,
			mipirx_RX_ULPS_ACTIVE_NOT_LAN1 => mipirx_RX_ULPS_ACTIVE_NOT_LAN1,
			mipirx_RX_ULPS_ACTIVE_NOT_LAN2 => mipirx_RX_ULPS_ACTIVE_NOT_LAN2,
			mipirx_RX_ULPS_ACTIVE_NOT_LAN3 => mipirx_RX_ULPS_ACTIVE_NOT_LAN3,
			mipirx_RX_ULPS_CLK_NOT => mipirx_RX_ULPS_CLK_NOT,
			mipirx_RX_ULPS_ESC_LAN0 => mipirx_RX_ULPS_ESC_LAN0,
			mipirx_RX_ULPS_ESC_LAN1 => mipirx_RX_ULPS_ESC_LAN1,
			mipirx_RX_ULPS_ESC_LAN2 => mipirx_RX_ULPS_ESC_LAN2,
			mipirx_RX_ULPS_ESC_LAN3 => mipirx_RX_ULPS_ESC_LAN3,
			mipirx_RX_VALID_HS_LAN0 => mipirx_RX_VALID_HS_LAN0,
			mipirx_RX_VALID_HS_LAN1 => mipirx_RX_VALID_HS_LAN1,
			mipirx_RX_VALID_HS_LAN2 => mipirx_RX_VALID_HS_LAN2,
			mipirx_RX_VALID_HS_LAN3 => mipirx_RX_VALID_HS_LAN3,
			mipirx_STOPSTATE_LAN0 => mipirx_STOPSTATE_LAN0,
			mipirx_STOPSTATE_LAN1 => mipirx_STOPSTATE_LAN1,
			mipirx_STOPSTATE_LAN2 => mipirx_STOPSTATE_LAN2,
			mipirx_STOPSTATE_LAN3 => mipirx_STOPSTATE_LAN3,

			scl_in => scl_in,
			scl_out => scl_out,
			scl_tri => scl_tri,

			sda_in => sda_in,
			sda_out => sda_out,
			sda_tri => sda_tri,

			RxDataHS0 => mipirx_RX_DATA_HS_LAN0,
			RxDataHS1 => mipirx_RX_DATA_HS_LAN1,
			RxDataHS2 => mipirx_RX_DATA_HS_LAN2,
			RxDataHS3 => mipirx_RX_DATA_HS_LAN3,

			datatype_dbg => camifDatatype_dbg,
			mipiAXIS_dbg => open,
			video_out_dbg => open,

			stateConfig_dbg => camifStateConfig_dbg
		);

	myCorner : Corner_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			vsync => vsync,
			NRow => NRow,
			NCol => NCol,

			grayFromVideoinAXIS_tready => grayVideoinToManyAXIS_tready,
			grayFromVideoinAXIS_tvalid => grayVideoinToManyAXIS_tvalid,
			grayFromVideoinAXIS_tdata => grayVideoinToManyAXIS_tdata,
			grayFromVideoinAXIS_tlast => grayVideoinToManyAXIS_tlast,

			reqInvAcquire => reqInvCornerAcquire,
			ackInvAcquire => ackInvCornerAcquire,

			reqInvConfig => reqInvCornerConfig,
			ackInvConfig => ackInvCornerConfig,

			configLinNotLog => cornerConfigLinNotLog,
			configThd => cornerConfigThd,
			configRow0 => cornerConfigRow0,
			configRow1 => cornerConfigRow1,
			configCol0 => cornerConfigCol0,
			configCol1 => cornerConfigCol1,

			getInfoTixVState => cornerGetInfoTixVState,
			getInfoTkst => cornerGetInfoTkst,
			getInfoScoreMin => cornerGetInfoScoreMin,
			getInfoScoreMax => cornerGetInfoScoreMax,

			reqInvSet => reqInvCornerSet,
			ackInvSet => ackInvCornerSet,

			setRng => cornerSetRng,

			reqInvUnlock => reqInvCornerUnlock,
			ackInvUnlock => ackInvCornerUnlock,

			tkclksrcGetTkstTkst => tkclksrcGetTkstTkst,

			reqCoobufToHostif => reqCoobufCornerToHostif,
			ackCoobufToHostif => ackCoobufCornerToHostif,
			dneCoobufToHostif => dneCoobufCornerToHostif,
			avllenCoobufToHostif => avllenCoobufCornerToHostif,

			coobufToHostifAXIS_tready => coobufCornerToHostifAXIS_tready,
			coobufToHostifAXIS_tvalid => coobufCornerToHostifAXIS_tvalid,
			coobufToHostifAXIS_tdata => coobufCornerToHostifAXIS_tdata,
			coobufToHostifAXIS_tlast => coobufCornerToHostifAXIS_tlast
		);

	myCputrack : Cputrack_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			trigA => trigA,
			trigB => trigB,
			trigC => trigC,
			trigD => trigD,

			getInfoTixVState => cputrackGetInfoTixVState,
			getInfoTCapt => cputrackGetInfoTCapt,
			getInfoPtr0Seqbuf => cputrackGetInfoPtr0Seqbuf,

			reqInvSelect => reqInvCputrackSelect,
			ackInvSelect => ackInvCputrackSelect,

			selectTixVCapture => cputrackSelectTixVCapture,
			selectStaTixVTrigger => cputrackSelectStaTixVTrigger,
			selectStaFallingNotRising => cputrackSelectStaFallingNotRising,
			selectStoTixVTrigger => cputrackSelectStoTixVTrigger,
			selectStoFallingNotRising => cputrackSelectStoFallingNotRising,

			reqInvSet => reqInvCputrackSet,
			ackInvSet => ackInvCputrackSet,

			setRng => cputrackSetRng,
			setTCaptMax => cputrackSetTCaptMax,

			reqSeqbufToHostif => reqSeqbufCputrackToHostif,
			ackSeqbufToHostif => ackSeqbufCputrackToHostif,
			dneSeqbufToHostif => dneSeqbufCputrackToHostif,
			avllenSeqbufToHostif => avllenSeqbufCputrackToHostif,

			seqbufToHostifAXIS_tready => seqbufCputrackToHostifAXIS_tready,
			seqbufToHostifAXIS_tvalid => seqbufCputrackToHostifAXIS_tvalid,
			seqbufToHostifAXIS_tdata => seqbufCputrackToHostifAXIS_tdata,
			seqbufToHostifAXIS_tlast => seqbufCputrackToHostifAXIS_tlast,

			hostifStateOp => hostifStateOp_dbg
		);

	myDdrif : Ddrif_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			resetMemclk => resetMemclk,
			memclk => memclk,

			tkclk => tkclk,

			getStatsNRdA => ddrifGetStatsNRdA,
			getStatsNRdB => ddrifGetStatsNRdB,
			getStatsNWrA => ddrifGetStatsNWrA,
			getStatsNWrB => ddrifGetStatsNWrB,

			reqRdA => reqHdrengToDdrifRd,
			ackRdA => ackHdrengToDdrifRd,

			rdAAXI_araddr => hdrmemAXI_araddr,
			rdAAXI_arready => hdrmemAXI_arready,
			rdAAXI_arvalid => hdrmemAXI_arvalid,
			rdAAXI_rdata => hdrmemAXI_rdata,
			rdAAXI_rlast => hdrmemAXI_rlast,
			rdAAXI_rready => hdrmemAXI_rready,
			rdAAXI_rresp => hdrmemAXI_rresp,
			rdAAXI_rvalid => hdrmemAXI_rvalid,

			reqRdB => reqRenderToDdrifRd,
			ackRdB => ackRenderToDdrifRd,

			rdBAXI_araddr => rndmemAXI_araddr,
			rdBAXI_arready => rndmemAXI_arready,
			rdBAXI_arvalid => rndmemAXI_arvalid,
			rdBAXI_rdata => rndmemAXI_rdata,
			rdBAXI_rlast => rndmemAXI_rlast,
			rdBAXI_rready => rndmemAXI_rready,
			rdBAXI_rresp => rndmemAXI_rresp,
			rdBAXI_rvalid => rndmemAXI_rvalid,

			reqWrA => reqHdrengToDdrifWr,
			ackWrA => ackHdrengToDdrifWr,

			wrAAXI_awaddr => hdrmemAXI_awaddr,
			wrAAXI_awready => hdrmemAXI_awready,
			wrAAXI_awvalid => hdrmemAXI_awvalid,
			wrAAXI_wdata => hdrmemAXI_wdata,
			wrAAXI_wlast => hdrmemAXI_wlast,
			wrAAXI_wready => hdrmemAXI_wready,
			wrAAXI_wvalid => hdrmemAXI_wvalid,

			reqWrB => reqRenderToDdrifWr,
			ackWrB => ackRenderToDdrifWr,

			wrBAXI_awaddr => rndmemAXI_awaddr,
			wrBAXI_awready => rndmemAXI_awready,
			wrBAXI_awvalid => rndmemAXI_awvalid,
			wrBAXI_wdata => rndmemAXI_wdata,
			wrBAXI_wlast => rndmemAXI_wlast,
			wrBAXI_wready => rndmemAXI_wready,
			wrBAXI_wvalid => rndmemAXI_wvalid,

			ddrAXI_arid => ddrAXI_arid,
			ddrAXI_araddr => ddrAXI_araddr,
			ddrAXI_arburst => ddrAXI_arburst,
			ddrAXI_arcache => ddrAXI_arcache,
			ddrAXI_arlen => ddrAXI_arlen,
			ddrAXI_arlock => ddrAXI_arlock,
			ddrAXI_arprot => ddrAXI_arprot,
			ddrAXI_arqos => ddrAXI_arqos,
			ddrAXI_arready => ddrAXI_arready,
			ddrAXI_arregion => ddrAXI_arregion,
			ddrAXI_arsize => ddrAXI_arsize,
			ddrAXI_arvalid => ddrAXI_arvalid,

			ddrAXI_rid => ddrAXI_rid,
			ddrAXI_rdata => ddrAXI_rdata,
			ddrAXI_rlast => ddrAXI_rlast,
			ddrAXI_rready => ddrAXI_rready_sig,
			ddrAXI_rresp => ddrAXI_rresp,
			ddrAXI_rvalid => ddrAXI_rvalid,

			ddrAXI_awid => ddrAXI_awid,
			ddrAXI_awaddr => ddrAXI_awaddr,
			ddrAXI_awburst => ddrAXI_awburst,
			ddrAXI_awcache => ddrAXI_awcache,
			ddrAXI_awlen => ddrAXI_awlen,
			ddrAXI_awlock => ddrAXI_awlock,
			ddrAXI_awprot => ddrAXI_awprot,
			ddrAXI_awqos => ddrAXI_awqos,
			ddrAXI_awready => ddrAXI_awready,
			ddrAXI_awregion => ddrAXI_awregion,
			ddrAXI_awsize => ddrAXI_awsize,
			ddrAXI_awvalid => ddrAXI_awvalid,

			ddrAXI_wdata => ddrAXI_wdata,
			ddrAXI_wlast => ddrAXI_wlast,
			ddrAXI_wready => ddrAXI_wready,
			ddrAXI_wstrb => ddrAXI_wstrb,
			ddrAXI_wvalid => ddrAXI_wvalid_sig,

			ddrAXI_bid => ddrAXI_bid,
			ddrAXI_bready => ddrAXI_bready,
			ddrAXI_bresp => ddrAXI_bresp,
			ddrAXI_bvalid => ddrAXI_bvalid
		);

	myDecim : Decim_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			vsync => vsync,
			ixTExp => ixTExp,

			NRow => NRow,
			NCol => NCol,

			grayFromVideoinAXIS_tready => grayVideoinToManyAXIS_tready,
			grayFromVideoinAXIS_tvalid => grayVideoinToManyAXIS_tvalid,
			grayFromVideoinAXIS_tdata => grayVideoinToManyAXIS_tdata,
			grayFromVideoinAXIS_tlast => grayVideoinToManyAXIS_tlast,

			rgbFromVideoinAXIS_tready => rgbVideoinToManyAXIS_tready,
			rgbFromVideoinAXIS_tvalid => rgbVideoinToManyAXIS_tvalid,
			rgbFromVideoinAXIS_tdata => rgbVideoinToManyAXIS_tdata,
			rgbFromVideoinAXIS_tlast => rgbVideoinToManyAXIS_tlast,

			reqInvAcquire => reqInvDecimAcquire,
			ackInvAcquire => ackInvDecimAcquire,

			acquireIxTExp => decimAcquireIxTExp,

			reqInvConfig => reqInvDecimConfig,
			ackInvConfig => ackInvDecimConfig,

			configRgbNotGray => decimConfigRgbNotGray,
			configEdge => decimConfigEdge,
			configEdge2 => decimConfigEdge2,
			configNDecim => decimConfigNDecim,

			getInfoTixVState => decimGetInfoTixVState,
			getInfoTkst => decimGetInfoTkst,

			reqInvSet => reqInvDecimSet,
			ackInvSet => ackInvDecimSet,

			setRng => decimSetRng,

			reqInvUnlock => reqInvDecimUnlock,
			ackInvUnlock => ackInvDecimUnlock,

			tkclksrcGetTkstTkst => tkclksrcGetTkstTkst,

			reqPvwbufToHostif => reqPvwbufDecimToHostif,
			ackPvwbufToHostif => ackPvwbufDecimToHostif,
			dnePvwbufToHostif => dnePvwbufDecimToHostif,
			avllenPvwbufToHostif => avllenPvwbufDecimToHostif,

			pvwbufToHostifAXIS_tready => pvwbufDecimToHostifAXIS_tready,
			pvwbufToHostifAXIS_tvalid => pvwbufDecimToHostifAXIS_tvalid,
			pvwbufToHostifAXIS_tdata => pvwbufDecimToHostifAXIS_tdata,
			pvwbufToHostifAXIS_tlast => pvwbufDecimToHostifAXIS_tlast,

			stateStore_dbg => decimStateStore_dbg,
			stateStream_dbg => decimStateStream_dbg
		);

	myDirector : Director_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			NRowRaw => NRowRaw,
			NColRaw => NColRaw,

			rng => rng,

			reqInvConfig => reqInvDirectorConfig,
			ackInvConfig => ackInvDirectorConfig,

			configNRowRaw => directorConfigNRowRaw,
			configNColRaw => directorConfigNColRaw,

			reqInvSet => reqInvDirectorSet,
			ackInvSet => ackInvDirectorSet,

			setRng => directorSetRng
		);

	myFreqprobeDbg0 : Freqprobe_v1_0_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			fMclk => fMclk
		)
		port map (
			reset => reset,
			mclk => mclk,
			bcdNotHex => '1',
			capt => dbg0,
			freq => freqDbg0
		);

	myFreqprobeDbg1 : Freqprobe_v1_0_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			fMclk => fMclk
		)
		port map (
			reset => reset,
			mclk => mclk,
			bcdNotHex => '1',
			capt => dbg1,
			freq => freqDbg1
		);

	myHdreng : Hdreng_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			resetMemclk => resetMemclk,
			memclk => memclk,

			hdrmemAXI_awaddr => hdrmemAXI_awaddr,
			hdrmemAXI_awready => hdrmemAXI_awready,
			hdrmemAXI_awvalid => hdrmemAXI_awvalid,
			hdrmemAXI_bready => hdrmemAXI_bready,
			hdrmemAXI_bresp => hdrmemAXI_bresp,
			hdrmemAXI_bvalid => hdrmemAXI_bvalid,
			hdrmemAXI_wdata => hdrmemAXI_wdata,
			hdrmemAXI_wlast => hdrmemAXI_wlast,
			hdrmemAXI_wready => hdrmemAXI_wready,
			hdrmemAXI_wvalid => hdrmemAXI_wvalid,

			reqToDdrifWr => reqHdrengToDdrifWr,
			ackToDdrifWr => ackHdrengToDdrifWr,

			hdrmemAXI_araddr => hdrmemAXI_araddr,
			hdrmemAXI_arready => hdrmemAXI_arready,
			hdrmemAXI_arvalid => hdrmemAXI_arvalid,
			hdrmemAXI_rdata => hdrmemAXI_rdata,
			hdrmemAXI_rlast => hdrmemAXI_rlast,
			hdrmemAXI_rready => hdrmemAXI_rready,
			hdrmemAXI_rresp => hdrmemAXI_rresp,
			hdrmemAXI_rvalid => hdrmemAXI_rvalid,

			reqToDdrifRd => reqHdrengToDdrifRd,
			ackToDdrifRd => ackHdrengToDdrifRd,

			vsync => vsync,
			ixTExp => ixTExp,

			NRow => NRow,
			NCol => NCol,

			rgbFromVideoinAXIS_tready => rgbVideoinToManyAXIS_tready,
			rgbFromVideoinAXIS_tvalid => rgbVideoinToManyAXIS_tvalid,
			rgbFromVideoinAXIS_tdata => rgbVideoinToManyAXIS_tdata,
			rgbFromVideoinAXIS_tlast => rgbVideoinToManyAXIS_tlast,

			reqInvAssign => reqInvHdrengAssign,
			ackInvAssign => ackInvHdrengAssign,

			assignIxMem => hdrengAssignIxMem,

			getInfoTixVState => hdrengGetInfoTixVState,
			getInfoTkst => hdrengGetInfoTkst,
			getInfoIxMem => hdrengGetInfoIxMem,
			getInfoIxMemAcq => hdrengGetInfoIxMemAcq,

			reqInvSet => reqInvHdrengSet,
			ackInvSet => ackInvHdrengSet,

			setRng => hdrengSetRng,

			tkclksrcGetTkstTkst => tkclksrcGetTkstTkst
		);

	myHostif : Hostif_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			fMclk => fMclk
		)
		port map (
			reset => reset,
			mclk => mclk,
			tkclk => tkclk,
			commok => commok,
			reqReset => reqResetFromHostif,

			identGetUnt => identGetUnt,
			identGetVer => identGetVer,
			identGetHash => identGetHash,
			identGetWho => identGetWho,

			identGetCfgFMclk => identGetCfgFMclk,
			identGetCfgFMemclk => identGetCfgFMemclk,

			reqInvCamifConfig => reqInvCamifConfig,
			ackInvCamifConfig => ackInvCamifConfig,

			camifConfigHdrNotFix => camifConfigHdrNotFix,
			camifConfigSynthNotLive => camifConfigSynthNotLive,

			reqInvCamifConfigSynth => reqInvCamifConfigSynth,
			ackInvCamifConfigSynth => ackInvCamifConfigSynth,

			camifConfigSynthTixVSynthmode => camifConfigSynthTixVSynthmode,
			camifConfigSynthTFramepad => camifConfigSynthTFramepad,
			camifConfigSynthTLinepad => camifConfigSynthTLinepad,

			reqInvCamifSetReg => reqInvCamifSetReg,
			ackInvCamifSetReg => ackInvCamifSetReg,

			camifSetRegAddr => camifSetRegAddr,
			camifSetRegVal => camifSetRegVal,

			reqInvCamifGetReg => reqInvCamifGetReg,
			ackInvCamifGetReg => ackInvCamifGetReg,

			camifGetRegAddr => camifGetRegAddr,
			camifGetRegVal => camifGetRegVal,

			reqInvCamifModReg => reqInvCamifModReg,
			ackInvCamifModReg => ackInvCamifModReg,

			camifModRegAddr => camifModRegAddr,
			camifModRegMask => camifModRegMask,
			camifModRegVal => camifModRegVal,

			reqInvCamifSetCorereg => reqInvCamifSetCorereg,
			ackInvCamifSetCorereg => ackInvCamifSetCorereg,

			camifSetCoreregAddr => camifSetCoreregAddr,
			camifSetCoreregVal => camifSetCoreregVal,

			reqInvCamifGetCorereg => reqInvCamifGetCorereg,
			ackInvCamifGetCorereg => ackInvCamifGetCorereg,

			camifGetCoreregAddr => camifGetCoreregAddr,
			camifGetCoreregVal => camifGetCoreregVal,

			reqInvCornerAcquire => reqInvCornerAcquire,
			ackInvCornerAcquire => ackInvCornerAcquire,

			reqInvCornerConfig => reqInvCornerConfig,
			ackInvCornerConfig => ackInvCornerConfig,

			cornerConfigLinNotLog => cornerConfigLinNotLog,
			cornerConfigThd => cornerConfigThd,
			cornerConfigRow0 => cornerConfigRow0,
			cornerConfigRow1 => cornerConfigRow1,
			cornerConfigCol0 => cornerConfigCol0,
			cornerConfigCol1 => cornerConfigCol1,

			cornerGetInfoTixVState => cornerGetInfoTixVState,
			cornerGetInfoTkst => cornerGetInfoTkst,
			cornerGetInfoScoreMin => cornerGetInfoScoreMin,
			cornerGetInfoScoreMax => cornerGetInfoScoreMax,

			reqInvCornerSet => reqInvCornerSet,
			ackInvCornerSet => ackInvCornerSet,

			cornerSetRng => cornerSetRng,

			reqInvCornerUnlock => reqInvCornerUnlock,
			ackInvCornerUnlock => ackInvCornerUnlock,

			ddrifGetStatsNRdA => ddrifGetStatsNRdA,
			ddrifGetStatsNRdB => ddrifGetStatsNRdB,
			ddrifGetStatsNWrA => ddrifGetStatsNWrA,
			ddrifGetStatsNWrB => ddrifGetStatsNWrB,

			reqInvDecimAcquire => reqInvDecimAcquire,
			ackInvDecimAcquire => ackInvDecimAcquire,

			decimAcquireIxTExp => decimAcquireIxTExp,

			reqInvDecimConfig => reqInvDecimConfig,
			ackInvDecimConfig => ackInvDecimConfig,

			decimConfigRgbNotGray => decimConfigRgbNotGray,
			decimConfigEdge => decimConfigEdge,
			decimConfigEdge2 => decimConfigEdge2,
			decimConfigNDecim => decimConfigNDecim,

			decimGetInfoTixVState => decimGetInfoTixVState,
			decimGetInfoTkst => decimGetInfoTkst,

			reqInvDecimSet => reqInvDecimSet,
			ackInvDecimSet => ackInvDecimSet,

			decimSetRng => decimSetRng,

			reqInvDecimUnlock => reqInvDecimUnlock,
			ackInvDecimUnlock => ackInvDecimUnlock,

			reqInvDirectorConfig => reqInvDirectorConfig,
			ackInvDirectorConfig => ackInvDirectorConfig,

			directorConfigNRowRaw => directorConfigNRowRaw,
			directorConfigNColRaw => directorConfigNColRaw,

			reqInvDirectorSet => reqInvDirectorSet,
			ackInvDirectorSet => ackInvDirectorSet,

			directorSetRng => directorSetRng,

			reqInvHdrengAssign => reqInvHdrengAssign,
			ackInvHdrengAssign => ackInvHdrengAssign,

			hdrengAssignIxMem => hdrengAssignIxMem,

			hdrengGetInfoTixVState => hdrengGetInfoTixVState,
			hdrengGetInfoTkst => hdrengGetInfoTkst,
			hdrengGetInfoIxMem => hdrengGetInfoIxMem,
			hdrengGetInfoIxMemAcq => hdrengGetInfoIxMemAcq,

			reqInvHdrengSet => reqInvHdrengSet,
			ackInvHdrengSet => ackInvHdrengSet,

			hdrengSetRng => hdrengSetRng,

			reqInvLaserSet => reqInvLaserSet,
			ackInvLaserSet => ackInvLaserSet,

			laserSetL => laserSetL,
			laserSetR => laserSetR,

			reqInvRotaryConfig => reqInvRotaryConfig,
			ackInvRotaryConfig => ackInvRotaryConfig,

			rotaryConfigTixVStepmode => rotaryConfigTixVStepmode,
			rotaryConfigTStep => rotaryConfigTStep,

			rotaryGetInfoTixVState => rotaryGetInfoTixVState,
			rotaryGetInfoAngle => rotaryGetInfoAngle,

			reqInvRotaryMoveto => reqInvRotaryMoveto,
			ackInvRotaryMoveto => ackInvRotaryMoveto,

			rotaryMovetoAngle => rotaryMovetoAngle,

			reqInvRotarySet => reqInvRotarySet,
			ackInvRotarySet => ackInvRotarySet,

			rotarySetRng => rotarySetRng,
			rotarySetCcwNotCw => rotarySetCcwNotCw,

			reqInvRotaryZero => reqInvRotaryZero,
			ackInvRotaryZero => ackInvRotaryZero,

			reqInvStepmuxSet => reqInvStepmuxSet,
			ackInvStepmuxSet => ackInvStepmuxSet,

			stepmuxSetLinNotRot => stepmuxSetLinNotRot,

			tkclksrcGetTkstTkst => tkclksrcGetTkstTkst,

			reqInvTkclksrcSetTkst => reqInvTkclksrcSetTkst,
			ackInvTkclksrcSetTkst => ackInvTkclksrcSetTkst,

			tkclksrcSetTkstTkst => tkclksrcSetTkstTkst,

			reqInvTraceAcquire => reqInvTraceAcquire,
			ackInvTraceAcquire => ackInvTraceAcquire,

			reqInvTraceConfig => reqInvTraceConfig,
			ackInvTraceConfig => ackInvTraceConfig,

			traceConfigTixVOrient => traceConfigTixVOrient,
			traceConfigRow0 => traceConfigRow0,
			traceConfigCol0 => traceConfigCol0,

			traceGetInfoTixVState => traceGetInfoTixVState,
			traceGetInfoTkst => traceGetInfoTkst,

			reqInvTraceUnlock => reqInvTraceUnlock,
			ackInvTraceUnlock => ackInvTraceUnlock,

			cputrackGetInfoTixVState => cputrackGetInfoTixVState,
			cputrackGetInfoTCapt => cputrackGetInfoTCapt,
			cputrackGetInfoPtr0Seqbuf => cputrackGetInfoPtr0Seqbuf,

			reqInvCputrackSelect => reqInvCputrackSelect,
			ackInvCputrackSelect => ackInvCputrackSelect,

			cputrackSelectTixVCapture => cputrackSelectTixVCapture,
			cputrackSelectStaTixVTrigger => cputrackSelectStaTixVTrigger,
			cputrackSelectStaFallingNotRising => cputrackSelectStaFallingNotRising,
			cputrackSelectStoTixVTrigger => cputrackSelectStoTixVTrigger,
			cputrackSelectStoFallingNotRising => cputrackSelectStoFallingNotRising,

			reqInvCputrackSet => reqInvCputrackSet,
			ackInvCputrackSet => ackInvCputrackSet,

			cputrackSetRng => cputrackSetRng,
			cputrackSetTCaptMax => cputrackSetTCaptMax,

			reqInvHshktrackClearMask => reqInvHshktrackClearMask,
			ackInvHshktrackClearMask => ackInvHshktrackClearMask,

			hshktrackGetInfoTixVState => hshktrackGetInfoTixVState,
			hshktrackGetInfoTCapt => hshktrackGetInfoTCapt,
			hshktrackGetInfoPtr0Seqbuf => hshktrackGetInfoPtr0Seqbuf,

			reqInvHshktrackSelect => reqInvHshktrackSelect,
			ackInvHshktrackSelect => ackInvHshktrackSelect,

			hshktrackSelectStaTixVTrigger => hshktrackSelectStaTixVTrigger,
			hshktrackSelectStaFallingNotRising => hshktrackSelectStaFallingNotRising,
			hshktrackSelectStoTixVTrigger => hshktrackSelectStoTixVTrigger,
			hshktrackSelectStoFallingNotRising => hshktrackSelectStoFallingNotRising,

			reqInvHshktrackSet => reqInvHshktrackSet,
			ackInvHshktrackSet => ackInvHshktrackSet,

			hshktrackSetRng => hshktrackSetRng,
			hshktrackSetTCaptMax => hshktrackSetTCaptMax,

			reqInvHshktrackSetMask => reqInvHshktrackSetMask,
			ackInvHshktrackSetMask => ackInvHshktrackSetMask,

			hshktrackSetMaskTixVCapture => hshktrackSetMaskTixVCapture,

			reqInvMemtrackClearMask => reqInvMemtrackClearMask,
			ackInvMemtrackClearMask => ackInvMemtrackClearMask,

			memtrackGetInfoTixVState => memtrackGetInfoTixVState,
			memtrackGetInfoTCapt => memtrackGetInfoTCapt,
			memtrackGetInfoPtr0Seqbuf => memtrackGetInfoPtr0Seqbuf,

			reqInvMemtrackSelect => reqInvMemtrackSelect,
			ackInvMemtrackSelect => ackInvMemtrackSelect,

			memtrackSelectStaTixVTrigger => memtrackSelectStaTixVTrigger,
			memtrackSelectStaFallingNotRising => memtrackSelectStaFallingNotRising,
			memtrackSelectStoTixVTrigger => memtrackSelectStoTixVTrigger,
			memtrackSelectStoFallingNotRising => memtrackSelectStoFallingNotRising,

			reqInvMemtrackSet => reqInvMemtrackSet,
			ackInvMemtrackSet => ackInvMemtrackSet,

			memtrackSetRng => memtrackSetRng,
			memtrackSetTCaptMax => memtrackSetTCaptMax,

			reqInvMemtrackSetMask => reqInvMemtrackSetMask,
			ackInvMemtrackSetMask => ackInvMemtrackSetMask,

			memtrackSetMaskTixVCapture => memtrackSetMaskTixVCapture,

			vidtrackGetInfoTixVState => vidtrackGetInfoTixVState,
			vidtrackGetInfoTCapt => vidtrackGetInfoTCapt,
			vidtrackGetInfoPtr0Seqbuf => vidtrackGetInfoPtr0Seqbuf,

			reqInvVidtrackSelect => reqInvVidtrackSelect,
			ackInvVidtrackSelect => ackInvVidtrackSelect,

			vidtrackSelectTixVCapture => vidtrackSelectTixVCapture,
			vidtrackSelectStaTixVTrigger => vidtrackSelectStaTixVTrigger,
			vidtrackSelectStaFallingNotRising => vidtrackSelectStaFallingNotRising,
			vidtrackSelectStoTixVTrigger => vidtrackSelectStoTixVTrigger,
			vidtrackSelectStoFallingNotRising => vidtrackSelectStoFallingNotRising,

			reqInvVidtrackSet => reqInvVidtrackSet,
			ackInvVidtrackSet => ackInvVidtrackSet,

			vidtrackSetRng => vidtrackSetRng,
			vidtrackSetTCaptMax => vidtrackSetTCaptMax,

			reqPvwbufFromDecim => reqPvwbufDecimToHostif,
			ackPvwbufFromDecim => ackPvwbufDecimToHostif,
			dnePvwbufFromDecim => dnePvwbufDecimToHostif,
			avllenPvwbufFromDecim => avllenPvwbufDecimToHostif,

			pvwbufFromDecimAXIS_tready => pvwbufDecimToHostifAXIS_tready,
			pvwbufFromDecimAXIS_tvalid => pvwbufDecimToHostifAXIS_tvalid,
			pvwbufFromDecimAXIS_tdata => pvwbufDecimToHostifAXIS_tdata,
			pvwbufFromDecimAXIS_tlast => pvwbufDecimToHostifAXIS_tlast,

			reqCoobufFromCorner => reqCoobufCornerToHostif,
			ackCoobufFromCorner => ackCoobufCornerToHostif,
			dneCoobufFromCorner => dneCoobufCornerToHostif,
			avllenCoobufFromCorner => avllenCoobufCornerToHostif,

			reqFlgbufFromTrace => reqFlgbufTraceToHostif,
			ackFlgbufFromTrace => ackFlgbufTraceToHostif,

			coobufFromCornerAXIS_tready => coobufCornerToHostifAXIS_tready,
			coobufFromCornerAXIS_tvalid => coobufCornerToHostifAXIS_tvalid,
			coobufFromCornerAXIS_tdata => coobufCornerToHostifAXIS_tdata,
			coobufFromCornerAXIS_tlast => coobufCornerToHostifAXIS_tlast,

			dneFlgbufFromTrace => dneFlgbufTraceToHostif,
			avllenFlgbufFromTrace => avllenFlgbufTraceToHostif,

			flgbufFromTraceAXIS_tready => flgbufTraceToHostifAXIS_tready,
			flgbufFromTraceAXIS_tvalid => flgbufTraceToHostifAXIS_tvalid,
			flgbufFromTraceAXIS_tdata => flgbufTraceToHostifAXIS_tdata,
			flgbufFromTraceAXIS_tlast => flgbufTraceToHostifAXIS_tlast,

			reqSeqbufFromCputrack => reqSeqbufCputrackToHostif,
			ackSeqbufFromCputrack => ackSeqbufCputrackToHostif,
			dneSeqbufFromCputrack => dneSeqbufCputrackToHostif,
			avllenSeqbufFromCputrack => avllenSeqbufCputrackToHostif,

			seqbufFromCputrackAXIS_tready => seqbufCputrackToHostifAXIS_tready,
			seqbufFromCputrackAXIS_tvalid => seqbufCputrackToHostifAXIS_tvalid,
			seqbufFromCputrackAXIS_tdata => seqbufCputrackToHostifAXIS_tdata,
			seqbufFromCputrackAXIS_tlast => seqbufCputrackToHostifAXIS_tlast,

			reqSeqbufFromHshktrack => reqSeqbufHshktrackToHostif,
			ackSeqbufFromHshktrack => ackSeqbufHshktrackToHostif,
			dneSeqbufFromHshktrack => dneSeqbufHshktrackToHostif,
			avllenSeqbufFromHshktrack => avllenSeqbufHshktrackToHostif,

			reqSeqbufFromMemtrack => reqSeqbufMemtrackToHostif,
			ackSeqbufFromMemtrack => ackSeqbufMemtrackToHostif,
			dneSeqbufFromMemtrack => dneSeqbufMemtrackToHostif,
			avllenSeqbufFromMemtrack => avllenSeqbufMemtrackToHostif,

			seqbufFromHshktrackAXIS_tready => seqbufHshktrackToHostifAXIS_tready,
			seqbufFromHshktrackAXIS_tvalid => seqbufHshktrackToHostifAXIS_tvalid,
			seqbufFromHshktrackAXIS_tdata => seqbufHshktrackToHostifAXIS_tdata,
			seqbufFromHshktrackAXIS_tlast => seqbufHshktrackToHostifAXIS_tlast,

			seqbufFromMemtrackAXIS_tready => seqbufMemtrackToHostifAXIS_tready,

			reqSeqbufFromVidtrack => reqSeqbufVidtrackToHostif,
			ackSeqbufFromVidtrack => ackSeqbufVidtrackToHostif,
			dneSeqbufFromVidtrack => dneSeqbufVidtrackToHostif,
			avllenSeqbufFromVidtrack => avllenSeqbufVidtrackToHostif,

			seqbufFromMemtrackAXIS_tvalid => seqbufMemtrackToHostifAXIS_tvalid,
			seqbufFromMemtrackAXIS_tdata => seqbufMemtrackToHostifAXIS_tdata,
			seqbufFromMemtrackAXIS_tlast => seqbufMemtrackToHostifAXIS_tlast,

			seqbufFromVidtrackAXIS_tready => seqbufVidtrackToHostifAXIS_tready,
			seqbufFromVidtrackAXIS_tvalid => seqbufVidtrackToHostifAXIS_tvalid,
			seqbufFromVidtrackAXIS_tdata => seqbufVidtrackToHostifAXIS_tdata,
			seqbufFromVidtrackAXIS_tlast => seqbufVidtrackToHostifAXIS_tlast,

			AXIL_araddr => apuAXIL_araddr,
			AXIL_arprot => apuAXIL_arprot,
			AXIL_arready => apuAXIL_arready,
			AXIL_arvalid => apuAXIL_arvalid,
			AXIL_rdata => apuAXIL_rdata,
			AXIL_rready => apuAXIL_rready,
			AXIL_rresp => apuAXIL_rresp,
			AXIL_rvalid => apuAXIL_rvalid,
			AXIL_rlast => apuAXIL_rlast,
			AXIL_awaddr => apuAXIL_awaddr,
			AXIL_awprot => apuAXIL_awprot,
			AXIL_awready => apuAXIL_awready,
			AXIL_awvalid => apuAXIL_awvalid,
			AXIL_wdata => apuAXIL_wdata,
			AXIL_wready => apuAXIL_wready,
			AXIL_wstrb => apuAXIL_wstrb,
			AXIL_wvalid => apuAXIL_wvalid,
			AXIL_bready => apuAXIL_bready,
			AXIL_bresp => apuAXIL_bresp,
			AXIL_bvalid => apuAXIL_bvalid,

			stateOp_dbg => hostifStateOp_dbg
		);

	myHshktrack : Hshktrack_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			trigA => trigA,
			trigB => trigB,
			trigC => trigC,
			trigD => trigD,

			reqInvClearMask => reqInvHshktrackClearMask,
			ackInvClearMask => ackInvHshktrackClearMask,

			getInfoTixVState => hshktrackGetInfoTixVState,
			getInfoTCapt => hshktrackGetInfoTCapt,
			getInfoPtr0Seqbuf => hshktrackGetInfoPtr0Seqbuf,

			reqInvSelect => reqInvHshktrackSelect,
			ackInvSelect => ackInvHshktrackSelect,

			selectStaTixVTrigger => hshktrackSelectStaTixVTrigger,
			selectStaFallingNotRising => hshktrackSelectStaFallingNotRising,
			selectStoTixVTrigger => hshktrackSelectStoTixVTrigger,
			selectStoFallingNotRising => hshktrackSelectStoFallingNotRising,

			reqInvSet => reqInvHshktrackSet,
			ackInvSet => ackInvHshktrackSet,

			setRng => hshktrackSetRng,
			setTCaptMax => hshktrackSetTCaptMax,

			reqInvSetMask => reqInvHshktrackSetMask,
			ackInvSetMask => ackInvHshktrackSetMask,

			setMaskTixVCapture => hshktrackSetMaskTixVCapture,

			reqSeqbufToHostif => reqSeqbufHshktrackToHostif,
			ackSeqbufToHostif => ackSeqbufHshktrackToHostif,
			dneSeqbufToHostif => dneSeqbufHshktrackToHostif,
			avllenSeqbufToHostif => avllenSeqbufHshktrackToHostif,

			seqbufToHostifAXIS_tready => seqbufHshktrackToHostifAXIS_tready,
			seqbufToHostifAXIS_tvalid => seqbufHshktrackToHostifAXIS_tvalid,
			seqbufToHostifAXIS_tdata => seqbufHshktrackToHostifAXIS_tdata,
			seqbufToHostifAXIS_tlast => seqbufHshktrackToHostifAXIS_tlast,

			vsync => vsync,
			cornerGetInfoTixVState => cornerGetInfoTixVState(1 downto 0),
			reqInvRotarySet => reqInvRotarySet,
			rotaryToStepmuxStep => rotaryToStepmuxStep
		);

	myIdent : Ident_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			fMclk => fMclk,
			fMemclk => fMemclk
		)
		port map (
			getUnt => identGetUnt,
			getVer => identGetVer,
			getHash => identGetHash,
			getWho => identGetWho,

			getCfgFMclk => identGetCfgFMclk,
			getCfgFMemclk => identGetCfgFMemclk
		);

	myLaser : Laser_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			fMclk => fMclk
		)
		port map (
			reset => reset,
			mclk => mclk,

			reqInvSet => reqInvLaserSet,
			ackInvSet => ackInvLaserSet,

			setL => laserSetL,
			setR => laserSetR,

			nss => cs,
			sclk => sclk,
			mosi => mosi
		);

	myLinear : Linear_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,
			toStepmuxNslp => linearToStepmuxNslp,
			toStepmuxM0 => linearToStepmuxM0,
			toStepmuxM0z => linearToStepmuxM0z,
			toStepmuxM1 => linearToStepmuxM1,
			toStepmuxDir => linearToStepmuxDir,
			toStepmuxStep => linearToStepmuxStep
		);

	myMemtrack : Memtrack_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			resetMemclk => resetMemclk,
			memclk => memclk,

			vsync => vsync,
			rgbVideoinToManyAXIS_tlast => rgbVideoinToManyAXIS_tlast,

			reqInvClearMask => reqInvMemtrackClearMask,
			ackInvClearMask => ackInvMemtrackClearMask,

			getInfoTixVState => memtrackGetInfoTixVState,
			getInfoTCapt => memtrackGetInfoTCapt,
			getInfoPtr0Seqbuf => memtrackGetInfoPtr0Seqbuf,

			reqInvSelect => reqInvMemtrackSelect,
			ackInvSelect => ackInvMemtrackSelect,

			selectStaTixVTrigger => memtrackSelectStaTixVTrigger,
			selectStaFallingNotRising => memtrackSelectStaFallingNotRising,
			selectStoTixVTrigger => memtrackSelectStoTixVTrigger,
			selectStoFallingNotRising => memtrackSelectStoFallingNotRising,

			reqInvSet => reqInvMemtrackSet,
			ackInvSet => ackInvMemtrackSet,

			setRng => memtrackSetRng,
			setTCaptMax => memtrackSetTCaptMax,

			reqInvSetMask => reqInvMemtrackSetMask,
			ackInvSetMask => ackInvMemtrackSetMask,

			setMaskTixVCapture => memtrackSetMaskTixVCapture,

			reqSeqbufToHostif => reqSeqbufMemtrackToHostif,
			ackSeqbufToHostif => ackSeqbufMemtrackToHostif,
			dneSeqbufToHostif => dneSeqbufMemtrackToHostif,
			avllenSeqbufToHostif => avllenSeqbufMemtrackToHostif,

			seqbufToHostifAXIS_tready => seqbufMemtrackToHostifAXIS_tready,
			seqbufToHostifAXIS_tvalid => seqbufMemtrackToHostifAXIS_tvalid,
			seqbufToHostifAXIS_tdata => seqbufMemtrackToHostifAXIS_tdata,
			seqbufToHostifAXIS_tlast => seqbufMemtrackToHostifAXIS_tlast,

			reqHdrengToDdrifRd => reqHdrengToDdrifRd,
			ackHdrengToDdrifRd => ackHdrengToDdrifRd,
			reqHdrengToDdrifWr => reqHdrengToDdrifWr,
			ackHdrengToDdrifWr => ackHdrengToDdrifWr,
			ddrAXI_rvalid => ddrAXI_rvalid,
			ddrAXI_rready_sig => ddrAXI_rready_sig,
			ddrAXI_wready => ddrAXI_wready,
			ddrAXI_bvalid => ddrAXI_bvalid,
			ddrAXI_wvalid_sig => ddrAXI_wvalid_sig
		);

	myRender : Render_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			resetMemclk => resetMemclk,
			memclk => memclk,

			rndmemAXI_awaddr => rndmemAXI_awaddr,
			rndmemAXI_awready => rndmemAXI_awready,
			rndmemAXI_awvalid => rndmemAXI_awvalid,
			rndmemAXI_wdata => rndmemAXI_wdata,
			rndmemAXI_wlast => rndmemAXI_wlast,
			rndmemAXI_wready => rndmemAXI_wready,
			rndmemAXI_wvalid => rndmemAXI_wvalid,

			reqToDdrifWr => reqRenderToDdrifWr,
			ackToDdrifWr => ackRenderToDdrifWr,

			rndmemAXI_araddr => rndmemAXI_araddr,
			rndmemAXI_arready => rndmemAXI_arready,
			rndmemAXI_arvalid => rndmemAXI_arvalid,
			rndmemAXI_rdata => rndmemAXI_rdata,
			rndmemAXI_rlast => rndmemAXI_rlast,
			rndmemAXI_rready => rndmemAXI_rready,
			rndmemAXI_rresp => rndmemAXI_rresp,
			rndmemAXI_rvalid => rndmemAXI_rvalid,

			reqToDdrifRd => reqRenderToDdrifRd,
			ackToDdrifRd => ackRenderToDdrifRd
		);

	myRgbled0 : Rgbled_v1_0_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			fMclk => 50000
		)
		port map (
			reset => reset,
			mclk => mclk,
			rgb => rgb0,

			r => rgb0_r,
			g => rgb0_g,
			b => rgb0_b
		);

	myRgbled1 : Rgbled_v1_0_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			fMclk => 50000
		)
		port map (
			reset => reset,
			mclk => mclk,
			rgb => rgb1,

			r => rgb1_r,
			g => rgb1_g,
			b => rgb1_b
		);

	myRotary : Rotary_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,
			tkclk => tkclk,

			toStepmuxNslp => rotaryToStepmuxNslp,
			toStepmuxM0 => rotaryToStepmuxM0,
			toStepmuxM0z => rotaryToStepmuxM0z,
			toStepmuxM1 => rotaryToStepmuxM1,
			toStepmuxDir => rotaryToStepmuxDir,
			toStepmuxStep => rotaryToStepmuxStep,

			reqInvConfig => reqInvRotaryConfig,
			ackInvConfig => ackInvRotaryConfig,

			configTixVStepmode => rotaryConfigTixVStepmode,
			configTStep => rotaryConfigTStep,

			getInfoTixVState => rotaryGetInfoTixVState,
			getInfoAngle => rotaryGetInfoAngle,

			reqInvMoveto => reqInvRotaryMoveto,
			ackInvMoveto => ackInvRotaryMoveto,

			movetoAngle => rotaryMovetoAngle,

			reqInvSet => reqInvRotarySet,
			ackInvSet => ackInvRotarySet,

			setRng => rotarySetRng,
			setCcwNotCw => rotarySetCcwNotCw,

			reqInvZero => reqInvRotaryZero,
			ackInvZero => ackInvRotaryZero
		);

	myState : State_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,
			tkclk => tkclk,
			commok => commok,
			rng => rng,
			rgb => rgb0
		);

	myStepmux : Stepmux_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			fromLinearNslp => linearToStepmuxNslp,
			fromLinearM0 => linearToStepmuxM0,
			fromLinearM0z => linearToStepmuxM0z,
			fromLinearM1 => linearToStepmuxM1,
			fromLinearDir => linearToStepmuxDir,
			fromLinearStep => linearToStepmuxStep,

			fromRotaryNslp => rotaryToStepmuxNslp,
			fromRotaryM0 => rotaryToStepmuxM0,
			fromRotaryM0z => rotaryToStepmuxM0z,
			fromRotaryM1 => rotaryToStepmuxM1,
			fromRotaryDir => rotaryToStepmuxDir,
			fromRotaryStep => rotaryToStepmuxStep,

			reqInvSet => reqInvStepmuxSet,
			ackInvSet => ackInvStepmuxSet,

			setLinNotRot => stepmuxSetLinNotRot,

			nslp => nslp,

			m0 => m0,
			m0z => m0z,

			m1 => m1,
			m1z => m1z,

			dir => dir,
			step => step
		);

	myTkclksrc : Tkclksrc_Easy_v1_0_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			fMclk => fMclk
		)
		port map (
			reset => reset,
			mclk => mclk,
			tkclk => tkclk,

			getTkstTkst => tkclksrcGetTkstTkst,

			reqInvSetTkst => reqInvTkclksrcSetTkst,
			ackInvSetTkst => ackInvTkclksrcSetTkst,

			setTkstTkst => tkclksrcSetTkstTkst,

			stateOp_dbg => tkclksrcStateOp_dbg
		);

	myTrace : Trace_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			vsync => vsync,
			ixTExp => ixTExp,

			NRow => NRow,
			NCol => NCol,

			rgbFromVideoinAXIS_tready => rgbVideoinToManyAXIS_tready,
			rgbFromVideoinAXIS_tvalid => rgbVideoinToManyAXIS_tvalid,
			rgbFromVideoinAXIS_tdata => rgbVideoinToManyAXIS_tdata,
			rgbFromVideoinAXIS_tlast => rgbVideoinToManyAXIS_tlast,

			tkclksrcGetTkstTkst => tkclksrcGetTkstTkst,

			reqInvAcquire => reqInvTraceAcquire,
			ackInvAcquire => ackInvTraceAcquire,

			reqInvConfig => reqInvTraceConfig,
			ackInvConfig => ackInvTraceConfig,

			configTixVOrient => traceConfigTixVOrient,
			configRow0 => traceConfigRow0,
			configCol0 => traceConfigCol0,

			getInfoTixVState => traceGetInfoTixVState,
			getInfoTkst => traceGetInfoTkst,

			reqInvUnlock => reqInvTraceUnlock,
			ackInvUnlock => ackInvTraceUnlock,

			reqFlgbufToHostif => reqFlgbufTraceToHostif,
			ackFlgbufToHostif => ackFlgbufTraceToHostif,
			dneFlgbufToHostif => dneFlgbufTraceToHostif,
			avllenFlgbufToHostif => avllenFlgbufTraceToHostif,

			flgbufToHostifAXIS_tready => flgbufTraceToHostifAXIS_tready,
			flgbufToHostifAXIS_tvalid => flgbufTraceToHostifAXIS_tvalid,
			flgbufToHostifAXIS_tdata => flgbufTraceToHostifAXIS_tdata,
			flgbufToHostifAXIS_tlast => flgbufTraceToHostifAXIS_tlast
		);

	myVecrend : Vecrend_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk
		);

	myVideoin : Videoin_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			fromCamifAXIS_tready => camifToVideoinAXIS_tready,
			fromCamifAXIS_tvalid => camifToVideoinAXIS_tvalid,
			fromCamifAXIS_tdata => camifToVideoinAXIS_tdata,
			fromCamifAXIS_tlast => camifToVideoinAXIS_tlast,

			vsync => vsync,
			NCol => NCol,

			grayToManyAXIS_tready => grayVideoinToManyAXIS_tready,
			grayToManyAXIS_tvalid => grayVideoinToManyAXIS_tvalid,
			grayToManyAXIS_tdata => grayVideoinToManyAXIS_tdata,
			grayToManyAXIS_tlast => grayVideoinToManyAXIS_tlast,

			rgbToManyAXIS_tready => rgbVideoinToManyAXIS_tready,
			rgbToManyAXIS_tvalid => rgbVideoinToManyAXIS_tvalid,
			rgbToManyAXIS_tdata => rgbVideoinToManyAXIS_tdata,
			rgbToManyAXIS_tlast => rgbVideoinToManyAXIS_tlast,

			stateIgr_dbg => videoinStateIgr_dbg,
			stateRgbegr_dbg => videoinStateRgbegr_dbg
		);

	myVidtrack : Vidtrack_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			trigA => trigA,
			trigB => trigB,
			trigC => trigC,
			trigD => trigD,

			getInfoTixVState => vidtrackGetInfoTixVState,
			getInfoTCapt => vidtrackGetInfoTCapt,
			getInfoPtr0Seqbuf => vidtrackGetInfoPtr0Seqbuf,

			reqInvSelect => reqInvVidtrackSelect,
			ackInvSelect => ackInvVidtrackSelect,

			selectTixVCapture => vidtrackSelectTixVCapture,
			selectStaTixVTrigger => vidtrackSelectStaTixVTrigger,
			selectStaFallingNotRising => vidtrackSelectStaFallingNotRising,
			selectStoTixVTrigger => vidtrackSelectStoTixVTrigger,
			selectStoFallingNotRising => vidtrackSelectStoFallingNotRising,

			reqInvSet => reqInvVidtrackSet,
			ackInvSet => ackInvVidtrackSet,

			setRng => vidtrackSetRng,
			setTCaptMax => vidtrackSetTCaptMax,

			reqSeqbufToHostif => reqSeqbufVidtrackToHostif,
			ackSeqbufToHostif => ackSeqbufVidtrackToHostif,
			dneSeqbufToHostif => dneSeqbufVidtrackToHostif,
			avllenSeqbufToHostif => avllenSeqbufVidtrackToHostif,

			seqbufToHostifAXIS_tready => seqbufVidtrackToHostifAXIS_tready,
			seqbufToHostifAXIS_tvalid => seqbufVidtrackToHostifAXIS_tvalid,
			seqbufToHostifAXIS_tdata => seqbufVidtrackToHostifAXIS_tdata,
			seqbufToHostifAXIS_tlast => seqbufVidtrackToHostifAXIS_tlast,

			videoinStateIgr => videoinStateIgr_dbg,
			videoinStateRgbegr => videoinStateRgbegr_dbg,
			decimStateStream => decimStateStream_dbg,
			decimStateStore => decimStateStore_dbg
		);

	------------------------------------------------------------------------
	-- implementation: mclk wiring and reset (mclk)
	------------------------------------------------------------------------

	-- IP impl.mclk.wiring --- RBEGIN
	mclk <= aclk;
	-- IP impl.mclk.wiring --- REND

	-- IP impl.mclk.wiring.cust --- LINE

	-- IP impl.mclk.rising --- BEGIN
	process (aresetn, mclk)
		-- IP impl.mclk.vars --- BEGIN
		constant imax: natural := 8;
		variable i: natural range 0 to imax;
		-- IP impl.mclk.vars --- END

	begin
		if aresetn='0' then
			-- IP impl.mclk.asyncrst --- BEGIN
			stateMclk <= stateMclkReset;
			reset <= '1';

			i := 0;
			-- IP impl.mclk.asyncrst --- END
			-- IP impl.mclk.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if stateMclk=stateMclkReset then
				if i=imax then
					reset <= '0';

					stateMclk <= stateMclkRun;

				else
					i := i + 1;

					stateMclk <= stateMclkReset;
				end if;

			elsif stateMclk=stateMclkRun then
				if reqResetFromHostif='1' then
					reset <= '1';

					i := 0;

					stateMclk <= stateMclkReset;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.mclk.rising --- END

	------------------------------------------------------------------------
	-- implementation: memclk wiring and reset (memclk)
	------------------------------------------------------------------------

	-- IP impl.memclk.wiring --- BEGIN
	-- IP impl.memclk.wiring --- END

	-- IP impl.memclk.wiring.cust --- LINE

	-- IP impl.memclk.rising --- BEGIN
	process (aresetn, memclk)
		-- IP impl.memclk.vars --- BEGIN
		constant imax: natural := (16*fMemclk)/fMclk+1;
		variable i: natural range 0 to imax;
		-- IP impl.memclk.vars --- END

	begin
		if aresetn='0' then
			-- IP impl.memclk.asyncrst --- BEGIN
			stateMemclk <= stateMemclkReset;
			resetMemclk <= '1';
			reset_memclk <= '1';
			reset_to_memclkm1 <= '1';
			reset_to_memclkm2 <= '1';

			i := 0;
			-- IP impl.memclk.asyncrst --- END
			-- IP impl.memclk.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if reset_to_memclkm1=reset_to_memclkm2 then
				reset_memclk <= reset_to_memclkm2;
			end if;
			reset_to_memclkm1 <= reset;
			reset_to_memclkm2 <= reset_to_memclkm1;

			if stateMemclk=stateMemclkReset then
				if i=imax then
					if reset_memclk='0' then
						resetMemclk <= '0';

						stateMemclk <= stateMemclkRun;
					end if;

				else
					i := i + 1;

					stateMemclk <= stateMemclkReset;
				end if;

			elsif stateMemclk=stateMemclkRun then
				if reset_memclk='1' then
					resetMemclk <= '1';

					i := 0;

					stateMemclk <= stateMemclkReset;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.memclk.rising --- END

	------------------------------------------------------------------------
	-- implementation: pixrxclk wiring and reset (pixrxclk)
	------------------------------------------------------------------------

	-- IP impl.pixrxclk.wiring --- BEGIN
	-- IP impl.pixrxclk.wiring --- END

	-- IP impl.pixrxclk.wiring.cust --- LINE

	-- IP impl.pixrxclk.rising --- BEGIN
	process (aresetn, pixrxclk)
		-- IP impl.pixrxclk.vars --- BEGIN
		constant imax: natural := (16*fPixrxclk)/fMclk+1;
		variable i: natural range 0 to imax;
		-- IP impl.pixrxclk.vars --- END

	begin
		if aresetn='0' then
			-- IP impl.pixrxclk.asyncrst --- BEGIN
			statePixrxclk <= statePixrxclkReset;
			resetPixrxclk <= '1';
			reset_pixrxclk <= '1';
			reset_to_pixrxclkm1 <= '1';
			reset_to_pixrxclkm2 <= '1';

			i := 0;
			-- IP impl.pixrxclk.asyncrst --- END
			-- IP impl.pixrxclk.asyncrst.cust --- INSERT

		elsif rising_edge(pixrxclk) then
			if reset_to_pixrxclkm1=reset_to_pixrxclkm2 then
				reset_pixrxclk <= reset_to_pixrxclkm2;
			end if;
			reset_to_pixrxclkm1 <= reset;
			reset_to_pixrxclkm2 <= reset_to_pixrxclkm1;

			if statePixrxclk=statePixrxclkReset then
				if i=imax then
					if reset_pixrxclk='0' then
						resetPixrxclk <= '0';

						statePixrxclk <= statePixrxclkRun;
					end if;

				else
					i := i + 1;

					statePixrxclk <= statePixrxclkReset;
				end if;

			elsif statePixrxclk=statePixrxclkRun then
				if reset_pixrxclk='1' then
					resetPixrxclk <= '1';

					i := 0;

					statePixrxclk <= statePixrxclkReset;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.pixrxclk.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	probe <= probe_sig;
	
	-- IP impl.oth.cust --- IBEGIN
	resetnMemclk <= not resetMemclk;

	-- debug scenario I
	--probe_sig(0) <= apuAXIL_awvalid;
	--probe_sig(1) <= apuAXIL_awready_sig;

	--probe_sig(2) <= apuAXIL_wvalid;
	--probe_sig(3) <= apuAXIL_wready_sig;

	--probe_sig(4) <= apuAXIL_bready;
	--probe_sig(5) <= apuAXIL_bvalid_sig;

	-- debug scenario II
	--probe_sig(0) <= mipiAXIS_dbg(0);
	--probe_sig(1) <= mipiAXIS_dbg(1);
	--probe_sig(2) <= mipiAXIS_dbg(3);

	--probe_sig(3) <= video_out_dbg(0);
	--probe_sig(4) <= video_out_dbg(1);
	--probe_sig(5) <= video_out_dbg(3);

	-- debug scenario III
	--probe_sig(0) <= camifToVideoinAXIS_tvalid;
	--probe_sig(1) <= camifToVideoinAXIS_tlast;

	--probe_sig(2) <= grayVideoinToManyAXIS_tvalid;
	--probe_sig(3) <= grayVideoinToManyAXIS_tlast;

	--probe_sig(4) <= rgbVideoinToManyAXIS_tvalid;
	--probe_sig(5) <= rgbVideoinToManyAXIS_tlast;

	-- debug scenario IV
	--probe_sig(0) <= camifToVideoinAXIS_tdata(0);
	--probe_sig(1) <= camifToVideoinAXIS_tdata(1);

	--probe_sig(2) <= grayVideoinToManyAXIS_tdata(0);
	--probe_sig(3) <= grayVideoinToManyAXIS_tdata(1);

	--probe_sig(4) <= rgbVideoinToManyAXIS_tdata(0);
	--probe_sig(5) <= rgbVideoinToManyAXIS_tdata(1);

	-- debug scenario V
	probe_sig(0) <= reqHdrengToDdrifRd;
	probe_sig(1) <= ackHdrengToDdrifRd;

	probe_sig(2) <= reqHdrengToDdrifWr;
	probe_sig(3) <= ackHdrengToDdrifWr;

	probe_sig(4) <= ddrAXI_awvalid_sig;
	probe_sig(5) <= ddrAXI_wvalid_sig;

	--apuAXIL_awready <= apuAXIL_awready_sig;
	--apuAXIL_wready <= apuAXIL_wready_sig;
	--apuAXIL_bvalid <= apuAXIL_bvalid_sig;

	dbg0 <= x"00" & hostifStateOp_dbg;
	dbg1 <= x"00" & camifStateConfig_dbg;

	NCol <= NColRaw(11 downto 1);
	NRow <= NRowRaw(11 downto 1);

	ddrAXI_rready <= ddrAXI_rready_sig;
	ddrAXI_wvalid <= ddrAXI_wvalid_sig;
	-- IP impl.oth.cust --- IEND

end Rtl;


-- file Axislave_v1_0_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Axislave_v1_0_8c100ea18901433eb4f7c0fdbf115e06 module implementation
-- copyright: (C) 2023 MPSI Technologies GmbH
-- author: Alexander Wirthmueller
-- date created: 15 Feb 2023
-- date modified: 24 Apr 2023
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Axislave_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
	generic(
		fMclk: natural := 50000; -- in kHz

		wA: natural := 32;
		wD: natural := 32
	);
	port(
		reset: in std_logic;
		mclk: in std_logic;

		req: in std_logic;
		ack: out std_logic;
		dne: out std_logic;

		sendNotRecv: in std_logic;
		len: in std_logic_vector(31 downto 0); -- minus one

		recvAXIS_tready: in std_logic;
		recvAXIS_tvalid: out std_logic;
		recvAXIS_tdata: out std_logic_vector(wD-1 downto 0);
		recvAXIS_tlast: out std_logic;

		sendAXIS_tready: out std_logic;
		sendAXIS_tvalid: in std_logic;
		sendAXIS_tdata: in std_logic_vector(wD-1 downto 0);
		sendAXIS_tlast: in std_logic;

		-- FPGA to host
		AXIL_araddr: in std_logic_vector(wA-1 downto 0);
		AXIL_arprot: in std_logic_vector(2 downto 0);
		AXIL_arready: out std_logic;
		AXIL_arvalid: in std_logic;
		AXIL_rdata: out std_logic_vector(wD-1 downto 0);
		AXIL_rready: in std_logic;
		AXIL_rresp: out std_logic_vector(1 downto 0);
		AXIL_rvalid: out std_logic;
		AXIL_rlast: out std_logic;

		-- host to FPGA
		AXIL_awaddr: in std_logic_vector(wA-1 downto 0);
		AXIL_awprot: in std_logic_vector(2 downto 0);
		AXIL_awready: out std_logic;
		AXIL_awvalid: in std_logic;
		AXIL_wdata: in std_logic_vector(wD-1 downto 0);
		AXIL_wready: out std_logic;
		AXIL_wstrb: in std_logic_vector(wD/8-1 downto 0);
		AXIL_wvalid: in std_logic;
		AXIL_bready: in std_logic;
		AXIL_bresp: out std_logic_vector(1 downto 0);
		AXIL_bvalid: out std_logic
	);
end Axislave_v1_0_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Axislave_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant ixSetWrite: natural := 0;
	constant ixWrite: natural := 1;
	constant ixSetRead: natural := 2;
	constant ixRead: natural := 3; -- blk(ixRead) effectively never used

	constant msbABlk: natural := 5; -- implies 0x10 increments for block addresses, sufficient for wD = 128
	constant lsbABlk: natural := 4;

	---- host to FPGA AXI channel operation (write)
	signal AXIL_awready_sig: std_logic;
	signal AXIL_awaddr_sig: std_logic_vector(wA-1 downto 0);

	signal AXIL_wready_sig: std_logic;
	signal AXIL_wdata_sig: std_logic_vector(wD-1 downto 0);

	signal AXIL_bvalid_sig: std_logic;
	signal AXIL_bresp_sig: std_logic_vector(1 downto 0);

	signal ixBlkWrite: natural range 0 to 3;

	signal strbWrite: std_logic;

	---- FPGA to host AXI channel operation (read)
	signal AXIL_arready_sig: std_logic;
	signal AXIL_araddr_sig: std_logic_vector(wA-1 downto 0);

	signal AXIL_rresp_sig: std_logic_vector(1 downto 0);
	signal AXIL_rvalid_sig: std_logic;

	signal ixBlkRead: natural range 0 to 3;

	signal strbRead: std_logic;

	---- recv (receive operation)
	type stateRecv_t is (
		stateRecvInit,
		stateRecvWaitStart,
		stateRecvAckStart,
		stateRecvXferA, stateRecvXferB,
		stateRecvWaitStop,
		stateRecvDone,
		stateRecvTimeout
	);
	signal stateRecv: stateRecv_t;

	signal recvAck: std_logic;
	signal recvDne: std_logic;

	signal recvAXIL_rdata: std_logic_vector(wD-1 downto 0);

	signal recvAXIS_tdata_sig: std_logic_vector(wD-1 downto 0);
	signal recvAXIS_tlast_sig: std_logic;

	signal recvStrbToStart: std_logic;
	signal recvStrbToStop: std_logic;

	---- send (send operation)
	type stateSend_t is (
		stateSendInit,
		stateSendWaitStart,
		stateSendAckStart,
		stateSendXferA, stateSendXferB,
		stateSendWaitStop,
		stateSendDone,
		stateSendTimeout
	);
	signal stateSend: stateSend_t;

	signal sendAck: std_logic;
	signal sendDne: std_logic;

	signal sendAXIL_rdata: std_logic_vector(wD-1 downto 0);

	signal sendStrbToStart: std_logic;
	signal sendStrbToStop: std_logic;

	---- timeout (to)
	type stateTo_t is (
		stateToInit,
		stateToReady,
		stateToWait,
		stateToDone
	);
	signal stateTo: stateTo_t;

	signal timeout: std_logic;

	---- other
	signal resetn: std_Logic;

	signal len_nat: natural;

	------------------------------------------------------------------------
	-- functions
	------------------------------------------------------------------------

	function isTrue (
				vec: std_logic_vector(wD-1 downto 0)
			) return boolean is

		variable chk: boolean := true;

	begin
		for i in 0 to wD/2-1 loop
			if vec(2*(i+1)-1 downto 2*i)/="01" then
				chk := false;
			end if;
		end loop;

		return chk;
	end function;

	function isFalse (
				vec: std_logic_vector(wD-1 downto 0)
			) return boolean is

		variable chk: boolean := true;

	begin
		for i in 0 to wD/2-1 loop
			if vec(2*(i+1)-1 downto 2*i)/="10" then
				chk := false;
			end if;
		end loop;

		return chk;
	end function;

begin

	------------------------------------------------------------------------
	-- implementation: write (host to FPGA AXI channel operation)
	------------------------------------------------------------------------

	-- write channel
	AXIL_awready <= AXIL_awready_sig;
	ixBlkWrite <= to_integer(unsigned(AXIL_awaddr_sig(msbABlk downto lsbABlk)));

	AXIL_wready <= AXIL_wready_sig;

	AXIL_bresp <= AXIL_bresp_sig;
	AXIL_bvalid <= AXIL_bvalid_sig;

	strbWrite <= '1' when AXIL_bready='1' and AXIL_bvalid_sig='1' else '0';

	process (mclk)
		variable awdone, wdone: boolean;

	begin
		if rising_edge(mclk) then
			if resetn='0' then
				AXIL_awready_sig <= '0';
				AXIL_awaddr_sig <= (others => '0');

				AXIL_wready_sig <= '0';
				AXIL_wdata_sig <= (others => '0');

				AXIL_bvalid_sig <= '0';
				AXIL_bresp_sig <= "00";
				
				awdone := false;
				wdone := false;

			else
				if not awdone and AXIL_awvalid='1' and AXIL_awready_sig='0' then
					AXIL_awready_sig <= '1';
					AXIL_awaddr_sig <= AXIL_awaddr;
				
				elsif AXIL_awready_sig='1' then
					AXIL_awready_sig <= '0';

					awdone := true;
				end if;

				if not wdone and AXIL_wvalid='1' and AXIL_wready_sig='0' then
					AXIL_wready_sig <= '1';
					for i in 0 to (wD/8-1) loop -- this implies that strb(0) is for data(7 downto 0)
						if AXIL_wstrb(i)='1' then
							AXIL_wdata_sig((i+1)*8-1 downto i*8) <= AXIL_wdata((i+1)*8-1 downto i*8);
						end if;
					end loop;
				
				elsif AXIL_wready_sig='1' then
					AXIL_wready_sig <= '0';

					wdone := true;
				end if;

				if awdone and wdone then
					if AXIL_bvalid_sig='0' then
						AXIL_bvalid_sig <= '1';
					elsif AXIL_bready='1' then
						AXIL_bvalid_sig <= '0';
						
						awdone := false;
						wdone := false;
					end if;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: read (FPGA to host AXI channel operation)
	------------------------------------------------------------------------

	-- read channel
	AXIL_arready	<= AXIL_arready_sig;
	ixBlkRead <= to_integer(unsigned(AXIL_araddr_sig(msbABlk downto lsbABlk)));

	AXIL_rdata <= sendAXIL_rdata when sendNotRecv='1' else recvAXIL_rdata;

	AXIL_rresp	<= AXIL_rresp_sig;
	AXIL_rvalid	<= AXIL_rvalid_sig;

	strbRead <= '1' when AXIL_arready_sig='1' and AXIL_arvalid='1' else '0';

	process (mclk)

	begin
		if rising_edge(mclk) then
			if resetn='0' then
				AXIL_arready_sig <= '0';
				AXIL_araddr_sig <= (others => '0');

				AXIL_rvalid_sig <= '0';
				AXIL_rresp_sig	<= "00";

			else
				if (AXIL_arready_sig='0' and AXIL_arvalid='1' and AXIL_rvalid_sig='0') then
					AXIL_arready_sig <= '1';
					AXIL_araddr_sig	<= AXIL_araddr;
				else
					AXIL_arready_sig <= '0';
				end if;

				if (AXIL_arready_sig='1' and AXIL_arvalid='1') then
					AXIL_rvalid_sig <= '1';
				elsif (AXIL_rvalid_sig='1' and AXIL_rready='1') then
					AXIL_rvalid_sig <= '0';
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: receive operation (recv)
	------------------------------------------------------------------------

	recvAck <= '1' when stateRecv=stateRecvAckStart or stateRecv=stateRecvXferA or stateRecv=stateRecvXferB or stateRecv=stateRecvWaitStop or stateRecv=stateRecvDone else '0';
	recvDne <= '1' when stateRecv=stateRecvDone else '0';

	recvAXIS_tvalid <= '1' when stateRecv=stateRecvXferB else '0';

	recvAXIS_tdata <= recvAXIS_tdata_sig;
	recvAXIS_tlast <= recvAXIS_tlast_sig;

	process (reset, mclk, stateRecv)
		variable wordcnt: natural;

	begin
		if reset='1' then
			stateRecv <= stateRecvInit;
			recvAXIS_tdata_sig <= (others => '0');
			recvAXIS_tlast_sig <= '0';
			recvAXIL_rdata <= (others => '0');
			recvStrbToStart <= '0';
			recvStrbToStop <= '0';

		elsif rising_edge(mclk) then
			if stateRecv=stateRecvInit or req='0' or sendNotRecv='1' or (stateRecv/=stateRecvTimeout and timeout='1') then
				recvAXIS_tdata_sig <= (others => '0');
				recvAXIS_tlast_sig <= '0';
				recvAXIL_rdata <= (others => '0');
				recvStrbToStart <= '0';
				recvStrbToStop <= '0';

				if req='0' or sendNotRecv='1' then
					stateRecv <= stateRecvInit;
				elsif timeout='1' then
					stateRecv <= stateRecvTimeout;
				else
					stateRecv <= stateRecvWaitStart;
				end if;

			elsif stateRecv=stateRecvWaitStart then
				if strbWrite='1' and ixBlkWrite=ixSetWrite and isFalse(AXIL_wdata_sig) then
					recvStrbToStart <= '1';

					stateRecv <= stateRecvAckStart;
				end if;

			elsif stateRecv=stateRecvAckStart then
				if strbRead='1' and ixBlkRead=ixSetWrite then
					for i in 0 to wD/2-1 loop
						recvAXIL_rdata(2*(i+1)-1 downto 2*i) <= "10"; -- false
					end loop;

					wordcnt := 0;

					recvStrbToStart <= '1';

					stateRecv <= stateRecvXferA;

				else
					recvStrbToStart <= '0';
				end if;

			elsif stateRecv=stateRecvXferA then
				recvStrbToStart <= '0';

				if strbWrite='1' and ixBlkWrite=ixWrite then
					recvAXIS_tdata_sig <= AXIL_wdata_sig;

					if wordcnt=len_nat then -- words received minus one
						recvAXIS_tlast_sig <= '1';
					end if;

					recvStrbToStop <= '1';

					stateRecv <= stateRecvXferB;
				end if;

			elsif stateRecv=stateRecvXferB then -- recvAXIS_tvalid='1'
				recvStrbToStop <= '0';

				if recvAXIS_tready='1' then
					recvStrbToStart <= '1';

					if recvAXIS_tlast_sig='1' then
						stateRecv <= stateRecvWaitStop;

					else
						wordcnt := wordcnt + 1; -- words received
						stateRecv <= stateRecvXferA;
					end if;
				end if;
			
			elsif stateRecv=stateRecvWaitStop then
				recvStrbToStart <= '0';

				if strbWrite='1' and ixBlkWrite=ixSetWrite and isTrue(AXIL_wdata_sig) then
					recvStrbToStop <= '1';

					stateRecv <= stateRecvDone;
				end if;

			elsif stateRecv=stateRecvDone then
				recvStrbToStop <= '0';

				--if req='0' then
				--	stateRecv <= stateRecvInit;
				--end if;

			elsif stateRecv=stateRecvTimeout then
				--if req='0' then
				--	stateRecv <= stateRecvInit;
				--end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: send operation (send)
	------------------------------------------------------------------------

	sendAck <= '1' when stateSend=stateSendAckStart or stateSend=stateSendXferA or stateSend=stateSendXferB or stateSend=stateSendWaitStop or stateSend=stateSendDone else '0';
	sendDne <= '1' when stateSend=stateSendDone else '0';

	sendAXIS_tready <= '1' when stateSend=stateSendXferA else '0';

	process (reset, mclk, stateSend)
		variable wordcnt: natural;

	begin
		if reset='1' then
			stateSend <= stateSendInit;
			sendAXIL_rdata <= (others => '0');
			sendStrbToStart <= '0';
			sendStrbToStop <= '0';

		elsif rising_edge(mclk) then
			if stateSend=stateSendInit or req='0' or sendNotRecv='0' or (stateSend/=stateSendTimeout and timeout='1') then
				sendAXIL_rdata <= (others => '0');
				sendStrbToStart <= '0';
				sendStrbToStop <= '0';

				if req='0' or sendNotRecv='0' then
					stateSend <= stateSendInit;
				elsif timeout='1' then
					stateSend <= stateSendTimeout;
				else
					stateSend <= stateSendWaitStart;
				end if;

			elsif stateSend=stateSendWaitStart then
				if strbWrite='1' and ixBlkWrite=ixSetRead and isFalse(AXIL_wdata_sig) then
					sendStrbToStart <= '1';

					stateSend <= stateSendAckStart;
				end if;

			elsif stateSend=stateSendAckStart then
				sendStrbToStart <= '0';

				if strbRead='1' and ixBlkRead=ixSetRead then
					for i in 0 to wD/2-1 loop
						sendAXIL_rdata(2*(i+1)-1 downto 2*i) <= "10"; -- false
					end loop;

					wordcnt := 0;

					sendStrbToStop <= '1';

					stateSend <= stateSendXferA;
				end if;

			elsif stateSend=stateSendXferA then -- sendAXIS_tready='1'
				sendStrbToStop <= '0';

				if sendAXIS_tvalid='1' then
					sendAXIL_rdata <= sendAXIS_tdata;

					sendStrbToStart <= '1';

					stateSend <= stateSendXferB;
				end if;

			elsif stateSend=stateSendXferB then
				if strbRead='1' and ixBlkRead=ixRead then
					if wordcnt=len_nat then -- words sent minus one
						sendStrbToStart <= '1';

						stateSend <= stateSendWaitStop;
					
					else
						wordcnt := wordcnt + 1; -- words sent

						sendStrbToStart <= '0';
						sendStrbToStop <= '1';

						stateSend <= stateSendXferA;
					end if;

				else
					sendStrbToStart <= '0';
				end if;
			
			elsif stateSend=stateSendWaitStop then
				sendStrbToStart <= '0';

				if strbWrite='1' and ixBlkWrite=ixSetRead and isTrue(AXIL_wdata_sig) then
					sendStrbToStop <= '1';

					stateSend <= stateSendDone;
				end if;

			elsif stateSend=stateSendDone then
				sendStrbToStop <= '0';

				--if req='0' then
				--	stateSend <= stateSendInit;
				--end if;

			elsif stateSend=stateSendTimeout then
				--if req='0' then
				--	stateSend <= stateSendInit;
				--end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: timeout (to)
	------------------------------------------------------------------------

	timeout <= '1' when stateTo=stateToDone else '0';

	process (reset, mclk)
		constant twait: natural := fMclk/5; -- 200us
		variable i: natural range 0 to twait;

	begin
		if reset='1' then
			stateTo <= stateToInit;
			i := 0;

		elsif rising_edge(mclk) then
			if (stateTo=stateToInit or req='0') then
				i := 0;

				if req='0' then
					stateTo <= stateToInit;
				else
					stateTo <= stateToReady;
				end if;

			elsif stateTo=stateToReady then
				if recvStrbToStart='1' or sendStrbToStart='1' then
					i := 0;

					stateTo <= stateToWait;
				end if;

			elsif stateTo=stateToWait then
				if recvStrbToStart='1' or sendStrbToStart='1' then
					i := 0;

				elsif recvStrbToStop='1' or sendStrbToStop='1' then
					stateTo <= stateToReady;
				
				else
					i := i + 1;

					if i=twait then
						stateTo <= stateToDone;
					end if;
				end if;

			elsif stateTo=stateToDone then
				--if req='0' then
				--	stateTo <= stateToInit;
				--end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: other
	------------------------------------------------------------------------

	resetn <= not reset;

	ack <= sendAck when sendNotRecv='1' else recvAck;
	dne <= sendDne when sendNotRecv='1' else recvDne;

	AXIL_rlast <= '1';

	len_nat <= to_integer(unsigned(len));

end Rtl;


-- file Camif_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Camif_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Camif_8c100ea18901433eb4f7c0fdbf115e06 is
	generic (
		fMclk: natural -- in kHz
	);
	port (
		reset: in std_logic;
		mclk: in std_logic;
		resetPixrxclk: in std_logic;
		pixrxclk: in std_logic;
		tkclk: in std_logic;

		NRowRaw: in std_logic_vector(11 downto 0);
		NCol: in std_logic_vector(10 downto 0);

		toVideoinAXIS_tready: in std_logic;
		toVideoinAXIS_tvalid: out std_logic;
		toVideoinAXIS_tdata: out std_logic_vector(23 downto 0);
		toVideoinAXIS_tlast: out std_logic;

		reqInvConfig: in std_logic;
		ackInvConfig: out std_logic;

		configHdrNotFix: in std_logic_vector(7 downto 0);
		configSynthNotLive: in std_logic_vector(7 downto 0);

		reqInvConfigSynth: in std_logic;
		ackInvConfigSynth: out std_logic;

		configSynthTixVSynthmode: in std_logic_vector(7 downto 0);
		configSynthTFramepad: in std_logic_vector(15 downto 0);
		configSynthTLinepad: in std_logic_vector(7 downto 0);

		reqInvSetReg: in std_logic;
		ackInvSetReg: out std_logic;

		setRegAddr: in std_logic_vector(15 downto 0);
		setRegVal: in std_logic_vector(7 downto 0);

		reqInvGetReg: in std_logic;
		ackInvGetReg: out std_logic;

		getRegAddr: in std_logic_vector(15 downto 0);
		getRegVal: out std_logic_vector(7 downto 0);

		reqInvModReg: in std_logic;
		ackInvModReg: out std_logic;

		modRegAddr: in std_logic_vector(15 downto 0);
		modRegMask: in std_logic_vector(7 downto 0);
		modRegVal: in std_logic_vector(7 downto 0);

		reqInvSetCorereg: in std_logic;
		ackInvSetCorereg: out std_logic;

		setCoreregAddr: in std_logic_vector(7 downto 0);
		setCoreregVal: in std_logic_vector(31 downto 0);

		reqInvGetCorereg: in std_logic;
		ackInvGetCorereg: out std_logic;

		getCoreregAddr: in std_logic_vector(7 downto 0);
		getCoreregVal: out std_logic_vector(31 downto 0);

		rng: in std_logic;

		vsync: out std_logic;
		ixTExp: out std_logic_vector(3 downto 0);

		clk_byte_HS: in std_logic;

		mipirx_RESET_N: out std_logic;
		mipirx_RST0_N: out std_logic;
		mipirx_ERR_CONTROL_LAN0: in std_logic;
		mipirx_ERR_CONTROL_LAN1: in std_logic;
		mipirx_ERR_CONTROL_LAN2: in std_logic;
		mipirx_ERR_CONTROL_LAN3: in std_logic;
		mipirx_ERR_ESC_LAN0: in std_logic;
		mipirx_ERR_ESC_LAN1: in std_logic;
		mipirx_ERR_ESC_LAN2: in std_logic;
		mipirx_ERR_ESC_LAN3: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN0: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN1: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN2: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN3: in std_logic;
		mipirx_ESC_CLK_LAN0: in std_logic;
		mipirx_ESC_CLK_LAN1: in std_logic;
		mipirx_ESC_CLK_LAN2: in std_logic;
		mipirx_ESC_CLK_LAN3: in std_logic;
		mipirx_RX_DATA_HS_LAN0: in std_logic_vector(15 downto 0);
		mipirx_RX_DATA_HS_LAN1: in std_logic_vector(15 downto 0);
		mipirx_RX_DATA_HS_LAN2: in std_logic_vector(15 downto 0);
		mipirx_RX_DATA_HS_LAN3: in std_logic_vector(15 downto 0);
		mipirx_RX_SKEW_CAL_HS_LAN0: in std_logic;
		mipirx_RX_SKEW_CAL_HS_LAN1: in std_logic;
		mipirx_RX_SKEW_CAL_HS_LAN2: in std_logic;
		mipirx_RX_SKEW_CAL_HS_LAN3: in std_logic;
		mipirx_RX_SYNC_HS_LAN0: in std_logic;
		mipirx_RX_SYNC_HS_LAN1: in std_logic;
		mipirx_RX_SYNC_HS_LAN2: in std_logic;
		mipirx_RX_SYNC_HS_LAN3: in std_logic;
		mipirx_RX_ULPS_ACTIVE_CLK_NOT: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN0: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN1: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN2: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN3: in std_logic;
		mipirx_RX_ULPS_CLK_NOT: in std_logic;
		mipirx_RX_ULPS_ESC_LAN0: in std_logic;
		mipirx_RX_ULPS_ESC_LAN1: in std_logic;
		mipirx_RX_ULPS_ESC_LAN2: in std_logic;
		mipirx_RX_ULPS_ESC_LAN3: in std_logic;
		mipirx_RX_VALID_HS_LAN0: in std_logic;
		mipirx_RX_VALID_HS_LAN1: in std_logic;
		mipirx_RX_VALID_HS_LAN2: in std_logic;
		mipirx_RX_VALID_HS_LAN3: in std_logic;
		mipirx_STOPSTATE_LAN0: in std_logic;
		mipirx_STOPSTATE_LAN1: in std_logic;
		mipirx_STOPSTATE_LAN2: in std_logic;
		mipirx_STOPSTATE_LAN3: in std_logic;

		scl_in: in std_logic;
		scl_out: out std_logic;
		scl_tri: out std_logic;

		sda_in: in std_logic;
		sda_out: out std_logic;
		sda_tri: out std_logic;

		RxDataHS0: in std_logic_vector(15 downto 0);
		RxDataHS1: in std_logic_vector(15 downto 0);
		RxDataHS2: in std_logic_vector(15 downto 0);
		RxDataHS3: in std_logic_vector(15 downto 0);

		datatype_dbg: out std_logic_vector(5 downto 0);
		mipiAXIS_dbg: out std_logic_vector(3 downto 0);
		video_out_dbg: out std_logic_vector(3 downto 0);

		stateConfig_dbg: out std_logic_vector(7 downto 0)
	);
end Camif_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Camif_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component I2cmaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
		generic (
			fMclk: natural := 50000;
			clkFastNotStd: std_logic := '0';
			clkFastplusNotFast: std_logic := '0'
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;

			req: in std_logic;
			ack: out std_logic;
			dne: out std_logic;

			devaddr: in std_logic_vector(7 downto 0);
			r16Not8: in std_logic;
			d16Not8: in std_logic;
			readNotWrite: in std_logic;
			readAradNotArd: in std_logic;
			writeAdNotArd: in std_logic;
			regaddr: in std_logic_vector(15 downto 0);
			send: in std_logic_vector(15 downto 0);
			recv: out std_logic_vector(15 downto 0);

			scl_in: in std_logic;
			scl_out: out std_logic;
			scl_tri: out std_logic;

			sda_in: in std_logic;
			sda_out: out std_logic;
			sda_tri: out std_logic
		);
	end component;

	component Csi2_hard_mipi_rx_efnx_w4 is
		port (
			reset_n: in std_logic;
			reset_byte_HS_n: in std_logic;
			reset_pixel_n: in std_logic;
			axi_reset_n: in std_logic;
			clk: in std_logic;
			clk_byte_HS: in std_logic;
			clk_pixel: in std_logic;
			axi_clk: in std_logic;

			RxClkEsc: in std_logic_vector(3 downto 0);
			RxErrEsc: in std_logic_vector(3 downto 0);
			RxErrControl: in std_logic_vector(3 downto 0);
			RxErrSotSyncHS: in std_logic_vector(3 downto 0);
			RxUlpsEsc: in std_logic_vector(3 downto 0);
			RxUlpsActiveNot: in std_logic_vector(3 downto 0);
			RxSkewCalHS: in std_logic_vector(3 downto 0);
			RxStopState: in std_logic_vector(3 downto 0);
			RxSyncHS: in std_logic_vector(3 downto 0);

			RxValidHS0: in std_logic_vector(1 downto 0);
			RxValidHS1: in std_logic_vector(1 downto 0);
			RxValidHS2: in std_logic_vector(1 downto 0);
			RxValidHS3: in std_logic_vector(1 downto 0);
			RxValidHS4: in std_logic_vector(1 downto 0);
			RxValidHS5: in std_logic_vector(1 downto 0);
			RxValidHS6: in std_logic_vector(1 downto 0);
			RxValidHS7: in std_logic_vector(1 downto 0);

			irq: out std_logic;
			pixel_per_clk: out std_logic_vector(3 downto 0);
			pixel_data: out std_logic_vector(63 downto 0);
			pixel_data_valid: out std_logic;
			datatype: out std_logic_vector(5 downto 0);
			shortpkt_data_field: out std_logic_vector(15 downto 0);
			word_count: out std_logic_vector(15 downto 0);
			vc: out std_logic_vector(1 downto 0);

			vsync_vc0: out std_logic;
			vsync_vc1: out std_logic;
			vsync_vc2: out std_logic;
			vsync_vc3: out std_logic;
			vsync_vc4: out std_logic;
			vsync_vc5: out std_logic;
			vsync_vc6: out std_logic;
			vsync_vc7: out std_logic;
			vsync_vc8: out std_logic;
			vsync_vc9: out std_logic;
			vsync_vc10: out std_logic;
			vsync_vc11: out std_logic;
			vsync_vc12: out std_logic;
			vsync_vc13: out std_logic;
			vsync_vc14: out std_logic;
			vsync_vc15: out std_logic;

			hsync_vc0: out std_logic;
			hsync_vc1: out std_logic;
			hsync_vc2: out std_logic;
			hsync_vc3: out std_logic;
			hsync_vc4: out std_logic;
			hsync_vc5: out std_logic;
			hsync_vc6: out std_logic;
			hsync_vc7: out std_logic;
			hsync_vc8: out std_logic;
			hsync_vc9: out std_logic;
			hsync_vc10: out std_logic;
			hsync_vc11: out std_logic;
			hsync_vc12: out std_logic;
			hsync_vc13: out std_logic;
			hsync_vc14: out std_logic;
			hsync_vc15: out std_logic;

			axi_araddr: in std_logic_vector(5 downto 0);
			axi_arready: out std_logic;
			axi_arvalid: in std_logic;
			axi_rdata: out std_logic_vector(31 downto 0);
			axi_rready: in std_logic;
			axi_rvalid: out std_logic;
			axi_awaddr: in std_logic_vector(5 downto 0);
			axi_awready: out std_logic;
			axi_awvalid: in std_logic;
			axi_wdata: in std_logic_vector(31 downto 0);
			axi_wready: out std_logic;
			axi_wvalid: in std_logic;
			axi_bready: in std_logic;
			axi_bvalid: out std_logic;

			RxUlpsClkNot: in std_logic_vector(0 downto 0);
			RxUlpsActiveClkNot: in std_logic_vector(0 downto 0);

			RxDataHS0: in std_logic_vector(15 downto 0);
			RxDataHS1: in std_logic_vector(15 downto 0);
			RxDataHS2: in std_logic_vector(15 downto 0);
			RxDataHS3: in std_logic_vector(15 downto 0);
			RxDataHS4: in std_logic_vector(15 downto 0);
			RxDataHS5: in std_logic_vector(15 downto 0);
			RxDataHS6: in std_logic_vector(15 downto 0);
			RxDataHS7: in std_logic_vector(15 downto 0)
		);
	end component;

	component Spram_v1_0_size2kB_w8_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			reset: in std_logic;
			clk: in std_logic;

			en: in std_logic;
			we: in std_logic;

			a: in std_logic_vector(10 downto 0);
			drd: out std_logic_vector(7 downto 0);
			dwr: in std_logic_vector(7 downto 0)
		);
	end component;

	component Sprsaxisfwd_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
		generic (
			wSize: natural range 3 to 16 := 12;
			wIxHshk: natural range 4 to 8 := 4;
			wIxData: natural range 2 to 6 := 4;
			wData: natural range 8 to 256 := 64;
			wUser: natural range 1 to 96 := 6
		);
		port (
			resetIgrclk: in std_logic;
			igrclk: in std_logic;

			reset: in std_logic;
			mclk: in std_logic;

			igrAXIS_tready: out std_logic;
			igrAXIS_tvalid: in std_logic;
			igrAXIS_tdata: in std_logic_vector(wData-1 downto 0);
			igrAXIS_tkeep: in std_logic_vector(wData/8-1 downto 0);
			igrAXIS_tlast: in std_logic;
			igrAXIS_tuser: in std_logic_vector(wUser-1 downto 0);

			enEgr: in std_logic;

			egrAXIS_tready: in std_logic;
			egrAXIS_tvalid: out std_logic;
			egrAXIS_tdata: out std_logic_vector(wData-1 downto 0);
			egrAXIS_tkeep: out std_logic_vector(wData/8-1 downto 0);
			egrAXIS_tlast: out std_logic;
			egrAXIS_tuser: out std_logic_vector(wUser-1 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant tixVSynthmodeRgb: std_logic_vector(7 downto 0) := x"00";
	constant tixVSynthmodeHdr: std_logic_vector(7 downto 0) := x"01";
	constant tixVSynthmodeChk: std_logic_vector(7 downto 0) := x"02";

	constant tixVFormatRaw8: std_logic_vector(7 downto 0) := x"2A";
	constant tixVFormatRaw10: std_logic_vector(7 downto 0) := x"2B";
	constant tixVFormatRaw12: std_logic_vector(7 downto 0) := x"2C";
	constant tixVFormatRaw14: std_logic_vector(7 downto 0) := x"2D";

	---- bytehsclk wiring and reset (bytehsclk)
	type stateBytehsclk_t is (
		stateBytehsclkReset,
		stateBytehsclkRun
	);
	signal stateBytehsclk: stateBytehsclk_t;

	signal resetnBytehsclk: std_logic;

	signal reset_bytehsclk: std_logic;
	signal reset_to_bytehsclkm1: std_logic;
	signal reset_to_bytehsclkm2: std_logic;

	-- IP sigs.bytehsclk.cust --- INSERT

	---- I2C configuration (config)
	type stateConfig_t is (
		stateConfigInit,
		stateConfigPrepA, stateConfigPrepB, stateConfigPrepC, stateConfigPrepD,
		stateConfigLoadA, stateConfigLoadB,
		stateConfigXfer,
		stateConfigStep,
		stateConfigPwupdnA, stateConfigPwupdnB,
		stateConfigInv
	);
	signal stateConfig: stateConfig_t;

	signal ackInvSetReg_sig: std_logic;
	signal ackInvGetReg_sig: std_logic;
	signal regVal: std_logic_vector(7 downto 0);
	signal ackInvModReg_sig: std_logic;
	signal enParrom: std_logic;

	signal aParrom_vec: std_logic_vector(10 downto 0);
	signal aParrom: natural range 0 to 2047;

	signal i2cReadNotWrite: std_logic;
	signal i2cRegaddr: std_logic_vector(15 downto 0);
	signal i2cSend: std_logic_vector(15 downto 0);

	-- IP sigs.config.cust --- INSERT

	---- MIPI RX core configuration (corecfg)
	type stateCorecfg_t is (
		stateCorecfgInit,
		stateCorecfgReadA, stateCorecfgReadB, stateCorecfgReadC,
		stateCorecfgWriteA, stateCorecfgWriteB, stateCorecfgWriteC,
		stateCorecfgInv
	);
	signal stateCorecfg: stateCorecfg_t;

	signal ackInvGetCorereg_sig: std_logic;
	signal getCoreregVal_sig: std_logic_vector(31 downto 0);
	signal ackInvSetCorereg_sig: std_logic;
	signal corecfgAXIL_araddr: std_logic_vector(5 downto 0);

	signal corecfgAXIL_awaddr: std_logic_vector(5 downto 0);
	signal corecfgAXIL_wdata: std_logic_vector(31 downto 0);

	-- IP sigs.corecfg.cust --- INSERT

	---- gearing from quad-RAW12 to dual-RAW12 (gear)

	signal enEgr: std_logic;
	signal pixrxclk_mclk: std_logic_vector(2 downto 0);

	signal video_out_tvalid: std_logic;
	signal video_out_tdata: std_logic_vector(23 downto 0);
	signal video_out_tlast: std_logic;
	signal video_out_tuser: std_logic_vector(5 downto 0);

	-- IP sigs.gear.cust --- INSERT

	---- live streaming operation (live)
	type stateLive_t is (
		stateLiveInit,
		stateLivePre,
		stateLiveRun,
		stateLiveUpdTExpA, stateLiveUpdTExpB
	);
	signal stateLive: stateLive_t;

	constant regShr0_0: std_logic_vector(15 downto 0) := x"3058";
	constant regShr0_1: std_logic_vector(15 downto 0) := x"3059";

	constant TExp0: std_logic_vector(15 downto 0) := x"0009"; -- longest, 66.47 ms / 2
	constant TExp1: std_logic_vector(15 downto 0) := x"0F44";
	constant TExp2: std_logic_vector(15 downto 0) := x"114A";
	constant TExp3: std_logic_vector(15 downto 0) := x"118B";
	constant TExp4: std_logic_vector(15 downto 0) := x"1193"; -- shortest, 17.1 us / 2

	constant rowRawStart: natural := 20;
	constant ixTExpLast: natural := 4;
	signal resetn: std_logic;
	signal resetnPixrxclk: std_logic;

	signal mipirx_ERR_CONTROL: std_logic_vector(3 downto 0);
	signal mipirx_ERR_ESC: std_logic_vector(3 downto 0);
	signal mipirx_ERR_SOT_SYNC_HS: std_logic_vector(3 downto 0);
	signal mipirx_ESC_CLK: std_logic_vector(3 downto 0);
	signal mipirx_RX_SKEW_CAL_HS: std_logic_vector(3 downto 0);
	signal mipirx_RX_SYNC_HS: std_logic_vector(3 downto 0);
	signal mipirx_RX_ULPS_ACTIVE_NOT: std_logic_vector(3 downto 0);
	signal mipirx_RX_ULPS_ESC: std_logic_vector(3 downto 0);
	signal mipirx_RX_VALID_HS_LAN0_sig: std_logic_vector(1 downto 0);
	signal mipirx_RX_VALID_HS_LAN1_sig: std_logic_vector(1 downto 0);
	signal mipirx_RX_VALID_HS_LAN2_sig: std_logic_vector(1 downto 0);
	signal mipirx_RX_VALID_HS_LAN3_sig: std_logic_vector(1 downto 0);
	signal mipirx_RX_ULPS_CLK_NOT_sig: std_logic_vector(0 downto 0);
	signal mipirx_RX_ULPS_ACTIVE_CLK_NOT_sig: std_logic_vector(0 downto 0);
	signal mipirx_STOPSTATE: std_logic_vector(3 downto 0);

	signal rowRawLast: natural range 0 to 2999;
	signal liveIxTExp: natural range 0 to ixTExpLast;

	signal liveSetRegAddr: std_logic_vector(15 downto 0);
	signal liveSetRegVal: std_logic_vector(7 downto 0);

	signal video_out_tlastm1: std_logic;

	-- IP sigs.live.cust --- INSERT

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv
	);
	signal stateOp: stateOp_t;

	signal ackInvConfig_sig: std_logic;
	signal hdrNotFix: std_logic;
	signal synthNotLive: std_logic;
	signal ackInvConfigSynth_sig: std_logic;
	signal tixVSynthmode: std_logic_vector(7 downto 0);
	signal TFramepad: std_logic_vector(15 downto 0);
	signal TLinepad: std_logic_vector(7 downto 0);
	signal tixVFormat: std_logic_vector(5 downto 0);

	-- IP sigs.op.cust --- INSERT

	---- forwarding of raw pixel data (rxfwd)

	signal pixel_datap1: std_logic_vector(63 downto 0);
	signal pixel_data_validp1: std_logic;
	signal datatypep1: std_logic_vector(5 downto 0);

	signal hsync_vc0n: std_logic;

	-- IP sigs.rxfwd.cust --- INSERT

	---- frame synthesis operation (synth)
	type stateSynth_t is (
		stateSynthInit,
		stateSynthRgb,
		stateSynthHdr,
		stateSynthChk,
		stateSynthEol,
		stateSynthEofA, stateSynthEofB
	);
	signal stateSynth: stateSynth_t;

	signal toVideoinAXIS_tvalid_sig: std_logic;
	signal toVideoinAXIS_tdata_sig: std_logic_vector(23 downto 0);
	signal toVideoinAXIS_tlast_sig: std_logic;

	signal vsync_sig: std_logic;
	signal ixTExp_sig: natural range 0 to ixTExpLast;

	signal row: unsigned(11 downto 0);
	signal col: unsigned(10 downto 0);

	-- IP sigs.synth.cust --- INSERT

	---- myI2c
	signal i2cRecv: std_logic_vector(15 downto 0);

	---- myMipirx
	signal pixel_per_clk: std_logic_vector(3 downto 0);

	signal pixel_data: std_logic_vector(63 downto 0);
	signal pixel_data_valid: std_logic;
	signal datatype: std_logic_vector(5 downto 0);

	signal word_count: std_logic_vector(15 downto 0);

	signal vsync_vc0: std_logic;
	signal hsync_vc0: std_logic;

	signal corecfgAXIL_rdata: std_logic_vector(31 downto 0);

	---- myParrom
	signal drdParrom: std_logic_vector(7 downto 0);

	---- myRawfwd
	signal video_out_x2_tvalid: std_logic;
	signal video_out_x2_tdata: std_logic_vector(63 downto 0);
	signal video_out_x2_tlast: std_logic;
	signal video_out_x2_tuser: std_logic_vector(5 downto 0);

	---- handshake
	-- config to myI2c
	signal reqI2c: std_logic;
	signal ackI2c: std_logic;
	signal dneI2c: std_logic;

	-- myMipirx to corecfg
	signal corecfgAXIL_arready: std_logic;
	signal corecfgAXIL_arvalid: std_logic;

	-- corecfg to myMipirx
	signal corecfgAXIL_rready: std_logic;
	signal corecfgAXIL_rvalid: std_logic;

	-- myMipirx to corecfg
	signal corecfgAXIL_awready: std_logic;
	signal corecfgAXIL_awvalid: std_logic;

	-- myMipirx to corecfg
	signal corecfgAXIL_wready: std_logic;
	signal corecfgAXIL_wvalid: std_logic;

	-- corecfg to myMipirx
	signal corecfgAXIL_bready: std_logic;
	signal corecfgAXIL_bvalid: std_logic;

	-- live to config
	signal reqLiveToConfigSetReg: std_logic;
	signal ackLiveToConfigSetReg: std_logic;

	---- other
	-- IP sigs.oth.cust --- IBEGIN

	------------------------------------------------------------------------
	-- functional description
	------------------------------------------------------------------------

	-- for simplicity (cross-platform and dphy clock required for Xilinx), target fMclk = 200 MHz

	-- IMX335 line rate 1188 Mbps x4 lanes @RAW12 allows for 396 Mpix/s
	-- 60 fps @ 2592x1944 corresponds to 302 Mpix/s (not a good indication for during-row rate because of h/v blanks)
	-- condensed gray or rgb format features 1296x972 pixels at quarter data date 

	-- for 1188 Mbps four-lane, Xilinx PG232 mandates pixclk > 148.5 MHz
	-- i.e. 200 MHz, 2 ppi should be fine for video_out_tdata

	-- with 200 MHz pixel clock, 12 MP = 4000x3000 -> 2000x1500 should be attainable at 66.67 fps
	-- however, 4ppi might be required and videoinToManyAXIS may have to keep tvalid high continuously

	-- IP sigs.oth.cust --- IEND

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myI2c : I2cmaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			fMclk => fMclk,
			clkFastNotStd => '0',
			clkFastplusNotFast => '0'
		)
		port map (
			reset => reset,
			mclk => mclk,

			req => reqI2c,
			ack => open,
			dne => dneI2c,

			devaddr => "00011010",
			r16Not8 => '1',
			d16Not8 => '0',
			readNotWrite => i2cReadNotWrite,
			readAradNotArd => '1',
			writeAdNotArd => '0',
			regaddr => i2cRegaddr,
			send => i2cSend,
			recv => i2cRecv,

			scl_in => scl_in,
			scl_out => scl_out,
			scl_tri => scl_tri,

			sda_in => sda_in,
			sda_out => sda_out,
			sda_tri => sda_tri
		);

	myMipirx : Csi2_hard_mipi_rx_efnx_w4
		port map (
			reset_n => resetnPixrxclk,
			reset_byte_HS_n => resetnBytehsclk,
			reset_pixel_n => resetn,
			axi_reset_n => resetn,
			clk => pixrxclk,
			clk_byte_HS => clk_byte_HS,
			clk_pixel => pixrxclk,
			axi_clk => mclk,

			RxClkEsc => mipirx_ESC_CLK,
			RxErrEsc => mipirx_ERR_ESC,
			RxErrControl => mipirx_ERR_CONTROL,
			RxErrSotSyncHS => mipirx_ERR_SOT_SYNC_HS,
			RxUlpsEsc => mipirx_RX_ULPS_ESC,
			RxUlpsActiveNot => mipirx_RX_ULPS_ACTIVE_NOT,
			RxSkewCalHS => mipirx_RX_SKEW_CAL_HS,
			RxStopState => mipirx_STOPSTATE,
			RxSyncHS => mipirx_RX_SYNC_HS,

			RxValidHS0 => mipirx_RX_VALID_HS_LAN0_sig,
			RxValidHS1 => mipirx_RX_VALID_HS_LAN1_sig,
			RxValidHS2 => mipirx_RX_VALID_HS_LAN2_sig,
			RxValidHS3 => mipirx_RX_VALID_HS_LAN3_sig,
			RxValidHS4 => (others => '0'),
			RxValidHS5 => (others => '0'),
			RxValidHS6 => (others => '0'),
			RxValidHS7 => (others => '0'),

			irq => open,
			pixel_per_clk => pixel_per_clk,
			pixel_data => pixel_data,
			pixel_data_valid => pixel_data_valid,
			datatype => datatype,
			shortpkt_data_field => open,
			word_count => word_count,
			vc => open,

			vsync_vc0 => vsync_vc0,
			vsync_vc1 => open,
			vsync_vc2 => open,
			vsync_vc3 => open,
			vsync_vc4 => open,
			vsync_vc5 => open,
			vsync_vc6 => open,
			vsync_vc7 => open,
			vsync_vc8 => open,
			vsync_vc9 => open,
			vsync_vc10 => open,
			vsync_vc11 => open,
			vsync_vc12 => open,
			vsync_vc13 => open,
			vsync_vc14 => open,
			vsync_vc15 => open,

			hsync_vc0 => hsync_vc0,
			hsync_vc1 => open,
			hsync_vc2 => open,
			hsync_vc3 => open,
			hsync_vc4 => open,
			hsync_vc5 => open,
			hsync_vc6 => open,
			hsync_vc7 => open,
			hsync_vc8 => open,
			hsync_vc9 => open,
			hsync_vc10 => open,
			hsync_vc11 => open,
			hsync_vc12 => open,
			hsync_vc13 => open,
			hsync_vc14 => open,
			hsync_vc15 => open,

			axi_araddr => corecfgAXIL_araddr,
			axi_arready => corecfgAXIL_arready,
			axi_arvalid => corecfgAXIL_arvalid,
			axi_rdata => corecfgAXIL_rdata,
			axi_rready => corecfgAXIL_rready,
			axi_rvalid => corecfgAXIL_rvalid,
			axi_awaddr => corecfgAXIL_awaddr,
			axi_awready => corecfgAXIL_awready,
			axi_awvalid => corecfgAXIL_awvalid,
			axi_wdata => corecfgAXIL_wdata,
			axi_wready => corecfgAXIL_wready,
			axi_wvalid => corecfgAXIL_wvalid,
			axi_bready => corecfgAXIL_bready,
			axi_bvalid => corecfgAXIL_bvalid,

			RxUlpsClkNot => mipirx_RX_ULPS_CLK_NOT_sig,
			RxUlpsActiveClkNot => mipirx_RX_ULPS_ACTIVE_CLK_NOT_sig,

			RxDataHS0 => RxDataHS0,
			RxDataHS1 => RxDataHS1,
			RxDataHS2 => RxDataHS2,
			RxDataHS3 => RxDataHS3,
			RxDataHS4 => (others => '0'),
			RxDataHS5 => (others => '0'),
			RxDataHS6 => (others => '0'),
			RxDataHS7 => (others => '0')
		);

	myParrom : Spram_v1_0_size2kB_w8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			clk => mclk,

			en => enParrom,
			we => '0',

			a => aParrom_vec,
			drd => drdParrom,
			dwr => (others => '0')
		);

	myRawfwd : Sprsaxisfwd_v1_0_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			wSize => 12,
			wIxHshk => 4,
			wIxData => 4,
			wData => 64,
			wUser => 6
		)
		port map (
			resetIgrclk => reset, -- in mclk domain
			igrclk => pixrxclk,

			reset => reset,
			mclk => mclk,

			igrAXIS_tready => open, -- always 1
			igrAXIS_tvalid => pixel_data_validp1,
			igrAXIS_tdata => pixel_datap1,
			igrAXIS_tkeep => (others => '1'),
			igrAXIS_tlast => hsync_vc0n,
			igrAXIS_tuser => datatypep1,

			enEgr => enEgr,

			egrAXIS_tready => '1',
			egrAXIS_tvalid => video_out_x2_tvalid,
			egrAXIS_tdata => video_out_x2_tdata,
			egrAXIS_tkeep => open,
			egrAXIS_tlast => video_out_x2_tlast,
			egrAXIS_tuser => video_out_x2_tuser
		);

	------------------------------------------------------------------------
	-- implementation: bytehsclk wiring and reset (bytehsclk)
	------------------------------------------------------------------------

	-- IP impl.bytehsclk.wiring --- BEGIN
	-- IP impl.bytehsclk.wiring --- END

	-- IP impl.bytehsclk.wiring.cust --- LINE

	-- IP impl.bytehsclk.rising --- BEGIN
	process (reset, clk_byte_HS)
		-- IP impl.bytehsclk.vars --- RBEGIN
		constant fBytehsclk: natural := 148500; -- at 1188 Mbps, expect 148.5 MHz
		constant imax: natural := (16*fBytehsclk)/fMclk+1;
		variable i: natural range 0 to imax;
		-- IP impl.bytehsclk.vars --- REND

	begin
		if reset='1' then
			-- IP impl.bytehsclk.asyncrst --- BEGIN
			stateBytehsclk <= stateBytehsclkReset;
			resetnBytehsclk <= '0';
			reset_bytehsclk <= '1';
			reset_to_bytehsclkm1 <= '1';
			reset_to_bytehsclkm2 <= '1';

			-- IP impl.bytehsclk.asyncrst --- END
			-- IP impl.bytehsclk.asyncrst.cust --- IBEGIN
			i := 0;
			-- IP impl.bytehsclk.asyncrst.cust --- IEND

		elsif rising_edge(clk_byte_HS) then
		-- IP impl.bytehsclk.pre --- IBEGIN
			if reset_to_bytehsclkm1=reset_to_bytehsclkm2 then
				reset_bytehsclk <= reset_to_bytehsclkm2;
			end if;
			reset_to_bytehsclkm1 <= reset;
			reset_to_bytehsclkm2 <= reset_to_bytehsclkm1;
		-- IP impl.bytehsclk.pre --- IEND

			if stateBytehsclk=stateBytehsclkReset then
				-- IP impl.bytehsclk.syncrst --- RBEGIN

				-- IP impl.bytehsclk.syncrst --- REND
				-- IP impl.bytehsclk.syncrst.cust --- INSERT

				if i=imax then
					if reset_bytehsclk='0' then
						resetnBytehsclk <= '1'; -- IP impl.bytehsclk.reset.done --- ILINE

						stateBytehsclk <= stateBytehsclkRun;

					else
						stateBytehsclk <= stateBytehsclkReset;
					end if;

				else
					i := i + 1; -- IP impl.bytehsclk.reset.inc --- ILINE

					stateBytehsclk <= stateBytehsclkReset;
				end if;

			elsif stateBytehsclk=stateBytehsclkRun then
				if reset_bytehsclk='1' then
					resetnBytehsclk <= '0'; -- IP impl.bytehsclk.run --- ILINE

					stateBytehsclk <= stateBytehsclkReset;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.bytehsclk.rising --- END

	------------------------------------------------------------------------
	-- implementation: I2C configuration (config)
	------------------------------------------------------------------------

	-- IP impl.config.wiring --- RBEGIN
	ackInvSetReg <= ackInvSetReg_sig;

	ackInvGetReg <= ackInvGetReg_sig;
	getRegVal <= regVal;

	ackInvModReg <= ackInvModReg_sig;

	enParrom <= '1' when stateConfig=stateConfigLoadA else '0';
	
	aParrom_vec <= std_logic_vector(to_unsigned(aParrom, 11));

	reqI2c <= '1' when stateConfig=stateConfigXfer else '0';
	-- IP impl.config.wiring --- REND

	-- IP impl.config.wiring.cust --- LINE

	stateConfig_dbg <= x"00" when stateConfig=stateConfigInit
				else x"10" when stateConfig=stateConfigPrepA
				else x"11" when stateConfig=stateConfigPrepB
				else x"12" when stateConfig=stateConfigPrepC
				else x"13" when stateConfig=stateConfigPrepD
				else x"20" when stateConfig=stateConfigLoadA
				else x"21" when stateConfig=stateConfigLoadB
				else x"30" when stateConfig=stateConfigXfer
				else x"40" when stateConfig=stateConfigStep
				else x"50" when stateConfig=stateConfigPwupdnA
				else x"51" when stateConfig=stateConfigPwupdnB
				else x"60" when stateConfig=stateConfigInv
				else (others => '1');

	-- IP impl.config.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.config.vars --- RBEGIN
		constant a0ParromGnr: natural := 0; -- IMX219 (or IMX227?)
		constant a0ParromSpec: natural := 512;

		constant a0ParromGnr2: natural := 1024; -- IMX335
		constant a0ParromSpec2: natural := 1536;

		variable prepdone: boolean;

		variable specNotGnr: boolean; -- during preparation: general vs. resolution-specific (leftover from OV5640)

		variable modNotGetSet: boolean;
		variable liveNotExt: boolean;

		variable bytecnt: natural range 0 to 4;

		constant imax: natural := 10; -- 1ms power up to reset high
		variable i: natural range 0 to imax;
		
		constant jmax: natural := 200; -- 20ms reset high to parrom initialization
		variable j: natural range 0 to jmax;
		
		constant kmax: natural := 2; -- parrom load
		variable k: natural range 0 to kmax;
		-- IP impl.config.vars --- REND

	begin
		if reset='1' then
			-- IP impl.config.asyncrst --- RBEGIN
			stateConfig <= stateConfigInit;

			ackInvSetReg_sig <= '0';
			ackInvGetReg_sig <= '0';
			regVal <= (others => '0');
			ackInvModReg_sig <= '0';

			i2cReadNotWrite <= '0';
			i2cRegaddr <= (others => '0');
			i2cSend <= (others => '0');

			aParrom <= 0;

			ackLiveToConfigSetReg <= '0';

			prepdone := false;
			-- IP impl.config.asyncrst --- REND
			-- IP impl.config.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if stateConfig=stateConfigInit then
				-- IP impl.config.syncrst --- RBEGIN
				ackInvSetReg_sig <= '0';
				ackInvGetReg_sig <= '0';
				regVal <= (others => '0');
				ackInvModReg_sig <= '0';

				aParrom <= 0;
				-- IP impl.config.syncrst --- REND
				-- IP impl.config.syncrst.cust --- INSERT

				if not prepdone then
					-- IP impl.config.init.prep --- IBEGIN
					i := 0;
					-- IP impl.config.init.prep --- IEND

					stateConfig <= stateConfigPrepB;

				elsif reqInvSetReg='1' then
					-- IP impl.config.init.invSetReg --- IBEGIN
					modNotGetSet := false;
					liveNotExt := false;
					
					i2cReadNotWrite <= '0';
					i2cRegaddr <= setRegAddr;
					i2cSend <= x"00" & setRegVal;
					-- IP impl.config.init.invSetReg --- IEND

					stateConfig <= stateConfigXfer;

				elsif reqInvGetReg='1' then
					-- IP impl.config.init.invGetReg --- IBEGIN
					modNotGetSet := false;
					liveNotExt := false;

					i2cReadNotWrite <= '1';
					i2cRegaddr <= getRegAddr;
					-- IP impl.config.init.invGetReg --- IEND

					stateConfig <= stateConfigXfer;

				elsif reqInvModReg='1' then
					-- IP impl.config.init.invModReg --- IBEGIN
					modNotGetSet := true;
					liveNotExt := false;

					i2cReadNotWrite <= '1';
					i2cRegaddr <= modRegAddr;
					-- IP impl.config.init.invModReg --- IEND

					stateConfig <= stateConfigXfer;

				elsif reqLiveToConfigSetReg='1' then
					-- IP impl.config.init.liveSetReg --- IBEGIN
					modNotGetSet := false;
					liveNotExt := true;
					
					i2cReadNotWrite <= '0';
					i2cRegaddr <= liveSetRegAddr;
					i2cSend <= x"00" & liveSetRegVal;
					-- IP impl.config.init.liveSetReg --- IEND

					stateConfig <= stateConfigXfer;
				end if;

			elsif stateConfig=stateConfigPrepA then
				if tkclk='1' then
					if i=imax then
						-- IP impl.config.prepA.done --- IBEGIN
						j := 0;
						-- IP impl.config.prepA.done --- IEND

						stateConfig <= stateConfigPrepD;

					else
						stateConfig <= stateConfigPrepB;
					end if;
				end if;

			elsif stateConfig=stateConfigPrepB then
				if tkclk='0' then
					i := i + 1; -- IP impl.config.prepB.inc --- ILINE

					stateConfig <= stateConfigPrepA;
				end if;

			elsif stateConfig=stateConfigPrepC then
				if tkclk='1' then
					if j=jmax then
						-- IP impl.config.prepC.done --- IBEGIN
						specNotGnr := false;
	
						i2cReadNotWrite <= '0';
	
						-- modification so camera is turned on with delay (no actual spec section for IMX335)
						--aParrom <= a0ParromGnr;
						aParrom <= a0ParromGnr2;
	
						bytecnt := 0;
						
						k := 0;
						-- IP impl.config.prepC.done --- IEND

						stateConfig <= stateConfigLoadA;

					else
						stateConfig <= stateConfigPrepD;
					end if;
				end if;

			elsif stateConfig=stateConfigPrepD then
				if tkclk='0' then
					j := j + 1; -- IP impl.config.prepD.inc --- ILINE

					stateConfig <= stateConfigPrepC;
				end if;

			elsif stateConfig=stateConfigLoadA then
				k := k + 1; -- IP impl.config.loadA.pre --- ILINE

				if k=kmax then
					stateConfig <= stateConfigLoadB;
				end if;

			elsif stateConfig=stateConfigLoadB then
				-- IP impl.config.loadB.pre --- IBEGIN
				bytecnt := bytecnt + 1;

				if bytecnt=4 then
					bytecnt := 0;
				end if;
				-- IP impl.config.loadB.pre --- IEND

				if (bytecnt=1 and drdParrom=x"00") then
					if not specNotGnr then
						-- IP impl.config.loadB.prepSpec --- IBEGIN
						--aParrom <= a0ParromSpec;
						aParrom <= a0ParromSpec2;
						
						specNotGnr := true;

						bytecnt := 0;
						
						k := 0;

						-- modification: use pwupdn to wait
						j := 0;

						--stateConfig <= stateConfigLoadA;
						-- IP impl.config.loadB.prepSpec --- IEND

						stateConfig <= stateConfigPwupdnB;

					else
						prepdone := true; -- IP impl.config.loadB.done --- ILINE

						stateConfig <= stateConfigInit;
					end if;

				else
					aParrom <= aParrom + 1; -- IP impl.config.loadB.inc --- ILINE

					if bytecnt=0 then
						stateConfig <= stateConfigXfer;

					elsif bytecnt=1 then
						-- IP impl.config.loadB.addrmsb --- IBEGIN
						i2cRegaddr(15 downto 8) <= drdParrom;

						k := 0;
						-- IP impl.config.loadB.addrmsb --- IEND

						stateConfig <= stateConfigLoadA;

					elsif bytecnt=2 then
						-- IP impl.config.loadB.addrlsb --- IBEGIN
						i2cRegaddr(7 downto 0) <= drdParrom;

						k := 0;
						-- IP impl.config.loadB.addrlsb --- IEND

						stateConfig <= stateConfigLoadA;

					elsif bytecnt=3 then
						-- IP impl.config.loadB.val --- IBEGIN
						i2cSend <= x"00" & drdParrom;

						k := 0;
						-- IP impl.config.loadB.val --- IEND

						stateConfig <= stateConfigLoadA;
					end if;
				end if;

			elsif stateConfig=stateConfigXfer then
				if dneI2c='1' then
					stateConfig <= stateConfigStep;
				end if;

			elsif stateConfig=stateConfigStep then
				if i2cReadNotWrite='0' then
					if not prepdone then
						-- IP impl.config.step.prep --- IBEGIN
						bytecnt := 0;

						k := 0;
						-- IP impl.config.step.prep --- IEND

						stateConfig <= stateConfigLoadA;

					else
						-- IP impl.config.step.cmdDone --- IBEGIN
						if not modNotGetSet then
							if not liveNotExt then
								ackInvSetReg_sig <= '1';
							else
								ackLiveToConfigSetReg <= '1';
							end if;
						else
							ackInvModReg_sig <= '1';
						end if;
						-- IP impl.config.step.cmdDone --- IEND

						stateConfig <= stateConfigInv;
					end if;

				else
					if not modNotGetSet then
						-- IP impl.config.step.get --- IBEGIN
						regVal <= i2cRecv(7 downto 0);

						ackInvGetReg_sig <= '1';
						-- IP impl.config.step.get --- IEND

						stateConfig <= stateConfigInv;

					else
						-- IP impl.config.step.mod --- IBEGIN
						i2cReadNotWrite <= '0';
						i2cSend <= x"00" & ((i2cRecv(7 downto 0) and (not modRegMask)) or (modRegVal and modRegMask));
						-- IP impl.config.step.mod --- IEND

						stateConfig <= stateConfigXfer;
					end if;
				end if;

			elsif stateConfig=stateConfigPwupdnA then
				if tkclk='1' then
					if j=jmax then
						stateConfig <= stateConfigLoadA;

					else
						stateConfig <= stateConfigPwupdnB;
					end if;
				end if;

			elsif stateConfig=stateConfigPwupdnB then
				if tkclk='0' then
					j := j + 1; -- IP impl.config.pwupdnB.inc --- ILINE

					stateConfig <= stateConfigPwupdnA;
				end if;

			elsif stateConfig=stateConfigInv then
				if ((reqInvSetReg='0' and ackInvSetReg_sig='1') or (reqInvGetReg='0' and ackInvGetReg_sig='1') or (reqInvModReg='0' and ackInvModReg_sig='1') or (reqLiveToConfigSetReg='0' and ackLiveToConfigSetReg='1')) then
					-- IP impl.config.inv.reset --- IBEGIN
					ackInvSetReg_sig <= '0';
					ackInvGetReg_sig <= '0';
					ackInvModReg_sig <= '0';
					ackLiveToConfigSetReg <= '0';
					-- IP impl.config.inv.reset --- IEND

					stateConfig <= stateConfigInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.config.rising --- END

	------------------------------------------------------------------------
	-- implementation: MIPI RX core configuration (corecfg)
	------------------------------------------------------------------------

	-- IP impl.corecfg.wiring --- BEGIN
	ackInvGetCorereg <= ackInvGetCorereg_sig;
	getCoreregVal <= getCoreregVal_sig;
	ackInvSetCorereg <= ackInvSetCorereg_sig;

	corecfgAXIL_arvalid <= '1' when stateCorecfg=stateCorecfgReadA else '0';

	corecfgAXIL_rready <= '1' when (stateCorecfg=stateCorecfgReadA or stateCorecfg=stateCorecfgReadB) else '0';

	corecfgAXIL_awvalid <= '1' when stateCorecfg=stateCorecfgWriteA else '0';

	corecfgAXIL_wvalid <= '1' when (stateCorecfg=stateCorecfgWriteA or stateCorecfg=stateCorecfgWriteB) else '0';

	corecfgAXIL_bready <= '1' when stateCorecfg=stateCorecfgWriteC else '0';
	-- IP impl.corecfg.wiring --- END

	-- IP impl.corecfg.wiring.cust --- LINE

	-- IP impl.corecfg.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.corecfg.vars --- BEGIN
		-- IP impl.corecfg.vars --- END

	begin
		if reset='1' then
			-- IP impl.corecfg.asyncrst --- BEGIN
			stateCorecfg <= stateCorecfgInit;
			ackInvGetCorereg_sig <= '0';
			getCoreregVal_sig <= (others => '0');
			ackInvSetCorereg_sig <= '0';
			corecfgAXIL_araddr <= (others => '0');
			corecfgAXIL_awaddr <= (others => '0');
			corecfgAXIL_wdata <= (others => '0');

			-- IP impl.corecfg.asyncrst --- END
			-- IP impl.corecfg.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if stateCorecfg=stateCorecfgInit then
				if reqInvGetCorereg='1' then
					-- IP impl.corecfg.init.invGetCorereg --- IBEGIN
					corecfgAXIL_araddr <= getCoreregAddr(5 downto 0);
					-- IP impl.corecfg.init.invGetCorereg --- IEND

					stateCorecfg <= stateCorecfgReadA;

				elsif reqInvSetCorereg='1' then
					-- IP impl.corecfg.init.invSetCorereg --- IBEGIN
					corecfgAXIL_awaddr <= setCoreregAddr(5 downto 0);
					corecfgAXIL_wdata <= setCoreregVal;
					-- IP impl.corecfg.init.invSetCorereg --- IEND

					stateCorecfg <= stateCorecfgWriteA;

				else
					-- IP impl.corecfg.syncrst --- RBEGIN
					ackInvGetCorereg_sig <= '0';
					ackInvSetCorereg_sig <= '0';
					corecfgAXIL_araddr <= (others => '0');
					corecfgAXIL_awaddr <= (others => '0');
					corecfgAXIL_wdata <= (others => '0');

					-- IP impl.corecfg.syncrst --- REND
					-- IP impl.corecfg.syncrst.cust --- INSERT

					stateCorecfg <= stateCorecfgInit;
				end if;

			elsif stateCorecfg=stateCorecfgReadA then
				if corecfgAXIL_arready='1' then
					if corecfgAXIL_rvalid='1' then
						getCoreregVal_sig <= corecfgAXIL_rdata; -- IP impl.corecfg.readA.copy --- ILINE

						stateCorecfg <= stateCorecfgReadC;

					else
						stateCorecfg <= stateCorecfgReadB;
					end if;
				end if;

			elsif stateCorecfg=stateCorecfgReadB then
				if corecfgAXIL_rvalid='1' then
					getCoreregVal_sig <= corecfgAXIL_rdata; -- IP impl.corecfg.readB.copy --- ILINE

					stateCorecfg <= stateCorecfgReadC;
				end if;

			elsif stateCorecfg=stateCorecfgReadC then
				ackInvGetCorereg_sig <= '1'; -- IP impl.corecfg.readC --- ILINE

				stateCorecfg <= stateCorecfgInv;

			elsif stateCorecfg=stateCorecfgWriteA then
				if corecfgAXIL_awready='1' then
					if corecfgAXIL_wready='1' then
						stateCorecfg <= stateCorecfgWriteC;

					else
						stateCorecfg <= stateCorecfgWriteB;
					end if;
				end if;

			elsif stateCorecfg=stateCorecfgWriteB then
				if corecfgAXIL_wready='1' then
					stateCorecfg <= stateCorecfgWriteC;
				end if;

			elsif stateCorecfg=stateCorecfgWriteC then
				if corecfgAXIL_bvalid='1' then
					ackInvSetCorereg_sig <= '1'; -- IP impl.corecfg.writeC --- ILINE

					stateCorecfg <= stateCorecfgInv;
				end if;

			elsif stateCorecfg=stateCorecfgInv then
				if ((reqInvGetCorereg='0' and ackInvGetCorereg_sig='1') or (reqInvSetCorereg='0' and ackInvSetCorereg_sig='1')) then
					-- IP impl.corecfg.inv.reset --- IBEGIN
					ackInvGetCorereg_sig <= '0';
					ackInvSetCorereg_sig <= '0';
					-- IP impl.corecfg.inv.reset --- IEND

					stateCorecfg <= stateCorecfgInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.corecfg.rising --- END

	------------------------------------------------------------------------
	-- implementation: gearing from quad-RAW12 to dual-RAW12 (gear)
	------------------------------------------------------------------------

	-- IP impl.gear.wiring --- BEGIN
	-- IP impl.gear.wiring --- END

	-- IP impl.gear.wiring.cust --- LINE

	-- IP impl.gear.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.gear.vars --- RBEGIN
		variable video_out_tdata_next: std_logic_vector(23 downto 0);
		-- IP impl.gear.vars --- REND

	begin
		if reset='1' then
			-- IP impl.gear.asyncrst --- BEGIN
			enEgr <= '0';
			pixrxclk_mclk <= (others => '0');
			video_out_tvalid <= '0';
			video_out_tdata <= (others => '0');
			video_out_tlast <= '1';
			video_out_tuser <= (others => '0');

			-- IP impl.gear.asyncrst --- END
			-- IP impl.gear.asyncrst.cust --- IBEGIN
			video_out_tdata_next := (others => '0');
			-- IP impl.gear.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			-- IP impl.gear --- IBEGIN
			enEgr <= not enEgr;

			if enEgr='1' then
				video_out_tvalid <= video_out_x2_tvalid;
				video_out_tdata_next := video_out_x2_tdata(24+23 downto 24+0); -- by design, video_out_x2_tdata should not change when sampled next
				video_out_tdata <= video_out_x2_tdata(23 downto 0);
				if video_out_x2_tlast='0' then
					video_out_tlast <= '0';
				end if;
				video_out_tuser <= video_out_x2_tuser;
			else
				video_out_tdata <= video_out_tdata_next;
				if video_out_x2_tlast='1' then
					video_out_tlast <= '1';
				end if;
			end if;
			-- IP impl.gear --- IEND
		end if;
	end process;
	-- IP impl.gear.rising --- END

	------------------------------------------------------------------------
	-- implementation: live streaming operation (live)
	------------------------------------------------------------------------

	-- IP impl.live.wiring --- RBEGIN

	-- liveIxTExp 0 | 1 | 2 | 3 | 4 |
	-- ixTExp_lcl   2   3   4   0   1

	resetn <= not reset;
	resetnPixrxclk <= not resetPixrxclk;

	vsync <= vsync_sig when synthNotLive='1'
				else '0' when stateLive=stateLivePre or stateLive=stateLiveRun else '1';

	ixTExp <= std_logic_vector(to_unsigned(ixTExp_sig, 4)) when synthNotLive='1'
				else std_logic_vector(to_unsigned(liveIxTExp, 4));

	toVideoinAXIS_tvalid <= toVideoinAXIS_tvalid_sig when synthNotLive='1'
				else '1' when stateLive=stateLiveRun and video_out_tvalid='1' and video_out_tuser=tixVFormat else '0';
	toVideoinAXIS_tdata <= toVideoinAXIS_tdata_sig when synthNotLive='1'
				else video_out_tdata;
	toVideoinAXIS_tlast <= toVideoinAXIS_tlast_sig when synthNotLive='1'
				else '0' when stateLive=stateLiveRun and video_out_tlast='0' else '1';

	rowRawLast <= to_integer(unsigned(NRowRaw) - 1);

	reqLiveToConfigSetReg <= '1' when stateLive=stateLiveUpdTExpB else '0';
	-- IP impl.live.wiring --- REND

	-- IP impl.live.wiring.cust --- LINE

	-- IP impl.live.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.live.vars --- RBEGIN
		variable rowRaw_lcl: natural range 0 to 2999;

		variable ixTExp_lcl: natural range 0 to ixTExpLast;
		variable i: natural range 0 to 1;
		-- IP impl.live.vars --- REND

	begin
		if reset='1' then
			-- IP impl.live.asyncrst --- BEGIN
			stateLive <= stateLiveInit;
			liveIxTExp <= 0;
			liveSetRegAddr <= (others => '0');
			liveSetRegVal <= (others => '0');
			video_out_tlastm1 <= '1';

			-- IP impl.live.asyncrst --- END
			-- IP impl.live.asyncrst.cust --- IBEGIN
			rowRaw_lcl := 0;

			ixTExp_lcl := 1;
			i := 0;
			-- IP impl.live.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			video_out_tlastm1 <= video_out_tlast; -- IP impl.live.pre --- ILINE

			if stateLive=stateLiveInit then
				-- IP impl.live.syncrst --- RBEGIN
				liveSetRegAddr <= (others => '0');
				liveSetRegVal <= (others => '0');
				-- IP impl.live.syncrst --- REND
				-- IP impl.live.syncrst.cust --- IBEGIN
				rowRaw_lcl := 0;

				i := 0;
				-- IP impl.live.syncrst.cust --- IEND

				if (video_out_tvalid='1' and video_out_tuser/=tixVFormat) then
					stateLive <= stateLivePre;

				else
					stateLive <= stateLiveInit;
				end if;

			elsif stateLive=stateLivePre then
				if (video_out_tlastm1='0' and video_out_tlast='1') then
					if rowRaw_lcl=rowRawStart then
						rowRaw_lcl := 0; -- IP impl.live.pre.done --- ILINE

						stateLive <= stateLiveRun;

					else
						rowRaw_lcl := rowRaw_lcl + 1; -- IP impl.live.pre.nextRow --- ILINE

						stateLive <= stateLivePre;
					end if;
				end if;

			elsif stateLive=stateLiveRun then
				if (video_out_tlastm1='0' and video_out_tlast='1') then
					if rowRaw_lcl=rowRawLast then
						rowRaw_lcl := 0; -- IP impl.live.run.TExpDone --- ILINE

						if hdrNotFix='0' then
							stateLive <= stateLiveInit;

						else
							-- IP impl.live.run.nextTExp --- IBEGIN
							if ixTExp_lcl=ixTExpLast then
								ixTExp_lcl := 0;
							else
								ixTExp_lcl := ixTExp_lcl + 1;
							end if;

							i := 0;
							-- IP impl.live.run.nextTExp --- IEND

							stateLive <= stateLiveUpdTExpA;
						end if;

					else
						rowRaw_lcl := rowRaw_lcl + 1; -- IP impl.live.run.nextRow --- ILINE

						stateLive <= stateLiveRun;
					end if;
				end if;

			elsif stateLive=stateLiveUpdTExpA then
				-- IP impl.live.updTExpA --- IBEGIN
				if i=0 then
					liveSetRegAddr <= regShr0_0;
				else
					liveSetRegAddr <= regShr0_1;
				end if;

				case ixTExp_lcl is
					when 0 =>
						liveSetRegVal <= TExp0(i*8+7 downto i*8);
					when 1 =>						
						liveSetRegVal <= TExp1(i*8+7 downto i*8);
					when 2 =>						
						liveSetRegVal <= TExp2(i*8+7 downto i*8);
					when 3 =>						
						liveSetRegVal <= TExp3(i*8+7 downto i*8);
					when 4 =>						
						liveSetRegVal <= TExp4(i*8+7 downto i*8);
					when others =>						
				end case;
				-- IP impl.live.updTExpA --- IEND

				stateLive <= stateLiveUpdTExpB;

			elsif stateLive=stateLiveUpdTExpB then
				if ackLiveToConfigSetReg='1' then
					if i=1 then
						-- IP impl.live.updTExpB.done --- IBEGIN
						if ixTExp_lcl=0 then
							liveIxTExp <= ixTExpLast;
						else
							liveIxTexp <= ixTExp_lcl - 1;
						end if;
						-- IP impl.live.updTExpB.done --- IEND

						stateLive <= stateLiveInit;

					else
						i := i + 1; -- IP impl.live.updTExpB.nextWord --- ILINE

						stateLive <= stateLiveUpdTExpA;
					end if;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.live.rising --- END

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	ackInvConfig <= ackInvConfig_sig;
	ackInvConfigSynth <= ackInvConfigSynth_sig;
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- LINE

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- BEGIN
		-- IP impl.op.vars --- END

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- BEGIN
			stateOp <= stateOpInit;
			ackInvConfig_sig <= '0';
			hdrNotFix <= '0';
			synthNotLive <= '0';
			ackInvConfigSynth_sig <= '0';
			tixVSynthmode <= (others => '0');
			TFramepad <= (others => '0');
			TLinepad <= (others => '0');
			tixVFormat <= tixVFormatRaw12(5 downto 0);

			-- IP impl.op.asyncrst --- END
			-- IP impl.op.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateOp=stateOpInit or (stateOp/=stateOpInv and (reqInvConfig='1' or reqInvConfigSynth='1'))) then
				if reqInvConfig='1' then
					-- IP impl.op.init.invConfig --- IBEGIN
					if configHdrNotFix=tru8 then
						hdrNotFix <= '1';
					else
						hdrNotFix <= '0';
					end if;
					if configSynthNotLive=tru8 then
						synthNotLive <= '1';
					else
						synthNotLive <= '0';
					end if;

					ackInvConfig_sig <= '1';
					ackInvConfigSynth_sig <= '0';
					-- IP impl.op.init.invConfig --- IEND

					stateOp <= stateOpInv;

				elsif reqInvConfigSynth='1' then
					-- IP impl.op.init.invConfigSynth --- IBEGIN
					tixVSynthmode <= configSynthTixVSynthmode;
					TFramepad <= configSynthTFramepad;
					TLinepad <= configSynthTLinepad;

					ackInvConfig_sig <= '0';
					ackInvConfigSynth_sig <= '1';
					-- IP impl.op.init.invConfigSynth --- IEND

					stateOp <= stateOpInv;

				else
					-- IP impl.op.syncrst --- RBEGIN
					ackInvConfig_sig <= '0';
					ackInvConfigSynth_sig <= '0';
					tixVFormat <= tixVFormatRaw12(5 downto 0);

					-- IP impl.op.syncrst --- REND
					-- IP impl.op.syncrst.cust --- INSERT

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpInv then
				if ((reqInvConfig='0' and ackInvConfig_sig='1') or (reqInvConfigSynth='0' and ackInvConfigSynth_sig='1')) then
					-- IP impl.op.inv.reset --- IBEGIN
					ackInvConfig_sig <= '0';
					ackInvConfigSynth_sig <= '0';
					-- IP impl.op.inv.reset --- IEND

					stateOp <= stateOpInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: forwarding of raw pixel data (rxfwd)
	------------------------------------------------------------------------

	-- IP impl.rxfwd.wiring --- BEGIN
	hsync_vc0n <= not hsync_vc0;
	-- IP impl.rxfwd.wiring --- END

	-- IP impl.rxfwd.wiring.cust --- LINE

	-- IP impl.rxfwd.rising --- BEGIN
	process (resetPixrxclk, pixrxclk)
		-- IP impl.rxfwd.vars --- BEGIN
		-- IP impl.rxfwd.vars --- END

	begin
		if resetPixrxclk='1' then
			-- IP impl.rxfwd.asyncrst --- BEGIN
			pixel_datap1 <= (others => '0');
			pixel_data_validp1 <= '0';
			datatypep1 <= (others => '0');

			-- IP impl.rxfwd.asyncrst --- END
			-- IP impl.rxfwd.asyncrst.cust --- INSERT

		elsif rising_edge(pixrxclk) then
			-- IP impl.rxfwd --- IBEGIN
			pixel_data_validp1 <= pixel_data_valid;
			pixel_datap1 <= pixel_data;
			datatypep1 <= datatype;
			-- IP impl.rxfwd --- IEND
		end if;
	end process;
	-- IP impl.rxfwd.rising --- END

	------------------------------------------------------------------------
	-- implementation: frame synthesis operation (synth)
	------------------------------------------------------------------------

	-- IP impl.synth.wiring --- BEGIN
	toVideoinAXIS_tlast_sig <= '0' when (stateSynth=stateSynthRgb or stateSynth=stateSynthHdr or stateSynth=stateSynthChk) else '1';

	vsync_sig <= '0' when (stateSynth=stateSynthRgb or stateSynth=stateSynthHdr or stateSynth=stateSynthChk
				 or stateSynth=stateSynthEol or stateSynth=stateSynthEofA) else '1';
	-- IP impl.synth.wiring --- END

	-- IP impl.synth.wiring.cust --- LINE

	-- IP impl.synth.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.synth.vars --- RBEGIN
		variable i: natural range 0 to 255; -- linepad counter
		variable j: natural range 0 to 65535; -- framepad counter

		variable r_lcl, g0_lcl, g1_lcl, b_lcl: natural range 0 to 4095;
		variable rsh, gsh, bsh: natural range 0 to 2;

		variable w0, w1: std_logic_vector(23 downto 0);

		-- chk related
		constant NSqr: natural := 10;
		variable rowchk: natural range 0 to NSqr-1;
		variable colchk: natural range 0 to NSqr-1;
		variable whtNotBlk0: boolean;
		variable whtNotBlk: boolean;
		variable blk: unsigned(11 downto 0);
		variable wht: unsigned(11 downto 0);
		-- IP impl.synth.vars --- REND

	begin
		if reset='1' then
			-- IP impl.synth.asyncrst --- RBEGIN
			stateSynth <= stateSynthInit;

			toVideoinAXIS_tvalid_sig <= '0';
			toVideoinAXIS_tdata_sig <= (others => '0');

			ixTExp_sig <= 0;

			row <= (others => '0');
			col <= (others => '0');

			r_lcl := 0;
			g0_lcl := 0;
			g1_lcl := 0;
			b_lcl := 0;

			rsh := 0;
			gsh := 0;
			bsh := 0;

			w0 := (others => '0');
			w1 := (others => '0');

			rowchk := 0;
			colchk := 0;
			whtNotBlk0 := false;
			whtNotBlk := false;
			blk := (others => '0');
			wht := (others => '0');
			-- IP impl.synth.asyncrst --- REND
			-- IP impl.synth.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateSynth=stateSynthInit or rng='0') then
				-- IP impl.synth.syncrst --- RBEGIN
				toVideoinAXIS_tvalid_sig <= '0';
				toVideoinAXIS_tdata_sig <= (others => '0');

				ixTExp_sig <= 0;

				row <= (others => '0');
				col <= (others => '0');
				-- IP impl.synth.syncrst --- REND
				-- IP impl.synth.syncrst.cust --- INSERT

				if rng='0' then
					stateSynth <= stateSynthInit;

				else
					if tixVSynthmode=tixVSynthmodeRgb then
						-- IP impl.synth.init.startRgb --- IBEGIN
						r_lcl := 0;
						g0_lcl := 2048;
						g1_lcl := 2048;
						b_lcl := 4095;
						-- IP impl.synth.init.startRgb --- IEND

						stateSynth <= stateSynthRgb;

					elsif tixVSynthmode=tixVSynthmodeHdr then
						-- IP impl.synth.init.startHdr --- IBEGIN
						r_lcl := 0;
						g0_lcl := 2048;
						g1_lcl := 2048;
						b_lcl := 4095;
			
						rsh := 0;
						gsh := 1;
						bsh := 2;
						-- IP impl.synth.init.startHdr --- IEND

						stateSynth <= stateSynthHdr;

					elsif tixVSynthmode=tixVSynthmodeChk then
						-- IP impl.synth.init.startChk --- IBEGIN
						whtNotBlk0 := false;
						whtNotBlk := false;
						rowchk := 0;
						colchk := 0;
						blk := (others => '0');
						wht := (others => '1');
						-- IP impl.synth.init.startChk --- IEND

						stateSynth <= stateSynthChk;
					end if;
				end if;

			elsif stateSynth=stateSynthRgb then
				-- IP impl.synth.rgb.pre --- IBEGIN
				-- pattern I: non HDR rgb ramp, r0..4095, g2048..2047, b4095..0
				toVideoinAXIS_tvalid_sig <= '1';

				if row(0)='0' then
					toVideoinAXIS_tdata_sig <= std_logic_vector(to_unsigned(r_lcl, 12)) & std_logic_vector(to_unsigned(g0_lcl, 12));
				else
					toVideoinAXIS_tdata_sig <= std_logic_vector(to_unsigned(g1_lcl, 12)) & std_logic_vector(to_unsigned(b_lcl, 12));
				end if;
				-- IP impl.synth.rgb.pre --- IEND

				if col=unsigned(NCol)-1 then
					i := 0; -- IP impl.synth.rgb.rowDone --- ILINE

					stateSynth <= stateSynthEol;

				else
					-- IP impl.synth.rgb.nextCol --- IBEGIN
					col <= col + 1;

					if row(0)='0' then
						if r_lcl=4095 then
							r_lcl := 0;
						else
							r_lcl := r_lcl + 1;
						end if;
						if g0_lcl=4095 then
							g0_lcl := 0;
						else
							g0_lcl := g0_lcl + 1;
						end if;
					else
						if b_lcl=0 then
							b_lcl := 4095;
						else
							b_lcl := b_lcl - 1;
						end if;
						if g1_lcl=4095 then
							g1_lcl := 0;
						else
							g1_lcl := g1_lcl + 1;
						end if;
					end if;
					-- IP impl.synth.rgb.nextCol --- IEND

					stateSynth <= stateSynthRgb;
				end if;

			elsif stateSynth=stateSynthHdr then
				-- IP impl.synth.hdr.pre --- IBEGIN
				-- pattern II: HDR rgb ramp where per line central 16 of 24 bits are shifted 0-2-4-0-2-4 bits
				toVideoinAXIS_tvalid_sig <= '1';

				if row(0)='0' then
					w1 := (others => '0');
					w1(2*rsh+4+11 downto 2*rsh+4) := std_logic_vector(to_unsigned(r_lcl, 12));

					w0 := (others => '0');
					w0(2*gsh+4+11 downto 2*gsh+4) := std_logic_vector(to_unsigned(g0_lcl, 12));
				else
					w1 := (others => '0');
					w1(2*gsh+4+11 downto 2*gsh+4) := std_logic_vector(to_unsigned(g1_lcl, 12));

					w0 := (others => '0');
					w0(2*bsh+4+11 downto 2*bsh+4) := std_logic_vector(to_unsigned(b_lcl, 12));
				end if;

				toVideoinAXIS_tdata_sig(23 downto 12) <= w1(3*ixTExp_sig+11 downto 3*ixTExp_sig);
				toVideoinAXIS_tdata_sig(11 downto 0) <= w0(3*ixTExp_sig+11 downto 3*ixTExp_sig);
				-- IP impl.synth.hdr.pre --- IEND

				if col=unsigned(NCol)-1 then
					i := 0; -- IP impl.synth.hdr.rowDone --- ILINE

					stateSynth <= stateSynthEol;

				else
					-- IP impl.synth.hdr.nextCol --- IBEGIN
					col <= col + 1;

					if row(0)='0' then
						if r_lcl=4095 then
							r_lcl := 0;
						else
							r_lcl := r_lcl + 1;
						end if;
						if g0_lcl=4095 then
							g0_lcl := 0;
						else
							g0_lcl := g0_lcl + 1;
						end if;
					else
						if b_lcl=0 then
							b_lcl := 4095;
						else
							b_lcl := b_lcl - 1;
						end if;
						if g1_lcl=4095 then
							g1_lcl := 0;
						else
							g1_lcl := g1_lcl + 1;
						end if;
					end if;
					-- IP impl.synth.hdr.nextCol --- IEND

					stateSynth <= stateSynthHdr;
				end if;

			elsif stateSynth=stateSynthChk then
				-- IP impl.synth.chk.pre --- IBEGIN
				-- pattern III: grayscale checkerboard with contrast from 0 vs. 4095 via 1024 vs. 4095-1024 via 1024+512 via 1024+512+256 ... up to 2047 vs. 2048 (11 steps)
				toVideoinAXIS_tvalid_sig <= '1';

				if not whtNotBlk then
					toVideoinAXIS_tdata_sig <= std_logic_vector(blk) & std_logic_vector(blk);
				else
					toVideoinAXIS_tdata_sig <= std_logic_vector(wht) & std_logic_vector(wht);
				end if;
				-- IP impl.synth.chk.pre --- IEND

				if col=unsigned(NCol)-1 then
					i := 0; -- IP impl.synth.chk.rowDone --- ILINE

					stateSynth <= stateSynthEol;

				else
					-- IP impl.synth.chk.nextCol --- IBEGIN
					col <= col + 1;

					if colchk=NSqr-1 then
						colchk := 0;
						whtNotBlk := not whtNotBlk;
					else
						colchk := colchk + 1;
					end if;
					-- IP impl.synth.chk.nextCol --- IEND

					stateSynth <= stateSynthChk;
				end if;

			elsif stateSynth=stateSynthEol then
				toVideoinAXIS_tvalid_sig <= '0'; -- IP impl.synth.eol.pre --- ILINE

				if i=to_integer(unsigned(Tlinepad)) then
					if row=unsigned(NRowRaw)-1 then
						j := 0; -- IP impl.synth.eol.done --- ILINE

						stateSynth <= stateSynthEofA;

					else
						-- IP impl.synth.eol.nextRow --- IBEGIN
						row <= row + 1;
						col <= (others => '0');
						-- IP impl.synth.eol.nextRow --- IEND

						if tixVSynthmode=tixVSynthmodeRgb then
							-- IP impl.synth.eol.restartRgb --- IBEGIN
							if row(0)='1' then
								r_lcl := 0;
								g0_lcl := 2048;
								g1_lcl := 2048;
								b_lcl := 4095;
							end if;
							-- IP impl.synth.eol.restartRgb --- IEND

							stateSynth <= stateSynthRgb;

						elsif tixVSynthmode=tixVSynthmodeHdr then
							-- IP impl.synth.eol.restartHdr --- IBEGIN
							if row(0)='1' then
								r_lcl := 0;
								g0_lcl := 2048;
								g1_lcl := 2048;
								b_lcl := 4095;

								if rsh=2 then
									rsh := 0;
								else
									rsh := rsh + 1;
								end if;
								if gsh=2 then
									gsh := 0;
								else
									gsh := gsh + 1;
								end if;
								if bsh=2 then
									bsh := 0;
								else
									bsh := bsh + 1;
								end if;
							end if;
							-- IP impl.synth.eol.restartHdr --- IEND

							stateSynth <= stateSynthHdr;

						elsif tixVSynthmode=tixVSynthmodeChk then
							-- IP impl.synth.eol.restartChk --- IBEGIN
							if rowchk=NSqr-1 then
								rowchk := 0;

								whtNotBlk0 := not whtNotBlk0;

								if blk(0)='1' then
									blk := (others => '0');
									wht := (others => '1');
								else
									-- delta 4095, 2047, 1023, ...,  1
									blk(10 downto 0) := "1" & blk(10 downto 1);
									wht(10 downto 0) := "0" & wht(10 downto 1);
								end if;
				
							else
								rowchk := rowchk + 1;
							end if;

							colchk := 0;

							whtNotBlk := whtNotBlk0;
							-- IP impl.synth.eol.restartChk --- IEND

							stateSynth <= stateSynthChk;
						end if;
					end if;

				else
					i := i + 1; -- IP impl.synth.eol.inc --- ILINE

					stateSynth <= stateSynthEol;
				end if;

			elsif stateSynth=stateSynthEofA then
				if j=to_integer(unsigned(TFramepad(15 downto 1))) then
					-- IP impl.synth.eofA.done --- IBEGIN
					if hdrNotFix='1' then
						if ixTExp_sig=ixTExpLast then -- require ixTExp to increment before vsync goes down
							ixTExp_sig <= 0;
						else
							ixTExp_sig <= ixTExp_sig + 1;
						end if;
					end if;
					
					j := 0;
					-- IP impl.synth.eofA.done --- IEND

					stateSynth <= stateSynthEofB;

				else
					j := j + 1; -- IP impl.synth.eofA.inc --- ILINE

					stateSynth <= stateSynthEofA;
				end if;

			elsif stateSynth=stateSynthEofB then
				if j=to_integer(unsigned(TFramepad(15 downto 1))) then
					-- IP impl.synth.eofB.done --- IBEGIN
					row <= (others => '0');
					col <= (others => '0');
					-- IP impl.synth.eofB.done --- IEND

					if tixVSynthmode=tixVSynthmodeRgb then
						-- IP impl.synth.eofB.restartRgb --- IBEGIN
						r_lcl := 0;
						g0_lcl := 2048;
						g1_lcl := 2048;
						b_lcl := 4095;
						-- IP impl.synth.eofB.restartRgb --- IEND

						stateSynth <= stateSynthRgb;

					elsif tixVSynthmode=tixVSynthmodeHdr then
						-- IP impl.synth.eofB.restartHdr --- IBEGIN
						r_lcl := 0;
						g0_lcl := 2048;
						g1_lcl := 2048;
						b_lcl := 4095;
			
						rsh := 0;
						gsh := 1;
						bsh := 2;
						-- IP impl.synth.eofB.restartHdr --- IEND

						stateSynth <= stateSynthHdr;

					elsif tixVSynthmode=tixVSynthmodeChk then
						-- IP impl.synth.eofB.restartChk --- IBEGIN
						whtNotBlk0 := false;
						whtNotBlk := false;
						rowchk := 0;
						colchk := 0;
						blk := (others => '0');
						wht := (others => '1');
						-- IP impl.synth.eofB.restartChk --- IEND

						stateSynth <= stateSynthChk;
					end if;

				else
					j := j + 1; -- IP impl.synth.eofB.inc --- ILINE

					stateSynth <= stateSynthEofB;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.synth.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- IBEGIN
	mipiAXIS_dbg(0) <= pixel_data_valid;
	mipiAXIS_dbg(1) <= '1' when datatype=tixVFormatRaw12(5 downto 0) else '0';
	mipiAXIS_dbg(2) <= datatype(0);
	mipiAXIS_dbg(3) <= hsync_vc0n;

	video_out_dbg(0) <= video_out_tvalid;
	video_out_dbg(1) <= '1' when video_out_tuser(5 downto 0)=tixVFormatRaw12(5 downto 0) else '0';
	video_out_dbg(2) <= video_out_tuser(0);
	video_out_dbg(3) <= video_out_tlast;

	mipirx_RESET_N <= resetn;
	mipirx_RST0_N <= resetnPixrxclk;

	mipirx_ERR_CONTROL <= mipirx_ERR_CONTROL_LAN3 & mipirx_ERR_CONTROL_LAN2 & mipirx_ERR_CONTROL_LAN1 & mipirx_ERR_CONTROL_LAN0;
	mipirx_ERR_ESC <= mipirx_ERR_ESC_LAN3 & mipirx_ERR_ESC_LAN2 & mipirx_ERR_ESC_LAN1 & mipirx_ERR_ESC_LAN0;
	mipirx_ERR_SOT_SYNC_HS <= mipirx_ERR_SOT_SYNC_HS_LAN3 & mipirx_ERR_SOT_SYNC_HS_LAN2 & mipirx_ERR_SOT_SYNC_HS_LAN1 & mipirx_ERR_SOT_SYNC_HS_LAN0; -- eliminated
	mipirx_ESC_CLK <= mipirx_ESC_CLK_LAN3 & mipirx_ESC_CLK_LAN2 & mipirx_ESC_CLK_LAN1 & mipirx_ESC_CLK_LAN0; -- eliminated
	mipirx_RX_SKEW_CAL_HS <= mipirx_RX_SKEW_CAL_HS_LAN3 & mipirx_RX_SKEW_CAL_HS_LAN2 & mipirx_RX_SKEW_CAL_HS_LAN1 & mipirx_RX_SKEW_CAL_HS_LAN0;
	mipirx_RX_SYNC_HS <= mipirx_RX_SYNC_HS_LAN3 & mipirx_RX_SYNC_HS_LAN2 & mipirx_RX_SYNC_HS_LAN1 & mipirx_RX_SYNC_HS_LAN0; -- eliminated
	mipirx_RX_ULPS_ACTIVE_NOT <= mipirx_RX_ULPS_ACTIVE_NOT_LAN3 & mipirx_RX_ULPS_ACTIVE_NOT_LAN2 & mipirx_RX_ULPS_ACTIVE_NOT_LAN1 & mipirx_RX_ULPS_ACTIVE_NOT_LAN0;
	mipirx_RX_ULPS_ESC <= mipirx_RX_ULPS_ESC_LAN3 & mipirx_RX_ULPS_ESC_LAN2 & mipirx_RX_ULPS_ESC_LAN1 & mipirx_RX_ULPS_ESC_LAN0;

	mipirx_RX_VALID_HS_LAN0_sig <= mipirx_RX_VALID_HS_LAN0 & mipirx_RX_VALID_HS_LAN0; -- all these are eliminated
	mipirx_RX_VALID_HS_LAN1_sig <= mipirx_RX_VALID_HS_LAN1 & mipirx_RX_VALID_HS_LAN1;
	mipirx_RX_VALID_HS_LAN2_sig <= mipirx_RX_VALID_HS_LAN2 & mipirx_RX_VALID_HS_LAN2;
	mipirx_RX_VALID_HS_LAN3_sig <= mipirx_RX_VALID_HS_LAN3 & mipirx_RX_VALID_HS_LAN3;

	mipirx_RX_ULPS_CLK_NOT_sig(0) <= mipirx_RX_ULPS_CLK_NOT;
	mipirx_RX_ULPS_ACTIVE_CLK_NOT_sig(0) <= mipirx_RX_ULPS_ACTIVE_CLK_NOT;
	
	mipirx_STOPSTATE <= mipirx_STOPSTATE_LAN3 & mipirx_STOPSTATE_LAN2 & mipirx_STOPSTATE_LAN1 & mipirx_STOPSTATE_LAN0;

	datatype_dbg <= datatype;
	-- IP impl.oth.cust --- IEND

end Rtl;


-- file Corner_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Corner_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Corner_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		vsync: in std_logic;
		NRow: in std_logic_vector(10 downto 0);
		NCol: in std_logic_vector(10 downto 0);

		grayFromVideoinAXIS_tready: out std_logic;
		grayFromVideoinAXIS_tvalid: in std_logic;
		grayFromVideoinAXIS_tdata: in std_logic_vector(71 downto 0);
		grayFromVideoinAXIS_tlast: in std_logic;

		reqInvAcquire: in std_logic;
		ackInvAcquire: out std_logic;

		reqInvConfig: in std_logic;
		ackInvConfig: out std_logic;

		configLinNotLog: in std_logic_vector(7 downto 0);
		configThd: in std_logic_vector(7 downto 0);
		configRow0: in std_logic_vector(15 downto 0);
		configRow1: in std_logic_vector(15 downto 0);
		configCol0: in std_logic_vector(15 downto 0);
		configCol1: in std_logic_vector(15 downto 0);

		getInfoTixVState: out std_logic_vector(7 downto 0);
		getInfoTkst: out std_logic_vector(31 downto 0);
		getInfoScoreMin: out std_logic_vector(7 downto 0);
		getInfoScoreMax: out std_logic_vector(7 downto 0);

		reqInvSet: in std_logic;
		ackInvSet: out std_logic;

		setRng: in std_logic_vector(7 downto 0);

		reqInvUnlock: in std_logic;
		ackInvUnlock: out std_logic;

		tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0);

		reqCoobufToHostif: in std_logic;
		ackCoobufToHostif: out std_logic;
		dneCoobufToHostif: in std_logic;
		avllenCoobufToHostif: out std_logic_vector(31 downto 0);

		coobufToHostifAXIS_tready: in std_logic;
		coobufToHostifAXIS_tvalid: out std_logic;
		coobufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
		coobufToHostifAXIS_tlast: out std_logic
	);
end Corner_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Corner_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_size2kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(8 downto 0);
			drdA: out std_logic_vector(31 downto 0);
			dwrA: in std_logic_vector(31 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(8 downto 0);
			drdB: out std_logic_vector(31 downto 0);
			dwrB: in std_logic_vector(31 downto 0)
		);
	end component;

	component Dpbram_size2kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(10 downto 0);
			drdA: out std_logic_vector(7 downto 0);
			dwrA: in std_logic_vector(7 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(10 downto 0);
			drdB: out std_logic_vector(7 downto 0);
			dwrB: in std_logic_vector(7 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant tixVStateIdle: std_logic_vector(7 downto 0) := x"00";
	constant tixVStateAcq: std_logic_vector(7 downto 0) := x"01";
	constant tixVStateLock: std_logic_vector(7 downto 0) := x"02";

	---- coordwrAte buffer B/hostif-facing operation (coobufB)
	type stateCoobufB_t is (
		stateCoobufBInit,
		stateCoobufBIdle,
		stateCoobufBXferA, stateCoobufBXferB,
		stateCoobufBDone
	);
	signal stateCoobufB: stateCoobufB_t;

	signal enCoobufB: std_logic;
	signal aCoobufB: natural range 0 to 2*1024/4-1;
	signal aCoobufB_vec: std_logic_vector(8 downto 0);

	-- IP sigs.coobufB.cust --- INSERT

	---- Harris corner detection and score pipeline operation (corner)
	type stateCorner_t is (
		stateCornerInit,
		stateCornerRun,
		stateCornerEolA, stateCornerEolB
	);
	signal stateCorner: stateCorner_t;

	signal dIgrm1: std_logic_vector(47 downto 0); -- 6x 8bits
	signal lat: natural range 0 to 2000-1; -- pipeline latency in counts of ceScore active
	signal ceScore: std_logic;
	signal abcde: natural range 0 to 4;
	signal dx: std_logic_vector(44 downto 0); -- 5x 9bits
	signal dy: std_logic_vector(44 downto 0); -- 5x 9bits

	-- IP sigs.corner.cust --- INSERT

	---- intermediate result streaming operation (imdstream)
	type stateImdstream_t is (
		stateImdstreamInit,
		stateImdstreamSkip,
		stateImdstreamRun,
		stateImdstreamHold,
		stateImdstreamEol
	);
	signal stateImdstream: stateImdstream_t;

	signal shift: natural range 0 to 47;
	signal scoreMin: std_logic_vector(7 downto 0);
	signal scoreMax: std_logic_vector(7 downto 0);

	signal ceMaxsel: std_logic;
	signal fghij: natural;

	signal enImdbuf: std_logic;
	signal enImd0buf: std_logic;
	signal enImd1buf: std_logic;
	signal enImd2buf: std_logic;
	signal enImd3buf: std_logic;
	signal enImd4buf: std_logic;

	signal aImdbuf: natural range 0 to 2*1024-1;
	signal aImdbuf_vec: std_logic_vector(10 downto 0);

	signal enImdbufB: std_logic;

	signal aImdbufB: natural range 0 to 2*1024-1;
	signal aImdbufB_vec: std_logic_vector(10 downto 0);

	signal dImd: std_logic_vector(39 downto 0);

	-- IP sigs.imdstream.cust --- INSERT

	---- intermediate result streaming operation (maxsel)
	type stateMaxsel_t is (
		stateMaxselInit,
		stateMaxselRun,
		stateMaxselEol
	);
	signal stateMaxsel: stateMaxsel_t;

	signal tkst: std_logic_vector(31 downto 0);

	type maximds_t is array (0 to 4) of std_logic_vector(7 downto 0);
	signal maximds: maximds_t;
	signal maximdsm1: maximds_t;

	type ixMaximds_t is array (0 to 4) of natural range 0 to 4;
	signal ixMaximds: ixMaximds_t;
	signal IxMaximdsm1: ixMaximds_t;

	type unqMaximds_t is array (0 to 4) of boolean;
	signal unqMaximds: unqMaximds_t;
	signal unqMaximdsm1: unqMaximds_t;

	signal ixMax: natural range 0 to 4;
	signal unqMax: boolean;

	signal enCoobuf: std_logic;

	signal aCoobuf: natural range 0 to 2*1024/4-1;
	signal aCoobuf_vec: std_logic_vector(8 downto 0);

	signal dwrCoobuf: std_logic_vector(31 downto 0);

	-- IP sigs.maxsel.cust --- INSERT

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv,
		stateOpRun
	);
	signal stateOp: stateOp_t;

	signal ackInvAcquire_sig: std_logic;
	signal ackInvConfig_sig: std_logic;
	signal ackInvSet_sig: std_logic;
	signal ackInvUnlock_sig: std_logic;

	signal rng: std_logic;
	signal tixVState: std_logic_vector(7 downto 0);
	signal linNotLog: std_logic;
	signal thd: natural range 0 to 255;

	signal row0: natural range 0 to 1500-1;
	signal row1: natural range 0 to 1500-1;
	signal col0: natural range 0 to 2000-1;
	signal col1: natural range 0 to 2000-1;

	signal colLast: natural range 0 to 2000-1;
	signal rowLast: natural range 0 to 1500-1;

	-- IP sigs.op.cust --- INSERT

	---- Harris score pipeline operation (score)
	type stateScore_t is (
		stateScoreInit,
		stateScoreRun
	);
	signal stateScore: stateScore_t;

	signal xsqr: std_logic_vector(89 downto 0); -- stage 1; 5x 18bits, set by modules xsqr0 to xsqr4
	signal ysqr: std_logic_vector(89 downto 0); -- 5x 18bits, set by modules ysqr0 to ysqr4
	signal xy: std_logic_vector(89 downto 0); -- 5x 18bits, set by modules xy0 to xy4

	signal colsumXA: std_logic_vector(37 downto 0); -- stage 2
	signal colsumYA: std_logic_vector(37 downto 0);
	signal colsumXYA: std_logic_vector(37 downto 0);

	signal xsqr4p1: std_logic_vector(17 downto 0);
	signal xsqr4p2: std_logic_vector(17 downto 0);

	signal ysqr4p1: std_logic_vector(17 downto 0);
	signal ysqr4p2: std_logic_vector(17 downto 0);

	signal xy4p1: std_logic_vector(17 downto 0);
	signal xy4p2: std_logic_vector(17 downto 0);

	signal colsumXB: std_logic_vector(19 downto 0); -- stage 3
	signal colsumYB: std_logic_vector(19 downto 0);
	signal colsumXYB: std_logic_vector(19 downto 0);

	signal colsumXC: std_logic_vector(20 downto 0); -- stage 4
	signal colsumYC: std_logic_vector(20 downto 0);
	signal colsumXYC: std_logic_vector(20 downto 0);

	signal colsumX: std_logic_vector(104 downto 0); -- stage 5; 5x 21bits
	signal colsumY: std_logic_vector(104 downto 0); -- 5x 21bits
	signal colsumXY: std_logic_vector(104 downto 0); -- 5x 21bits

	signal sumXA: std_logic_vector(43 downto 0); -- stage 6
	signal sumYA: std_logic_vector(43 downto 0);
	signal sumXYA: std_logic_vector(43 downto 0);

	signal colsumX4p1: std_logic_vector(20 downto 0);
	signal colsumX4p2: std_logic_vector(20 downto 0);

	signal colsumY4p1: std_logic_vector(20 downto 0);
	signal colsumY4p2: std_logic_vector(20 downto 0);

	signal colsumXY4p1: std_logic_vector(20 downto 0);
	signal colsumXY4p2: std_logic_vector(20 downto 0);

	signal sumXB: std_logic_vector(22 downto 0); -- stage 7
	signal sumYB: std_logic_vector(22 downto 0);
	signal sumXYB: std_logic_vector(22 downto 0);

	signal sumX: std_logic_vector(22 downto 0); -- stage 8
	signal sumY: std_logic_vector(22 downto 0);
	signal sumXY: std_logic_vector(22 downto 0);

	signal sumIII: std_logic_vector(23 downto 0); -- stage 9
	signal termI: std_logic_vector(45 downto 0);
	signal termII: std_logic_vector(45 downto 0);
	signal termIII: std_logic_vector(47 downto 0); -- stage 10
	signal diffI_II: std_logic_vector(46 downto 0);
	signal termIIIk: std_logic_vector(43 downto 0); -- stage 11
	signal diffI_IIp1: std_logic_vector(46 downto 0);
	signal r: std_logic_vector(47 downto 0); -- stage 12
	signal rexp: std_logic_vector(7 downto 0); -- stage 13
	signal rshift: natural range 0 to 39;

	-- IP sigs.score.cust --- INSERT

	---- myImd0buf
	signal drdImd0bufB: std_logic_vector(7 downto 0);

	---- myImd1buf
	signal drdImd1bufB: std_logic_vector(7 downto 0);

	---- myImd2buf
	signal drdImd2bufB: std_logic_vector(7 downto 0);

	---- myImd3buf
	signal drdImd3bufB: std_logic_vector(7 downto 0);

	---- myImd4buf
	signal drdImd4bufB: std_logic_vector(7 downto 0);

	---- other
	signal sprsNotFull: std_logic := '1';
	-- IP sigs.oth.cust --- IBEGIN

	------------------------------------------------------------------------
	-- functional description
	------------------------------------------------------------------------

	-- pipelined Harris corner detection algorithm

	-- IP sigs.oth.cust --- IEND

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myCoobuf : Dpbram_size2kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enCoobuf,
			weA => '1',

			aA => aCoobuf_vec,
			drdA => open,
			dwrA => dwrCoobuf,

			rstB => reset,
			clkB => mclk,

			enB => enCoobufB,
			weB => '0',

			aB => aCoobufB_vec,
			drdB => coobufToHostifAXIS_tdata,
			dwrB => (others => '0')
		);

	myImd0buf : Dpbram_size2kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enImd0buf,
			weA => '1',

			aA => aImdbuf_vec,
			drdA => open,
			dwrA => rexp,

			rstB => reset,
			clkB => mclk,

			enB => enImdbufB,
			weB => '0',

			aB => aImdbufB_vec,
			drdB => drdImd0bufB,
			dwrB => (others => '0')
		);

	myImd1buf : Dpbram_size2kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enImd1buf,
			weA => '1',

			aA => aImdbuf_vec,
			drdA => open,
			dwrA => rexp,

			rstB => reset,
			clkB => mclk,

			enB => enImdbufB,
			weB => '0',

			aB => aImdbufB_vec,
			drdB => drdImd1bufB,
			dwrB => (others => '0')
		);

	myImd2buf : Dpbram_size2kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enImd2buf,
			weA => '1',

			aA => aImdbuf_vec,
			drdA => open,
			dwrA => rexp,

			rstB => reset,
			clkB => mclk,

			enB => enImdbufB,
			weB => '0',

			aB => aImdbufB_vec,
			drdB => drdImd2bufB,
			dwrB => (others => '0')
		);

	myImd3buf : Dpbram_size2kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enImd3buf,
			weA => '1',

			aA => aImdbuf_vec,
			drdA => open,
			dwrA => rexp,

			rstB => reset,
			clkB => mclk,

			enB => enImdbufB,
			weB => '0',

			aB => aImdbufB_vec,
			drdB => drdImd3bufB,
			dwrB => (others => '0')
		);

	myImd4buf : Dpbram_size2kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enImd4buf,
			weA => '1',

			aA => aImdbuf_vec,
			drdA => open,
			dwrA => rexp,

			rstB => reset,
			clkB => mclk,

			enB => enImdbufB,
			weB => '0',

			aB => aImdbufB_vec,
			drdB => drdImd4bufB,
			dwrB => (others => '0')
		);

	------------------------------------------------------------------------
	-- implementation: coordwrAte buffer B/hostif-facing operation (coobufB)
	------------------------------------------------------------------------

	-- IP impl.coobufB.wiring --- BEGIN
	ackCoobufToHostif <= '1' when (stateCoobufB=stateCoobufBXferA or stateCoobufB=stateCoobufBXferB or stateCoobufB=stateCoobufBDone) else '0';

	coobufToHostifAXIS_tvalid <= '1' when stateCoobufB=stateCoobufBXferB else '0';
	coobufToHostifAXIS_tlast <= '0' when (stateCoobufB=stateCoobufBXferA or (stateCoobufB=stateCoobufBXferB and aCoobufB/=2*1024/4-1)) else '1';

	enCoobufB <= '1' when stateCoobufB=stateCoobufBXferA else '0';
	aCoobufB_vec <= std_logic_vector(to_unsigned(aCoobufB, 9));
	-- IP impl.coobufB.wiring --- END

	-- IP impl.coobufB.wiring.cust --- RBEGIN
	avllenCoobufToHostif <= std_logic_vector(to_unsigned(2*1024, 32)) when stateCoobufB=stateCoobufBIdle else (others => '0');
	-- IP impl.coobufB.wiring.cust --- REND

	-- IP impl.coobufB.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.coobufB.vars --- BEGIN
		-- IP impl.coobufB.vars --- END

	begin
		if reset='1' then
			-- IP impl.coobufB.asyncrst --- BEGIN
			stateCoobufB <= stateCoobufBInit;
			aCoobufB <= 0;

			-- IP impl.coobufB.asyncrst --- END
			-- IP impl.coobufB.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if stateCoobufB=stateCoobufBInit then
				-- IP impl.coobufB.syncrst --- BEGIN
				aCoobufB <= 0;

				-- IP impl.coobufB.syncrst --- END
				-- IP impl.coobufB.syncrst.cust --- INSERT

				if reqCoobufToHostif='0' then
					stateCoobufB <= stateCoobufBIdle;
				end if;

			elsif stateCoobufB=stateCoobufBIdle then
				if reqCoobufToHostif='1' then
					stateCoobufB <= stateCoobufBXferA;
				end if;

			elsif stateCoobufB=stateCoobufBXferA then
				stateCoobufB <= stateCoobufBXferB;

			elsif stateCoobufB=stateCoobufBXferB then
				if coobufToHostifAXIS_tready='1' then
					if aCoobufB=2*1024/4-1 then
						stateCoobufB <= stateCoobufBDone;

					else
						aCoobufB <= aCoobufB + 1; -- IP impl.coobufB.xferB.inc --- ILINE

						stateCoobufB <= stateCoobufBXferA;
					end if;

				elsif reqCoobufToHostif='0' then
					stateCoobufB <= stateCoobufBInit;
				end if;

			elsif stateCoobufB=stateCoobufBDone then
				if dneCoobufToHostif='1' then
					stateCoobufB <= stateCoobufBInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.coobufB.rising --- END

	------------------------------------------------------------------------
	-- implementation: Harris corner detection and score pipeline operation (corner)
	------------------------------------------------------------------------

	-- IP impl.corner.wiring --- BEGIN
	-- IP impl.corner.wiring --- END

	-- IP impl.corner.wiring.cust --- LINE

	-- IP impl.corner.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.corner.vars --- RBEGIN
		variable col_lcl: natural range 0 to 1999;
		variable postcol_lcl: natural range 0 to 1999;
		-- IP impl.corner.vars --- REND

	begin
		if reset='1' then
			-- IP impl.corner.asyncrst --- BEGIN
			stateCorner <= stateCornerInit;
			dIgrm1 <= (others => '0');
			lat <= 22;
			ceScore <= '0';
			abcde <= 0;
			dx <= (others => '0');
			dy <= (others => '0');

			-- IP impl.corner.asyncrst --- END
			-- IP impl.corner.asyncrst.cust --- IBEGIN
			col_lcl := 0;
			postcol_lcl := 0;
			-- IP impl.corner.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			if (stateCorner=stateCornerInit or rng='0') then
				-- IP impl.corner.syncrst --- BEGIN
				dIgrm1 <= (others => '0');
				lat <= 22;
				ceScore <= '0';
				abcde <= 0;
				dx <= (others => '0');
				dy <= (others => '0');

				-- IP impl.corner.syncrst --- END
				-- IP impl.corner.syncrst.cust --- IBEGIN
				col_lcl := 0;
				postcol_lcl := 0;
				-- IP impl.corner.syncrst.cust --- IEND

				if (rng='1' and vsync='1') then
					stateCorner <= stateCornerRun;

				else
					stateCorner <= stateCornerInit;
				end if;

			elsif stateCorner=stateCornerRun then
				-- IP impl.corner.run.pre --- IBEGIN
				if ceScore='1' then
					if abcde=4 then
						abcde <= 0;
					else
						abcde <= abcde + 1;
					end if;
				end if;
				-- IP impl.corner.run.pre --- IEND

				if (vsync='0' and grayFromVideoinAXIS_tvalid='1') then
					-- IP impl.corner.run --- IBEGIN
					for i in 0 to 4 loop
						dx((4-i+1)*9-1 downto (4-i)*9) <= std_logic_vector(signed('0' & grayFromVideoinAXIS_tdata((4-i)*12+11 downto (4-i)*12+4)) - signed('0' & dIgrm1((4-i)*8+7 downto (4-i)*8)));
						dy((4-i+1)*9-1 downto (4-i)*9) <= std_logic_vector(signed('0' & grayFromVideoinAXIS_tdata((4-i)*12+11 downto (4-i)*12+4)) - signed('0' & grayFromVideoinAXIS_tdata((4-i+1)*12+11 downto (4-i+1)*12+4)));
					end loop;

					for i in 0 to 5 loop
						dIgrm1(i*8+7 downto i*8) <= grayFromVideoinAXIS_tdata(i*12+11 downto i*12+4);
					end loop;

					ceScore <= '1';

					col_lcl := col_lcl + 1;
					-- IP impl.corner.run --- IEND

					if grayFromVideoinAXIS_tlast='1' then
						postcol_lcl := 0; -- IP impl.corner.run.done --- ILINE

						if sprsNotFull='0' then
							stateCorner <= stateCornerEolA;

						else
							stateCorner <= stateCornerEolB;
						end if;

					else
						stateCorner <= stateCornerRun;
					end if;

				else
					ceScore <= '0'; -- IP impl.corner.run.reset --- ILINE

					stateCorner <= stateCornerRun;
				end if;

			elsif stateCorner=stateCornerEolA then
				if postcol_lcl=lat+2 then
					ceScore <= '0'; -- IP impl.corner.eolA.reset --- ILINE

					if vsync='1' then
						stateCorner <= stateCornerInit;

					else
						-- IP impl.corner.eolA.restart --- IBEGIN
						abcde <= 0;

						col_lcl := 0;
						-- IP impl.corner.eolA.restart --- IEND

						stateCorner <= stateCornerRun;
					end if;

				else
					-- IP impl.corner.eolA.inc --- IBEGIN
					ceScore <= '1';

					postcol_lcl := postcol_lcl + 1;
					-- IP impl.corner.eolA.inc --- IEND

					if sprsNotFull='0' then
						stateCorner <= stateCornerEolA;

					else
						stateCorner <= stateCornerEolB;
					end if;
				end if;

			elsif stateCorner=stateCornerEolB then
				ceScore <= '0'; -- IP impl.corner.eolB --- ILINE

				stateCorner <= stateCornerEolA;
			end if;
		end if;
	end process;
	-- IP impl.corner.rising --- END

	------------------------------------------------------------------------
	-- implementation: intermediate result streaming operation (imdstream)
	------------------------------------------------------------------------

	-- IP impl.imdstream.wiring --- BEGIN
	getInfoScoreMin <= scoreMin;
	getInfoScoreMax <= scoreMax;

	enImd0buf <= '1' when (enImdbuf='1' and fghij=0) else '0';
	enImd1buf <= '1' when (enImdbuf='1' and fghij=1) else '0';
	enImd2buf <= '1' when (enImdbuf='1' and fghij=2) else '0';
	enImd3buf <= '1' when (enImdbuf='1' and fghij=3) else '0';
	enImd4buf <= '1' when (enImdbuf='1' and fghij=4) else '0';

	aImdbuf_vec <= std_logic_vector(to_unsigned(aImdbuf, 11));

	aImdbufB_vec <= std_logic_vector(to_unsigned(aImdbufB, 11));
	-- IP impl.imdstream.wiring --- END

	-- IP impl.imdstream.wiring.cust --- LINE

	-- IP impl.imdstream.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.imdstream.vars --- RBEGIN
		variable col_lcl: natural range 0 to 2000-1;

		variable shift_lcl: natural range 0 to 47;

		variable scoreMin_lcl: std_logic_vector(7 downto 0);
		variable scoreMax_lcl: std_logic_vector(7 downto 0);
		-- IP impl.imdstream.vars --- REND

	begin
		if reset='1' then
			-- IP impl.imdstream.asyncrst --- BEGIN
			stateImdstream <= stateImdstreamInit;
			shift <= 0;
			scoreMin <= (others => '1');
			scoreMax <= (others => '0');
			ceMaxsel <= '0';
			fghij <= 0;
			enImdbuf <= '0';
			aImdbuf <= 0;
			enImdbufB <= '0';
			aImdbufB <= 0;
			dImd <= (others => '0');

			-- IP impl.imdstream.asyncrst --- END
			-- IP impl.imdstream.asyncrst.cust --- IBEGIN
			col_lcl := 0;
			shift_lcl := 0;
			scoreMin_lcl := (others => '1');
			scoreMax_lcl := (others => '0');
			-- IP impl.imdstream.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			if (stateImdstream=stateImdstreamInit or rng='0') then
				-- IP impl.imdstream.syncrst --- BEGIN
				shift <= 0;
				scoreMin <= (others => '1');
				scoreMax <= (others => '0');
				ceMaxsel <= '0';
				fghij <= 0;
				enImdbuf <= '0';
				aImdbuf <= 0;
				enImdbufB <= '0';
				aImdbufB <= 0;
				dImd <= (others => '0');

				-- IP impl.imdstream.syncrst --- END
				-- IP impl.imdstream.syncrst.cust --- IBEGIN
				col_lcl := 0;
				shift_lcl := 0;
				scoreMin_lcl := (others => '1');
				scoreMax_lcl := (others => '0');
				-- IP impl.imdstream.syncrst.cust --- IEND

				if (rng='1' and (vsync='1' and tixVState/=tixVStateLock)) then
					stateImdstream <= stateImdstreamSkip;

				else
					stateImdstream <= stateImdstreamInit;
				end if;

			elsif stateImdstream=stateImdstreamSkip then
				if ceScore='1' then
					if col_lcl=lat then
						col_lcl := 0; -- IP impl.imdstream.skip.done --- ILINE

						stateImdstream <= stateImdstreamRun;

					else
						col_lcl := col_lcl + 1; -- IP impl.imdstream.skip.inc --- ILINE

						stateImdstream <= stateImdstreamSkip;
					end if;
				end if;

			elsif stateImdstream=stateImdstreamRun then
				if ceScore='1' then
					-- IP impl.imdstream.run --- IBEGIN
					-- min/max update
					if unsigned(rexp)<unsigned(scoreMin_lcl) then
						scoreMin_lcl := rexp;
					end if;
					
					if unsigned(rexp)>unsigned(scoreMax_lcl) then
						scoreMax_lcl := rexp;
					end if;
					
					if rshift>shift_lcl then
						shift_lcl := rshift;
					end if;

					-- store
					enImdbuf <= '1';

					-- load
					enImdbufB <= '1';

					if col_lcl>0 then
						ceMaxsel <= '1';

						case fghij is
							when 3 =>
								dImd <= drdImd0bufB & drdImd1bufB & drdImd2bufB & drdImd3bufB & drdImd4bufB;
							when 4 =>
								dImd <= drdImd1bufB & drdImd2bufB & drdImd3bufB & drdImd4bufB & drdImd0bufB;
							when 0 =>
								dImd <= drdImd2bufB & drdImd3bufB & drdImd4bufB & drdImd0bufB & drdImd1bufB;
							when 1 =>
								dImd <= drdImd3bufB & drdImd4bufB & drdImd0bufB & drdImd1bufB & drdImd2bufB;
							when 2 =>
								dImd <= drdImd4bufB & drdImd0bufB & drdImd1bufB & drdImd2bufB & drdImd3bufB;
							when others =>
						end case;
					end if;

					if fghij=4 then
						fghij <= 0;
					else
						fghij <= fghij + 1;
					end if;

					if col_lcl/=0 and col_lcl/=colLast then
						aImdbuf <= aImdbuf + 1;
						aImdbufB <= aImdbufB + 1;
					end if;
					-- IP impl.imdstream.run --- IEND

					if col_lcl=colLast then
						stateImdstream <= stateImdstreamEol;

					else
						col_lcl := col_lcl + 1; -- IP impl.imdstream.run.nextCol --- ILINE

						if sprsNotFull='0' then
							stateImdstream <= stateImdstreamRun;

						else
							stateImdstream <= stateImdstreamHold;
						end if;
					end if;
				end if;

			elsif stateImdstream=stateImdstreamHold then
				-- IP impl.imdstream.hold --- IBEGIN
				enImdbuf <= '0';
				enImdbufB <= '0';

				ceMaxsel <= '0';
				-- IP impl.imdstream.hold --- IEND

				stateImdstream <= stateImdstreamRun;

			elsif stateImdstream=stateImdstreamEol then
				-- IP impl.imdstream.eol.pre --- IBEGIN
				enImdbuf <= '0';
				enImdbufB <= '0';

				ceMaxsel <= '0';
				-- IP impl.imdstream.eol.pre --- IEND

				if vsync='1' then
					-- IP impl.imdstream.eol.done --- IBEGIN
					if shift_lcl>=40 then
						shift <= 40;
					else
						shift <= shift_lcl;
					end if;

					scoreMin <= scoreMin_lcl;
					scoreMax <= scoreMax_lcl;
					-- IP impl.imdstream.eol.done --- IEND

					stateImdstream <= stateImdstreamInit;

				else
					-- IP impl.imdstream.eol.restart --- IBEGIN
					fghij <= 0;

					aImdbuf <= 0;
					aImdbufB <= 0;

					col_lcl := 0;
					-- IP impl.imdstream.eol.restart --- IEND

					stateImdstream <= stateImdstreamSkip;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.imdstream.rising --- END

	------------------------------------------------------------------------
	-- implementation: intermediate result streaming operation (maxsel)
	------------------------------------------------------------------------

	-- IP impl.maxsel.wiring --- BEGIN
	getInfoTkst <= tkst;

	aCoobuf_vec <= std_logic_vector(to_unsigned(aCoobuf, 9));
	-- IP impl.maxsel.wiring --- END

	-- IP impl.maxsel.wiring.cust --- LINE

	-- IP impl.maxsel.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.maxsel.vars --- RBEGIN
		variable postNotLive: boolean;
		
		constant imax: natural := 2; -- post-live cycles
		variable i: natural range 0 to imax;

		variable colmax_lcl: natural range 0 to 4;

		variable row_lcl: natural range 0 to 1500-1;
		variable col_lcl: natural range 0 to 2000-1;

		variable d0_1, d0_2, d0_3, d0_4, d1_2, d1_3, d1_4, d2_3, d2_4, d3_4: signed(8 downto 0);
		variable ge0_1, ge0_2, ge0_3, ge0_4, ge1_2, ge1_3, ge1_4, ge2_3, ge2_4, ge3_4: boolean;
		variable eq0, eq1, eq2, eq3, eq4: boolean; -- equal to any of the other elements

		variable e0_1, e0_2, e0_3, e0_4, e1_2, e1_3, e1_4, e2_3, e2_4, e3_4: signed(8 downto 0);
		variable gf0_1, gf0_2, gf0_3, gf0_4, gf1_2, gf1_3, gf1_4, gf2_3, gf2_4, gf3_4: boolean;
		variable er0, er1, er2, er3, er4: boolean; -- equal to any of the other elements

		variable flag: boolean;
		-- IP impl.maxsel.vars --- REND

	begin
		if reset='1' then
			-- IP impl.maxsel.asyncrst --- RBEGIN
			stateMaxsel <= stateMaxselInit;
			tkst <= (others => '0');
			maximds <= (others => (others => '0'));
			ixMaximds <= (others => 0);
			ixMaximdsm1 <= (others => 0);
			unqMaximds <= (others => false);
			unqMaximdsm1 <= (others => false);
			ixMax <= 0;
			unqMax <= false;
			enCoobuf <= '0';
			aCoobuf <= 0;
			dwrCoobuf <= (others => '0');

			postNotLive := false;
			i := 0;
			colmax_lcl := 0;
			row_lcl := 0;
			col_lcl := 0;
			-- IP impl.maxsel.asyncrst --- REND
			-- IP impl.maxsel.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateMaxsel=stateMaxselInit or rng='0') then
				-- IP impl.maxsel.syncrst --- RBEGIN
				maximds <= (others => (others => '0'));
				ixMaximds <= (others => 0);
				ixMaximdsm1 <= (others => 0);
				unqMaximds <= (others => false);
				unqMaximdsm1 <= (others => false);

				ixMax <= 0;
				unqMax <= false;

				enCoobuf <= '0';
				aCoobuf <= 0;
				dwrCoobuf <= (others => '0');

				postNotLive := false;

				i := 0;

				colmax_lcl := 0;

				row_lcl := 0;
				col_lcl := 0;
				-- IP impl.maxsel.syncrst --- REND
				-- IP impl.maxsel.syncrst.cust --- INSERT

				if (rng='1' and (vsync='1' and tixVState/=tixVStateLock)) then
					tkst <= tkclksrcGetTkstTkst; -- IP impl.maxsel.init.start --- ILINE

					stateMaxsel <= stateMaxselRun;

				else
					stateMaxsel <= stateMaxselInit;
				end if;

			elsif stateMaxsel=stateMaxselRun then
				-- IP impl.maxsel.run.pre --- IBEGIN
				if enCoobuf='1' then
					aCoobuf <= aCoobuf + 1;
				end if;
				-- IP impl.maxsel.run.pre --- IEND

				if ceMaxsel='1' or postNotLive then
					-- IP impl.maxsel.run --- IBEGIN
					-- find maximum element in incoming column
					d0_1 := signed('0' & dImd(39 downto 32)) - signed('0' & dImd(31 downto 24));
					ge0_1 := (d0_1(8) = '0');
					d0_2 := signed('0' & dImd(39 downto 32)) - signed('0' & dImd(23 downto 16));
					ge0_2 := (d0_2(8) = '0');
					d0_3 := signed('0' & dImd(39 downto 32)) - signed('0' & dImd(15 downto 8));
					ge0_3 := (d0_3(8) = '0');
					d0_4 := signed('0' & dImd(39 downto 32)) - signed('0' & dImd(7 downto 0));
					ge0_4 := (d0_4(8) = '0');

					eq0 := ((d0_1 = 0) or (d0_2 = 0) or (d0_3 = 0) or (d0_4 = 0));

					d1_2 := signed('0' & dImd(31 downto 24)) - signed('0' & dImd(23 downto 16));
					ge1_2 := (d1_2(8) = '0');
					d1_3 := signed('0' & dImd(31 downto 24)) - signed('0' & dImd(15 downto 8));
					ge1_3 := (d1_3(8) = '0');
					d1_4 := signed('0' & dImd(31 downto 24)) - signed('0' & dImd(7 downto 0));
					ge1_4 := (d1_4(8) = '0');

					eq1 := ((d0_1 = 0) or (d1_2 = 0) or (d1_3 = 0) or (d1_4 = 0));

					d2_3 := signed('0' & dImd(23 downto 16)) - signed('0' & dImd(15 downto 8));
					ge2_3 := (d2_3(8) = '0');
					d2_4 := signed('0' & dImd(23 downto 16)) - signed('0' & dImd(7 downto 0));
					ge2_4 := (d2_4(8) = '0');

					eq2 := ((d0_2 = 0) or (d1_2 = 0) or (d2_3 = 0) or (d2_4 = 0));

					d3_4 := signed('0' & dImd(15 downto 8)) - signed('0' & dImd(7 downto 0));
					ge3_4 := (d3_4(8) = '0');

					eq3 := ((d0_3 = 0) or (d1_3 = 0) or (d2_3 = 0) or (d3_4 = 0));

					eq4 := ((d0_4 = 0) or (d1_4 = 0) or (d2_4 = 0) or (d3_4 = 0));

					if (ge0_1 and ge0_2 and ge0_3 and ge0_4) then
						maximds(colmax_lcl) <= dImd(39 downto 32);
						ixMaximds(colmax_lcl) <= 0;
						unqMaximds(colmax_lcl) <= eq0;

					elsif (not ge0_1 and ge1_2 and ge1_3 and ge1_4) then
						maximds(colmax_lcl) <= dImd(31 downto 24);
						ixMaximds(colmax_lcl) <= 1;
						unqMaximds(colmax_lcl) <= eq1;

					elsif (not ge0_2 and not ge1_2 and ge2_3 and ge2_4) then
						maximds(colmax_lcl) <= dImd(23 downto 16);
						ixMaximds(colmax_lcl) <= 2;
						unqMaximds(colmax_lcl) <= eq2;

					elsif (not ge0_3 and not ge1_3 and not ge2_3 and ge3_4) then
						maximds(colmax_lcl) <= dImd(15 downto 8);
						ixMaximds(colmax_lcl) <= 3;
						unqMaximds(colmax_lcl) <= eq3;

					else
						maximds(colmax_lcl) <= dImd(7 downto 0);
						ixMaximds(colmax_lcl) <= 4;
						unqMaximds(colmax_lcl) <= eq4;
					end if;

					maximdsm1 <= maximds;
					ixMaximdsm1 <= ixMaximds;
					unqMaximdsm1 <= unqMaximds;

					-- find maximum among columns
					-- insufficient to just check if new maximd is max because current max might be overwritten (with a non-max)
					e0_1 := signed('0' & maximds(0)) - signed('0' & maximds(1));
					gf0_1 := (e0_1(8) = '0');
					e0_2 := signed('0' & maximds(0)) - signed('0' & maximds(2));
					gf0_2 := (e0_2(8) = '0');
					e0_3 := signed('0' & maximds(0)) - signed('0' & maximds(3));
					gf0_3 := (e0_3(8) = '0');
					e0_4 := signed('0' & maximds(0)) - signed('0' & maximds(4));
					gf0_4 := (e0_4(8) = '0');

					er0 := ((e0_1 = 0) or (e0_2 = 0) or (e0_3 = 0) or (e0_4 = 0));

					e1_2 := signed('0' & maximds(1)) - signed('0' & maximds(2));
					gf1_2 := (e1_2(8) = '0');
					e1_3 := signed('0' & maximds(1)) - signed('0' & maximds(3));
					gf1_3 := (e1_3(8) = '0');
					e1_4 := signed('0' & maximds(1)) - signed('0' & maximds(4));
					gf1_4 := (e1_4(8) = '0');

					er1 := ((e0_1 = 0) or (e1_2 = 0) or (e1_3 = 0) or (e1_4 = 0));

					e2_3 := signed('0' & maximds(2)) - signed('0' & maximds(3));
					gf2_3 := (e2_3(8) = '0');
					e2_4 := signed('0' & maximds(2)) - signed('0' & maximds(4));
					gf2_4 := (e2_4(8) = '0');

					er2 := ((e0_2 = 0) or (e1_2 = 0) or (e2_3 = 0) or (e2_4 = 0));

					e3_4 := signed('0' & maximds(3)) - signed('0' & maximds(4));
					gf3_4 := (e3_4(8) = '0');

					er3 := ((e0_3 = 0) or (e1_3 = 0) or (e2_3 = 0) or (e3_4 = 0));

					er4 := ((e0_4 = 0) or (e1_4 = 0) or (e2_4 = 0) or (e3_4 = 0));

					if (gf0_1 and gf0_2 and gf0_3 and gf0_4) then
						ixMax <= 0;
						unqMax <= er0;

					elsif (not gf0_1 and gf1_2 and gf1_3 and gf1_4) then
						ixMax <= 1;
						unqMax <= er1;

					elsif (not gf0_2 and not gf1_2 and gf2_3 and gf2_4) then
						ixMax <= 2;
						unqMax <= er2;

					elsif (not gf0_3 and not gf1_3 and not gf2_3 and gf3_4) then
						ixMax <= 3;
						unqMax <= er3;

					else
						ixMax <= 4;
						unqMax <= er4;
					end if;

					-- flag and store
					flag := false;

--					if unqMax then
--						if (colmax_lcl=0 and ixMax=3 and unqMaximdsm1(3) and unsigned(maximdsm1(3))>thd) then
--							flag := '1';
--						elsif (colmax_lcl=1 and ixMax=4 and unqMaximdsm1(4) and unsigned(maximdsm1(4))>thd) then
--							flag := '1';
--						elsif (colmax_lcl=2 and ixMax=0 and unqMaximdsm1(0) and unsigned(maximdsm1(0))>thd) then
--							flag := '1';
--						elsif (colmax_lcl=3 and ixMax=1 and unqMaximdsm1(1) and unsigned(maximdsm1(1))>thd) then
--							flag := '1';
--						elsif (colmax_lcl=4 and ixMax=2 and unqMaximdsm1(2) and unsigned(maximdsm1(2))>thd) then
--							flag := '1';
--						end if;
--					end if;
					if (colmax_lcl=0 and ixMax=3 and unsigned(maximdsm1(3))>thd) then
						flag := true;
					elsif (colmax_lcl=1 and ixMax=4 and unsigned(maximdsm1(4))>thd) then
						flag := true;
					elsif (colmax_lcl=2 and ixMax=0 and unsigned(maximdsm1(0))>thd) then
						flag := true;
					elsif (colmax_lcl=3 and ixMax=1 and unsigned(maximdsm1(1))>thd) then
						flag := true;
					elsif (colmax_lcl=4 and ixMax=2 and unsigned(maximdsm1(2))>thd) then
						flag := true;
					end if;

					if col_lcl<col0 or col_lcl>col1 or row_lcl<row0 or row_lcl>row1 or aCoobuf=2*1024/4-1 then
						flag := false;
					end if;

					if flag then
						enCoobuf <= '1';

						dwrCoobuf(31 downto 16) <= std_logic_vector(to_unsigned(row_lcl, 16));
						dwrCoobuf(15 downto 0) <= std_logic_vector(to_unsigned(col_lcl, 16));

					else
						enCoobuf <= '0';
					end if;

					if colmax_lcl=4 then
						colmax_lcl := 0;
					else
						colmax_lcl := colmax_lcl + 1;
					end if;
					-- IP impl.maxsel.run --- IEND

					if col_lcl+imax=colLast then
						if not postNotLive then
							-- IP impl.maxsel.run.toPost --- IBEGIN
							postNotLive := true;
							i := 0;
							-- IP impl.maxsel.run.toPost --- IEND

							stateMaxsel <= stateMaxselRun;

						else
							if i=imax then
								stateMaxsel <= stateMaxselEol;

							else
								i := i + 1; -- IP impl.maxsel.run.inc --- ILINE

								stateMaxsel <= stateMaxselRun;
							end if;
						end if;

					else
						col_lcl := col_lcl + 1; -- IP impl.maxsel.run.nextCol --- ILINE

						stateMaxsel <= stateMaxselRun;
					end if;

				else
					enCoobuf <= '0'; -- IP impl.maxsel.run.reset --- ILINE

					stateMaxsel <= stateMaxselRun;
				end if;

			elsif stateMaxsel=stateMaxselEol then
				if (row_lcl=rowLast or vsync='1') then
					-- IP impl.maxsel.eol.done --- IBEGIN
					enCoobuf <= '1';
					dwrCoobuf <= (others => '1');
					-- IP impl.maxsel.eol.done --- IEND

					stateMaxsel <= stateMaxselInit;

				else
					-- IP impl.maxsel.eol.nextRow --- IBEGIN
					row_lcl := row_lcl + 1;

					maximds <= (others => (others => '0'));
					ixMaximds <= (others => 0);
					ixMaximdsm1 <= (others => 0);
					unqMaximds <= (others => false);
					unqMaximdsm1 <= (others => false);

					ixMax <= 0;
					unqMax <= false;

					enCoobuf <= '0';

					postNotLive := false;

					colmax_lcl := 0;
					col_lcl := 0;
					-- IP impl.maxsel.eol.nextRow --- IEND

					stateMaxsel <= stateMaxselRun;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.maxsel.rising --- END

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	ackInvAcquire <= ackInvAcquire_sig;
	ackInvConfig <= ackInvConfig_sig;
	ackInvSet <= ackInvSet_sig;
	ackInvUnlock <= ackInvUnlock_sig;

	getInfoTixVState <= tixVState;

	colLast <= to_integer(unsigned(NCol) - 1);
	rowLast <= to_integer(unsigned(NRow) - 1);
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- LINE

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- RBEGIN
		variable vsync_last: std_logic;
		-- IP impl.op.vars --- REND

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- RBEGIN
			stateOp <= stateOpInit;
			ackInvAcquire_sig <= '0';
			ackInvConfig_sig <= '0';
			ackInvSet_sig <= '0';
			ackInvUnlock_sig <= '0';
			rng <= '0';
			tixVState <= (others => '0');
			linNotLog <= '0';
			thd <= 80;
			row0 <= 0;
			row1 <= 1499;
			col0 <= 0;
			col1 <= 1999;

			vsync_last := '0';
			-- IP impl.op.asyncrst --- REND
			-- IP impl.op.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateOp=stateOpInit or (stateOp/=stateOpInv and (reqInvAcquire='1' or reqInvConfig='1' or reqInvSet='1' or reqInvUnlock='1'))) then
				if reqInvAcquire='1' then
					-- IP impl.op.init.invAcquire --- IBEGIN
					if tixVState=tixVStateIdle then
						tixVState <= tixVStateAcq;
					end if;

					ackInvAcquire_sig <= '1';
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvUnlock_sig <= '0';
					-- IP impl.op.init.invAcquire --- IEND

					stateOp <= stateOpInv;

				elsif reqInvConfig='1' then
					-- IP impl.op.init.invConfig --- IBEGIN
					if configLinNotLog=tru8 then
						linNotLog <= '1';
					else
						linNotLog <= '0';
					end if;
					thd <= to_integer(unsigned(configThd));
					row0 <= to_integer(unsigned(configRow0));
					row1 <= to_integer(unsigned(configRow1));
					col0 <= to_integer(unsigned(configCol0));
					col1 <= to_integer(unsigned(configCol1));

					ackInvAcquire_sig <= '0';
					ackInvConfig_sig <= '1';
					ackInvSet_sig <= '0';
					ackInvUnlock_sig <= '0';
					-- IP impl.op.init.invConfig --- IEND

					stateOp <= stateOpInv;

				elsif reqInvSet='1' then
					-- IP impl.op.init.invSet --- IBEGIN
					if setRng=tru8 then
						rng <= '1';
					else
						rng <= '0';
					end if;

					ackInvAcquire_sig <= '0';
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '1';
					ackInvUnlock_sig <= '0';
					-- IP impl.op.init.invSet --- IEND

					stateOp <= stateOpInv;

				elsif reqInvUnlock='1' then
					-- IP impl.op.init.invUnlock --- IBEGIN
					if tixVState=tixVStateLock then
						tixVState <= tixVStateIdle;
					end if;

					ackInvAcquire_sig <= '0';
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvUnlock_sig <= '1';
					-- IP impl.op.init.invUnlock --- IEND

					stateOp <= stateOpInv;

				else
					-- IP impl.op.syncrst --- RBEGIN
					ackInvAcquire_sig <= '0';
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvUnlock_sig <= '0';

					vsync_last := vsync;
					-- IP impl.op.syncrst --- REND
					-- IP impl.op.syncrst.cust --- INSERT

					if rng='1' then
						stateOp <= stateOpRun;

					else
						stateOp <= stateOpInit;
					end if;
				end if;

			elsif stateOp=stateOpInv then
				if ((reqInvAcquire='0' and ackInvAcquire_sig='1') or (reqInvConfig='0' and ackInvConfig_sig='1') or (reqInvSet='0' and ackInvSet_sig='1') or (reqInvUnlock='0' and ackInvUnlock_sig='1')) then
					-- IP impl.op.inv.reset --- IBEGIN
					ackInvAcquire_sig <= '0';
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvUnlock_sig <= '0';
					-- IP impl.op.inv.reset --- IEND

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpRun then
				-- IP impl.op.run --- IBEGIN
				if tixVState=tixVStateAcq and vsync_last='0' and vsync='1' then
					tixVState <= tixVStateLock;
				end if;

				vsync_last := vsync;
				-- IP impl.op.run --- IEND
			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: Harris score pipeline operation (score)
	------------------------------------------------------------------------

	-- IP impl.score.wiring --- BEGIN
	-- IP impl.score.wiring --- END

	-- IP impl.score.wiring.cust --- LINE

	-- IP impl.score.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.score.vars --- RBEGIN
		variable x: unsigned(50 downto 0);

		variable msb: natural range 0 to 47;
		-- IP impl.score.vars --- REND

	begin
		if reset='1' then
			-- IP impl.score.asyncrst --- BEGIN
			stateScore <= stateScoreInit;
			xsqr <= (others => '0');
			ysqr <= (others => '0');
			xy <= (others => '0');
			colsumXA <= (others => '0');
			colsumYA <= (others => '0');
			colsumXYA <= (others => '0');
			xsqr4p1 <= (others => '0');
			xsqr4p2 <= (others => '0');
			ysqr4p1 <= (others => '0');
			ysqr4p2 <= (others => '0');
			xy4p1 <= (others => '0');
			xy4p2 <= (others => '0');
			colsumXB <= (others => '0');
			colsumYB <= (others => '0');
			colsumXYB <= (others => '0');
			colsumXC <= (others => '0');
			colsumYC <= (others => '0');
			colsumXYC <= (others => '0');
			colsumX <= (others => '0');
			colsumY <= (others => '0');
			colsumXY <= (others => '0');
			sumXA <= (others => '0');
			sumYA <= (others => '0');
			sumXYA <= (others => '0');
			colsumX4p1 <= (others => '0');
			colsumX4p2 <= (others => '0');
			colsumY4p1 <= (others => '0');
			colsumY4p2 <= (others => '0');
			colsumXY4p1 <= (others => '0');
			colsumXY4p2 <= (others => '0');
			sumXB <= (others => '0');
			sumYB <= (others => '0');
			sumXYB <= (others => '0');
			sumX <= (others => '0');
			sumY <= (others => '0');
			sumXY <= (others => '0');
			sumIII <= (others => '0');
			termI <= (others => '0');
			termII <= (others => '0');
			termIII <= (others => '0');
			diffI_II <= (others => '0');
			termIIIk <= (others => '0');
			diffI_IIp1 <= (others => '0');
			r <= (others => '0');
			rexp <= (others => '0');
			rshift <= 0;

			-- IP impl.score.asyncrst --- END
			-- IP impl.score.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if stateScore=stateScoreInit then
				-- IP impl.score.syncrst --- BEGIN
				xsqr <= (others => '0');
				ysqr <= (others => '0');
				xy <= (others => '0');
				colsumXA <= (others => '0');
				colsumYA <= (others => '0');
				colsumXYA <= (others => '0');
				xsqr4p1 <= (others => '0');
				xsqr4p2 <= (others => '0');
				ysqr4p1 <= (others => '0');
				ysqr4p2 <= (others => '0');
				xy4p1 <= (others => '0');
				xy4p2 <= (others => '0');
				colsumXB <= (others => '0');
				colsumYB <= (others => '0');
				colsumXYB <= (others => '0');
				colsumXC <= (others => '0');
				colsumYC <= (others => '0');
				colsumXYC <= (others => '0');
				colsumX <= (others => '0');
				colsumY <= (others => '0');
				colsumXY <= (others => '0');
				sumXA <= (others => '0');
				sumYA <= (others => '0');
				sumXYA <= (others => '0');
				colsumX4p1 <= (others => '0');
				colsumX4p2 <= (others => '0');
				colsumY4p1 <= (others => '0');
				colsumY4p2 <= (others => '0');
				colsumXY4p1 <= (others => '0');
				colsumXY4p2 <= (others => '0');
				sumXB <= (others => '0');
				sumYB <= (others => '0');
				sumXYB <= (others => '0');
				sumX <= (others => '0');
				sumY <= (others => '0');
				sumXY <= (others => '0');
				sumIII <= (others => '0');
				termI <= (others => '0');
				termII <= (others => '0');
				termIII <= (others => '0');
				diffI_II <= (others => '0');
				termIIIk <= (others => '0');
				diffI_IIp1 <= (others => '0');
				r <= (others => '0');
				rexp <= (others => '0');
				rshift <= 0;

				-- IP impl.score.syncrst --- END
				-- IP impl.score.syncrst.cust --- INSERT

				stateScore <= stateScoreRun;

			elsif stateScore=stateScoreRun then
				-- IP impl.score.run --- IBEGIN
				if ceScore='1' then
					-- stage 1 (replaces dxsqr, dysqr, xy)
					for i in 0 to 4 loop
						xsqr(i*18+17 downto i*18) <= std_logic_vector(signed(dx(i*9+8 downto i*9)) * signed(dx(i*9+8 downto i*9)));
						ysqr(i*18+17 downto i*18) <= std_logic_vector(signed(dy(i*9+8 downto i*9)) * signed(dy(i*9+8 downto i*9)));
						xy(i*18+17 downto i*18) <= std_logic_vector(signed(dx(i*9+8 downto i*9)) * signed(dy(i*9+8 downto i*9)));
					end loop;

					-- stage 2 (replaces colsumXA, colsumYA, colsumXYA)
					for i in 0 to 1 loop
						colsumXA(i*19+18 downto i*19) <= std_logic_vector(resize(signed(xsqr(2*i*18+35 downto 2*i*18+18)), 19) + resize(signed(xsqr(2*i*18+17 downto 2*i*18)), 19));
						colsumYA(i*19+18 downto i*19) <= std_logic_vector(resize(signed(ysqr(2*i*18+35 downto 2*i*18+18)), 19) + resize(signed(ysqr(2*i*18+17 downto 2*i*18)), 19));
						colsumXYA(i*19+18 downto i*19) <= std_logic_vector(resize(signed(xy(2*i*18+35 downto 2*i*18+18)), 19) + resize(signed(xy(2*i*18+17 downto 2*i*18)), 19));
					end loop;
					xsqr4p1 <= xsqr(4*18+17 downto 4*18);
					ysqr4p1 <= ysqr(4*18+17 downto 4*18);
					xy4p1 <= xy(4*18+17 downto 4*18);

					-- stage 3 (replaces colsumXB, colsumYB, colsumXYB)
					colsumXB <= std_logic_vector(resize(signed(colsumXA(37 downto 19)), 20) + resize(signed(colsumXA(18 downto 0)), 20));
					colsumYB <= std_logic_vector(resize(signed(colsumYA(37 downto 19)), 20) + resize(signed(colsumYA(18 downto 0)), 20));
					colsumXYB <= std_logic_vector(resize(signed(colsumXYA(37 downto 19)), 20) + resize(signed(colsumXYA(18 downto 0)), 20));
					xsqr4p2 <= xsqr4p1;
					ysqr4p2 <= ysqr4p1;
					xy4p2 <= xy4p1;

					-- stage 4 (replaces colsumXC, colsumYC, colsumXYC)
					colsumXC <= std_logic_vector(resize(signed(colsumXB), 21) + resize(signed(xsqr4p2), 21));
					colsumYC <= std_logic_vector(resize(signed(colsumYB), 21) + resize(signed(ysqr4p2), 21));
					colsumXYC <= std_logic_vector(resize(signed(colsumXYB), 21) + resize(signed(xy4p2), 21));

					-- stage 5 (replaces FSM copy)
					if abcde=0 then
						colsumX((4-4+1)*21-1 downto (4-4)*21) <= colsumXC;
						colsumY((4-4+1)*21-1 downto (4-4)*21) <= colsumYC;
						colsumXY((4-4+1)*21-1 downto (4-4)*21) <= colsumXYC;
					elsif abcde=1 then
						colsumX((4-0+1)*21-1 downto (4-0)*21) <= colsumXC;
						colsumY((4-0+1)*21-1 downto (4-0)*21) <= colsumYC;
						colsumXY((4-0+1)*21-1 downto (4-0)*21) <= colsumXYC;
					elsif abcde=2 then
						colsumX((4-1+1)*21-1 downto (4-1)*21) <= colsumXC;
						colsumY((4-1+1)*21-1 downto (4-1)*21) <= colsumYC;
						colsumXY((4-1+1)*21-1 downto (4-1)*21) <= colsumXYC;
					elsif abcde=3 then
						colsumX((4-2+1)*21-1 downto (4-2)*21) <= colsumXC;
						colsumY((4-2+1)*21-1 downto (4-2)*21) <= colsumYC;
						colsumXY((4-2+1)*21-1 downto (4-2)*21) <= colsumXYC;
					elsif abcde=4 then
						colsumX((4-3+1)*21-1 downto (4-3)*21) <= colsumXC;
						colsumY((4-3+1)*21-1 downto (4-3)*21) <= colsumYC;
						colsumXY((4-3+1)*21-1 downto (4-3)*21) <= colsumXYC;
					end if;

					-- stage 6 (replaces sumXA, sumYA, sumXYA)
					for i in 0 to 1 loop
						sumXA(i*22+21 downto i*22) <= std_logic_vector(resize(signed(colsumX(2*i*21+41 downto 2*i*21+21)), 22) + resize(signed(colsumX(2*i*21+20 downto 2*i*21)), 22));
						sumYA(i*22+21 downto i*22) <= std_logic_vector(resize(signed(colsumY(2*i*21+41 downto 2*i*21+21)), 22) + resize(signed(colsumY(2*i*21+20 downto 2*i*21)), 22));
						sumXYA(i*22+21 downto i*22) <= std_logic_vector(resize(signed(colsumXY(2*i*21+41 downto 2*i*21+21)), 22) + resize(signed(colsumXY(2*i*21+20 downto 2*i*21)), 22));
					end loop;
					colsumX4p1 <= colsumX(4*21+20 downto 4*21);
					colsumY4p1 <= colsumY(4*21+20 downto 4*21);
					colsumXY4p1 <= colsumXY(4*21+20 downto 4*21);

					-- stage 7 (replaces sumXB, sumYB, sumXYB)
					sumXB <= std_logic_vector(resize(signed(sumXA(43 downto 22)), 23) + resize(signed(sumXA(21 downto 0)), 23));
					sumYB <= std_logic_vector(resize(signed(sumYA(43 downto 22)), 23) + resize(signed(sumYA(21 downto 0)), 23));
					sumXYB <= std_logic_vector(resize(signed(sumXYA(43 downto 22)), 23) + resize(signed(sumXYA(21 downto 0)), 23));
					colsumX4p2 <= colsumX4p1;
					colsumY4p2 <= colsumY4p1;
					colsumXY4p2 <= colsumXY4p1;

					-- stage 8 (replaces sumX, sumY, sumXY); max. sum is of 25 18-bit elements, thus 23 bit result is sufficient
					sumX <= std_logic_vector(signed(sumXB) + resize(signed(colsumX4p2), 23));
					sumY <= std_logic_vector(signed(sumYB) + resize(signed(colsumY4p2), 23));
					sumXY <= std_logic_vector(signed(sumXYB) + resize(signed(colsumXY4p2), 23));

					-- stage 9 (replaces sumIII, termII, termI)
					sumIII <= std_logic_vector(resize(signed(sumX), 24) + resize(signed(sumY), 24));
					termII <= std_logic_vector(signed(sumXY) * signed(sumXY));
					termI <= std_logic_vector(signed(sumX) * signed(sumY));

					-- stage 10 (replaces termIII, diffI_II)
					termIII <= std_logic_vector(signed(sumIII) * signed(sumIII));
					diffI_II <= std_logic_vector(resize(signed(termI), 47) - resize(signed(termII), 47));

					-- stage 11 (replaces FSM factk)
					x := unsigned(std_logic_vector'(std_logic_vector'("0" & termIII) & "00")) + unsigned(std_logic_vector'("000" & termIII)); -- x5
					termIIIk <= std_logic_vector(x(50 downto 7)); -- /128

					diffI_IIp1 <= diffI_II;

					-- stage 12 (replaces r)
					r <= std_logic_vector(resize(signed(diffI_IIp1), 48) - resize(signed(termIIIk), 48));

					-- stage 13 (replaces FSM exp)
					for i in 0 to 47 loop
						if r(i)='1' then
							msb := i;
						end if;
					end loop;

					if linNotLog='0' then
						if msb<2 then
							rexp <= "000000" & r(1 downto 0);
						elsif msb=47 then
							rexp <= (others => '0');
						else
							rexp <= std_logic_vector(to_unsigned(msb-1, 6)) & r(msb-1 downto msb-2);
						end if;

					else
						if (msb<7 or msb=47) then
							rshift <= 0;
						else
							rshift <= msb - 7;
						end if;
	
						if msb=47 then
							rexp <= (others => '0');
						elsif msb<shift then
							rexp <= (others => '0');
						elsif msb>shift+7 then
							rexp <= (others => '1');
						else
							rexp <= r(shift+7 downto shift);
						end if;
					end if;
				end if;
				-- IP impl.score.run --- IEND
			end if;
		end if;
	end process;
	-- IP impl.score.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;


-- file Cputrack_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Cputrack_8c100ea18901433eb4f7c0fdbf115e06 fsmtrack_Easy_v1_0 easy model debug controller implementation
-- copyright: (C) 2023 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 28 Jun 2025
-- IP header --- ABOVE

-- module parameters:
-- trkclk (clock): mclk
-- ratioTrkclk (clock ratio wrt. master clock): 1
-- capts (FSM's to be captured): hostif.op
-- trigs (triggers): trigA;trigB;trigC;trigD
-- sizeSeqbuf (sequence buffer size [kB]): 4

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Cputrack_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		trigA: in std_logic;
		trigB: in std_logic;
		trigC: in std_logic;
		trigD: in std_logic;

		getInfoTixVState: out std_logic_vector(7 downto 0);
		getInfoTCapt: out std_logic_vector(31 downto 0);
		getInfoPtr0Seqbuf: out std_logic_vector(15 downto 0);

		reqInvSelect: in std_logic;
		ackInvSelect: out std_logic;

		selectTixVCapture: in std_logic_vector(7 downto 0);
		selectStaTixVTrigger: in std_logic_vector(7 downto 0);
		selectStaFallingNotRising: in std_logic_vector(7 downto 0);
		selectStoTixVTrigger: in std_logic_vector(7 downto 0);
		selectStoFallingNotRising: in std_logic_vector(7 downto 0);

		reqInvSet: in std_logic;
		ackInvSet: out std_logic;

		setRng: in std_logic_vector(7 downto 0);
		setTCaptMax: in std_logic_vector(31 downto 0);

		reqSeqbufToHostif: in std_logic;
		ackSeqbufToHostif: out std_logic;
		dneSeqbufToHostif: in std_logic;
		avllenSeqbufToHostif: out std_logic_vector(31 downto 0);

		seqbufToHostifAXIS_tready: in std_logic;
		seqbufToHostifAXIS_tvalid: out std_logic;
		seqbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
		seqbufToHostifAXIS_tlast: out std_logic;

		hostifStateOp: in std_logic_vector(7 downto 0)
	);
end Cputrack_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Cputrack_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_size4kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(9 downto 0);
			drdA: out std_logic_vector(31 downto 0);
			dwrA: in std_logic_vector(31 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(9 downto 0);
			drdB: out std_logic_vector(31 downto 0);
			dwrB: in std_logic_vector(31 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant wD: natural := 32;
	constant logWD: natural := 2;

	constant sizeSeqbuf: natural := 4096;
	constant logSizeSeqbuf: natural := 12;

	constant tixVCaptureHostifOp: std_logic_vector(7 downto 0) := x"01";

	constant tixVStateIdle: std_logic_vector(7 downto 0) := x"00";
	constant tixVStateArm: std_logic_vector(7 downto 0) := x"01";
	constant tixVStateAcq: std_logic_vector(7 downto 0) := x"02";
	constant tixVStateDone: std_logic_vector(7 downto 0) := x"03";

	constant tixVTriggerVoid: std_logic_vector(7 downto 0) := x"00";
	constant tixVTriggerTrigA: std_logic_vector(7 downto 0) := x"02";
	constant tixVTriggerTrigB: std_logic_vector(7 downto 0) := x"03";
	constant tixVTriggerTrigC: std_logic_vector(7 downto 0) := x"04";
	constant tixVTriggerTrigD: std_logic_vector(7 downto 0) := x"05";

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv,
		stateOpIdle,
		stateOpStart,
		stateOpRun,
		stateOpStop,
		stateOpClear
	);
	signal stateOp: stateOp_t;

	signal ackInvSelect_sig: std_logic;
	signal ackInvSet_sig: std_logic;

	signal tixVCapture: std_logic_vector(7 downto 0);

	signal staTixVTrigger: std_logic_vector(7 downto 0);
	signal staFallingNotRising: boolean;

	signal stoTixVTrigger: std_logic_vector(7 downto 0);
	signal stoFallingNotRising: boolean;

	signal strbStart: std_logic;
	signal strbStop: std_logic;

	---- sequence operation (seq)
	type stateSeq_t is (
		stateSeqInit,
		stateSeqIdle,
		stateSeqRun,
		stateSeqDone,
		stateSeqClear,
		stateSeqAckClear
	);
	signal stateSeq: stateSeq_t;

	signal rdySeq: std_logic;
	signal dneSeq: std_logic;

	signal TCapt: std_logic_vector(31 downto 0);

	signal ptr0SeqbufTrackNotFixed: std_logic;
	signal ptr0Seqbuf: natural range 0 to sizeSeqbuf/4-1;

	signal enSeqbuf: std_logic;

	signal aSeqbuf: natural range 0 to sizeSeqbuf/4-1;
	signal aSeqbuf_vec: std_logic_vector(logSizeSeqbuf-2-1 downto 0);

	signal dwrSeqbuf: std_logic_vector(31 downto 0);

	---- sequence buffer B/hostif-facing operation (seqbufB)
	type stateSeqbufB_t is (
		stateSeqbufBInit,
		stateSeqbufBIdle,
		stateSeqbufBXferA, stateSeqbufBXferB,
		stateSeqbufBDone,
		stateSeqbufBClear
	);
	signal stateSeqbufB: stateSeqbufB_t;

	signal enSeqbufB: std_logic;

	signal aSeqbufB: natural range 0 to sizeSeqbuf/(wD/8)-1;
	signal aSeqbufB_vec: std_logic_vector(logSizeSeqbuf-logWD-1 downto 0);

	---- sampling operation (sample)
	signal state: std_logic_vector(7 downto 0);

	signal start: std_logic;
	signal stop: std_logic;

	---- handshake

	-- op to (many)
	signal reqOpClear: std_logic;

	-- seqbufB to seq
	signal reqSeqbufBToSeqClear: std_logic;
	signal ackSeqbufBToSeqClear: std_logic;

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	mySeqbuf : Dpbram_size4kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enSeqbuf,
			weA => '1',

			aA => aSeqbuf_vec,
			drdA => open,
			dwrA => dwrSeqbuf,

			rstB => reset,
			clkB => mclk,

			enB => enSeqbufB,
			weB => '0',

			aB => aSeqbufB_vec,
			drdB => seqbufToHostifAXIS_tdata,
			dwrB => (others => '0')
		);

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	ackInvSelect <= ackInvSelect_sig;
	ackInvSet <= ackInvSet_sig;

	getInfoTixVState <= tixVStateArm when stateOp=stateOpIdle
				else tixVStateAcq when stateOp=stateOpRun
				else tixVStateDone when stateOp=stateOpStop
				else tixVStateIdle;
	getInfoTCapt <= TCapt;
	getInfoPtr0Seqbuf <= std_logic_vector(to_unsigned(ptr0Seqbuf, 16));

	strbStart <= '1' when stateOp=stateOpStart else '0';

	reqOpClear <= '1' when stateOp=stateOpClear else '0';

	process (reset, mclk, stateOp)
		variable rng: boolean;
		variable restart: boolean;

		variable TCaptMax: std_logic_vector(31 downto 0);

		variable strb_last: std_logic;

	begin
		if reset='1' then
			stateOp <= stateOpInit;
			ackInvSelect_sig <= '0';
			ackInvSet_sig <= '0';
			tixVCapture <= x"01";
			staTixVTrigger <= tixVTriggerVoid;
			staFallingNotRising <= false;
			stoTixVTrigger <= tixVTriggerVoid;
			stoFallingNotRising <= false;
			strbStop <= '0';

			rng := false;
			restart := false;
			TCaptMax := (others => '0');
			strb_last := '0';

		elsif rising_edge(mclk) then
			if stateOp=stateOpInit or (stateOp/=stateOpInv and (reqInvSelect='1' or reqInvSet='1'))  then
				strbStop <= '0';

				if reqInvSelect='1' then
					tixVCapture <= selectTixVCapture;
					staTixVTrigger <= selectStaTixVTrigger;
					staFallingNotRising <= (selectStaFallingNotRising=tru8);
					stoTixVTrigger <= selectStoTixVTrigger;
					stoFallingNotRising <= (selectStoFallingNotRising=tru8);

					ackInvSelect_sig <= '1';
					stateOp <= stateOpInv;

				elsif reqInvSet='1' then
					if setRng=tru8 then
						rng := true;
					else
						rng := false;
					end if;
					TCaptMax := setTCaptMax;

					ackInvSet_sig <= '1';
					stateOp <= stateOpInv;

				else
					restart := false;

					if rng then
						strb_last := start;

						stateOp <= stateOpIdle;

					else
						stateOp <= stateOpInit;
					end if;
				end if;

			elsif stateOp=stateOpInv then
				if (reqInvSet='0' and ackInvSet_sig='1') or (reqInvSelect='0' and ackInvSelect_sig='1') then
					ackInvSet_sig <= '0';
					ackInvSelect_sig <= '0';

					strbStop <= '1';

					restart := true;

					stateOp <= stateOpStop;
				end if;

			elsif stateOp=stateOpIdle then
				if staTixVTrigger=tixVTriggerVoid or (not staFallingNotRising and strb_last='0' and start='1') or (staFallingNotRising and strb_last='1' and start='0') then
					stateOp <= stateOpStart;
				else
					strb_last := start;
				end if;

			elsif stateOp=stateOpStart then -- strbStart='1'
				strb_last := stop;

				stateOp <= stateOpRun;

			elsif stateOp=stateOpRun then
				if (stoTixVTrigger=tixVTriggerVoid and unsigned(TCaptMax)/=0 and (unsigned(TCapt)>=unsigned(TCaptMax) or dneSeq='1')) or unsigned(TCapt)>=x"FFFFFF00" or (not stoFallingNotRising and strb_last='0' and stop='1') or (stoFallingNotRising and strb_last='1' and stop='0') then
					strbStop <= '1';

					stateOp <= stateOpStop;

				else
					strb_last := stop;
				end if;

			elsif stateOp=stateOpStop then
				strbStop <= '0';

				if restart then
					stateOp <= stateOpClear;

				else
					if rdySeq='1' then
						stateOp <= stateOpInit;
					end if;
				end if;

			elsif stateOp=stateOpClear then -- reqOpClear='1'
				if rdySeq='1' then
					stateOp <= stateOpInit;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: sampling operation (sample)
	------------------------------------------------------------------------

	process (reset, mclk)

	begin
		if reset='1' then
			state <= (others => '1');
			start <= '0';
			stop <= '0';

		elsif rising_edge(mclk) then
			case tixVCapture is
				when tixVCaptureHostifOp =>
					state <= hostifStateOp;
				when others =>
					state <= (others => '1');
			end case;

			case staTixVTrigger is
				when tixVTriggerTrigA =>
					start <= trigA;
				when tixVTriggerTrigB =>
					start <= trigB;
				when tixVTriggerTrigC =>
					start <= trigC;
				when tixVTriggerTrigD =>
					start <= trigD;
				when others =>
					start <= '0';
			end case;

			case stoTixVTrigger is
				when tixVTriggerTrigA =>
					stop <= trigA;
				when tixVTriggerTrigB =>
					stop <= trigB;
				when tixVTriggerTrigC =>
					stop <= trigC;
				when tixVTriggerTrigD =>
					stop <= trigD;
				when others =>
					stop <= '0';
			end case;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: sequence operation (seq)
	------------------------------------------------------------------------

	rdySeq <= '1' when stateSeq=stateSeqIdle else '0';
	dneSeq <= '1' when stateSeq=stateSeqDone else '0';

	ptr0Seqbuf <= aSeqbuf when ptr0SeqbufTrackNotFixed='1' else 0;

	aSeqbuf_vec <= std_logic_vector(to_unsigned(aSeqbuf, logSizeSeqbuf-2));

	ackSeqbufBToSeqClear <= '1' when stateSeq=stateSeqAckClear else '0';

	process (reset, mclk, stateSeq)
		variable quad: std_logic_vector(31 downto 0);

		variable i: natural range 0 to 3;

		variable first: boolean;
		variable stop_lcl: boolean;

		variable burstState: std_logic_vector(7 downto 0);
		variable burstCnt: natural range 0 to 65535;

	begin
		if reset='1' then
			stateSeq <= stateSeqInit;
			TCapt <= (others => '0');
			ptr0SeqbufTrackNotFixed <= '0';
			enSeqbuf <= '0';
			aSeqbuf <= 0;
			dwrSeqbuf <= (others => '0');

			quad := (others => '0');
			i := 0;
			first := true;
			stop_lcl := false;
			burstState := (others => '1');
			burstCnt := 0;

		elsif rising_edge(mclk) then
			if stateSeq=stateSeqInit then
				TCapt <= (others => '0');
				ptr0SeqbufTrackNotFixed <= '0';
				enSeqbuf <= '0';
				aSeqbuf <= 0;
				dwrSeqbuf <= (others => '0');

				quad := (others => '0');
				i := 0;
				first := true;
				stop_lcl := false;
				burstState := (others => '1');
				burstCnt := 0;

				stateSeq <= stateSeqIdle;

			elsif stateSeq=stateSeqIdle then -- rdySeq='1'
				if strbStart='1' then
					stateSeq <= stateSeqRun;
				end if;

			elsif stateSeq=stateSeqRun then
				TCapt <= std_logic_vector(unsigned(TCapt) + 1);

				if strbStop='1' or (stoTixVTrigger=tixVTriggerVoid and (i=0 and aSeqbuf=sizeSeqbuf/4-1)) then
					stop_lcl := true;
				end if;

				quad((i+1)*8-1 downto i*8) := state;

				if i=3 then
					if quad(23 downto 16)=state and quad(15 downto 8)=state and quad(7 downto 0)=state then
						if state/=burstState or burstCnt=65535 then
							if not first then
								if aSeqbuf=sizeSeqbuf/4-1 then
									ptr0SeqbufTrackNotFixed <= '1';
									aSeqbuf <= 0;
								else
									aSeqbuf <= aSeqbuf + 1;
								end if;
							end if;

							burstCnt := 0;
						end if;

						burstState := state;
						burstCnt := burstCnt + 1;

						dwrSeqbuf <= x"FF" & burstState & std_logic_vector(to_unsigned(burstCnt, 16));

					else
						burstState := (others => '1');
						burstCnt := 0;

						if not first then
							if aSeqbuf=sizeSeqbuf/4-1 then
								ptr0SeqbufTrackNotFixed <= '1';
								aSeqbuf <= 0;
							else
								aSeqbuf <= aSeqbuf + 1;
							end if;
						end if;

						dwrSeqbuf <= quad;
					end if;

					enSeqbuf <= '1';

					i := 0;
					first := false;

					stateSeq <= stateSeqRun;

				else
					enSeqbuf <= '0';

					if stop_lcl then
						stateSeq <= stateSeqDone;

					else
						i := i + 1;

						stateSeq <= stateSeqRun;
					end if;
				end if;

			elsif stateSeq=stateSeqDone then
				if reqOpClear='1' or reqSeqbufBToSeqClear='1' then
					aSeqbuf <= 0;
					dwrSeqbuf <= (others => '1');

					stateSeq <= stateSeqClear;
				end if;

			elsif stateSeq=stateSeqClear then
				if aSeqbuf=sizeSeqbuf/4-1 then
					if reqSeqbufBToSeqClear='1' then
						stateSeq <= stateSeqAckClear;
					else
						stateSeq <= stateSeqInit;
					end if;

				else
					aSeqbuf <= aSeqbuf + 1;
				end if;

			elsif stateSeq=stateSeqAckClear then -- ackSeqbufBToSeqClear='1'
				if reqSeqbufBToSeqClear='0' then
					stateSeq <= stateSeqInit;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: sequence buffer B/hostif-facing operation (seqbufB)
	------------------------------------------------------------------------

	ackSeqbufToHostif <= '1' when stateSeqbufB=stateSeqbufBXferA or stateSeqbufB=stateSeqbufBXferB or stateSeqbufB=stateSeqbufBDone else '0';

	avllenSeqbufToHostif <= std_logic_vector(to_unsigned(sizeSeqbuf, 32)) when dneSeq='1'
				else (others => '0');

	seqbufToHostifAXIS_tvalid <= '1' when stateSeqbufB=stateSeqbufBXferB else '0';

	seqbufToHostifAXIS_tlast <= '1' when stateSeqbufB=stateSeqbufBXferB and aSeqbufB=(sizeSeqbuf/(wD/8))-1 else '0';

	enSeqbufB <= '1' when stateSeqbufB=stateSeqbufBXferA else '0';

	aSeqbufB_vec <= std_logic_vector(to_unsigned(aSeqbufB, logSizeSeqbuf-logWD));

	reqSeqbufBToSeqClear <= '1' when stateSeqbufB=stateSeqbufBClear else '0';

	process (reset, mclk, stateSeqbufB)

	begin
		if reset='1' then
			stateSeqbufB <= stateSeqbufBInit;
			aSeqbufB <= 0;

		elsif rising_edge(mclk) then
			if stateSeqbufB=stateSeqbufBInit then
				aSeqbufB <= 0;

				stateSeqbufB <= stateSeqbufBIdle;

			elsif stateSeqbufB=stateSeqbufBIdle then
				if reqSeqbufToHostif='1' then
					stateSeqbufB <= stateSeqbufBXferA;
				end if;

			elsif stateSeqbufB=stateSeqbufBXferA then -- enSeqbufB='1'
				stateSeqbufB <= stateSeqbufBXferB;
				
			elsif stateSeqbufB=stateSeqbufBXferB then -- seqbufToHostifAXIS_tvalid='1'
				if seqbufToHostifAXIS_tready='1' then
					if aSeqbufB=(sizeSeqbuf/(wD/8))-1 then
						stateSeqbufB <= stateSeqbufBDone;

					else
						aSeqbufB <= aSeqbufB + 1;

						stateSeqbufB <= stateSeqbufBXferA;
					end if;

				elsif reqSeqbufToHostif='0' then
					stateSeqbufB <= stateSeqbufBInit;
				end if;

			elsif stateSeqbufB=stateSeqbufBDone then
				if dneSeqbufToHostif='1' then
					stateSeqbufB <= stateSeqbufBClear;

				elsif reqSeqbufToHostif='0' then
					stateSeqbufB <= stateSeqbufBInit;
				end if ;

			elsif stateSeqbufB=stateSeqbufBClear then -- reqSeqbufBToSeqClear='1'
				if reqSeqbufToHostif='0' and ackSeqbufBToSeqClear='1' then
					stateSeqbufB <= stateSeqbufBInit;
				end if;
			end if;
		end if;
	end process;

end Rtl;


-- file Crc8005_32_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Crc8005_32_8c100ea18901433eb4f7c0fdbf115e06 crcspec_v3_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 28 Jun 2025
-- IP header --- ABOVE

-- module parameters:
-- poly (polynomial): 8005
-- wD (data width 8/16/32/64/128 [bit]): 32
-- leNotBe (endianness): true

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Crc8005_32_8c100ea18901433eb4f7c0fdbf115e06 is
	generic (
		initInvert: boolean := false;
		byteFlip: boolean := false;
		outFlip: boolean := false;
		outInvert: boolean := false
	);
	port (
		reset: in std_logic;
		mclk: in std_logic;

		AXIS_tready: out std_logic;
		AXIS_tvalid: in std_logic;
		AXIS_tdata: in std_logic_vector(31 downto 0);
		AXIS_tkeep: in std_logic_vector(3 downto 0);
		AXIS_tlast: in std_logic;

		crc: out std_logic_vector(15 downto 0);
		validCrc: out std_logic
	);
end Crc8005_32_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Crc8005_32_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant wPoly: natural := 16;
	constant wD: natural := 32;

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpCapt
	);
	signal stateOp: stateOp_t;

	signal word_imd: std_logic_vector(wD-1 downto 0);
	signal word: std_logic_vector(wD-1 downto 0);

	signal crc_imd: std_logic_vector(wPoly-1 downto 0);
	signal crc_sig: std_logic_vector(wPoly-1 downto 0);

	signal validCrc_sig: std_logic;

	signal first: std_logic;

begin

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	AXIS_tready <= '1' when stateOp=stateOpCapt else '0';

	gen_word: for i in 0 to wD/8-1 generate
		gen_byte: for j in 0 to 7 generate
			word(8*i+j) <= word_imd(8*i+(8-j-1)) when byteFlip else word_imd(8*i+j);
		end generate;
	end generate;
	word_imd(wD-1 downto wPoly) <= AXIS_tdata(wD-1 downto wPoly);
	word_imd(wPoly-1 downto 0) <= not AXIS_tdata(wPoly-1 downto 0) when initInvert and first='1' else AXIS_tdata(wPoly-1 downto 0);

	crc <= not crc_sig when outInvert else crc_sig;

	gen_crc: for i in 0 to wPoly-1 generate
		crc_sig(i) <= crc_imd(wPoly-i-1) when outFlip else crc_imd(i);
	end generate;

	validCrc <= validCrc_sig;
	
	process (reset, mclk, stateOp)

	begin
		if reset='1' then
			stateOp <= stateOpInit;

			crc_imd <= (others => '0');

			validCrc_sig <= '0';

			first <= '1';

		elsif rising_edge(mclk) then
			if stateOp=stateOpInit then
				if AXIS_tlast='0' then
					crc_imd <= (others => '0');

					validCrc_sig <= '0';

					first <= '1';

					stateOp <= stateOpCapt;
				end if;

			elsif stateOp=stateOpCapt then
				if AXIS_tvalid='1' and (first='1' or validCrc_sig='1') then
					case AXIS_tkeep is
						when "1111" =>
							crc_imd(15) <= word(7) xor word(6) xor word(5) xor word(2) xor word(1) xor word(0) xor word(15) xor word(14) xor word(13) xor word(12) xor word(11) xor word(10) xor word(9) xor word(8) xor word(23) xor word(22) xor word(20) xor word(19) xor word(18) xor word(17) xor word(16) xor word(31) xor word(30) xor word(29) xor word(28) xor word(27) xor word(26) xor word(25) xor word(24) xor crc_imd(0) xor crc_imd(1) xor crc_imd(2) xor crc_imd(3) xor crc_imd(4) xor crc_imd(5) xor crc_imd(6) xor crc_imd(7) xor crc_imd(8) xor crc_imd(9) xor crc_imd(10) xor crc_imd(13) xor crc_imd(14) xor crc_imd(15);
							crc_imd(14) <= word(4) xor word(2) xor word(21) xor word(20) xor crc_imd(10) xor crc_imd(12);
							crc_imd(13) <= word(3) xor word(1) xor word(20) xor word(19) xor crc_imd(9) xor crc_imd(11);
							crc_imd(12) <= word(2) xor word(0) xor word(19) xor word(18) xor crc_imd(8) xor crc_imd(10);
							crc_imd(11) <= word(1) xor word(15) xor word(18) xor word(17) xor crc_imd(7) xor crc_imd(9);
							crc_imd(10) <= word(0) xor word(14) xor word(17) xor word(16) xor crc_imd(6) xor crc_imd(8);
							crc_imd(9) <= word(15) xor word(13) xor word(16) xor word(31) xor crc_imd(5) xor crc_imd(7);
							crc_imd(8) <= word(14) xor word(12) xor word(31) xor word(30) xor crc_imd(4) xor crc_imd(6);
							crc_imd(7) <= word(13) xor word(11) xor word(30) xor word(29) xor crc_imd(3) xor crc_imd(5);
							crc_imd(6) <= word(12) xor word(10) xor word(29) xor word(28) xor crc_imd(2) xor crc_imd(4);
							crc_imd(5) <= word(7) xor word(11) xor word(9) xor word(28) xor word(27) xor crc_imd(1) xor crc_imd(3) xor crc_imd(15);
							crc_imd(4) <= word(7) xor word(6) xor word(10) xor word(8) xor word(27) xor word(26) xor crc_imd(0) xor crc_imd(2) xor crc_imd(14) xor crc_imd(15);
							crc_imd(3) <= word(7) xor word(6) xor word(5) xor word(9) xor word(23) xor word(26) xor word(25) xor crc_imd(1) xor crc_imd(13) xor crc_imd(14) xor crc_imd(15);
							crc_imd(2) <= word(7) xor word(6) xor word(5) xor word(4) xor word(8) xor word(22) xor word(25) xor word(24) xor crc_imd(0) xor crc_imd(12) xor crc_imd(13) xor crc_imd(14) xor crc_imd(15);
							crc_imd(1) <= word(7) xor word(4) xor word(3) xor word(2) xor word(1) xor word(0) xor word(15) xor word(14) xor word(13) xor word(12) xor word(11) xor word(10) xor word(9) xor word(8) xor word(22) xor word(21) xor word(20) xor word(19) xor word(18) xor word(17) xor word(16) xor word(31) xor word(30) xor word(29) xor word(28) xor word(27) xor word(26) xor word(25) xor crc_imd(0) xor crc_imd(1) xor crc_imd(2) xor crc_imd(3) xor crc_imd(4) xor crc_imd(5) xor crc_imd(6) xor crc_imd(7) xor crc_imd(8) xor crc_imd(9) xor crc_imd(10) xor crc_imd(11) xor crc_imd(12) xor crc_imd(15);
							crc_imd(0) <= word(7) xor word(6) xor word(3) xor word(2) xor word(1) xor word(0) xor word(15) xor word(14) xor word(13) xor word(12) xor word(11) xor word(10) xor word(9) xor word(8) xor word(23) xor word(21) xor word(20) xor word(19) xor word(18) xor word(17) xor word(16) xor word(31) xor word(30) xor word(29) xor word(28) xor word(27) xor word(26) xor word(25) xor word(24) xor crc_imd(0) xor crc_imd(1) xor crc_imd(2) xor crc_imd(3) xor crc_imd(4) xor crc_imd(5) xor crc_imd(6) xor crc_imd(7) xor crc_imd(8) xor crc_imd(9) xor crc_imd(10) xor crc_imd(11) xor crc_imd(14) xor crc_imd(15);
							validCrc_sig <= '1';
						when "0111" =>
							crc_imd(15) <= word(7) xor word(6) xor word(5) xor word(4) xor word(3) xor word(2) xor word(1) xor word(0) xor word(15) xor word(14) xor word(12) xor word(11) xor word(10) xor word(9) xor word(8) xor word(23) xor word(22) xor word(21) xor word(20) xor word(19) xor word(18) xor word(17) xor word(16) xor crc_imd(0) xor crc_imd(1) xor crc_imd(2) xor crc_imd(3) xor crc_imd(4) xor crc_imd(6) xor crc_imd(7) xor crc_imd(8) xor crc_imd(9) xor crc_imd(10) xor crc_imd(11) xor crc_imd(12) xor crc_imd(13) xor crc_imd(14) xor crc_imd(15);
							crc_imd(14) <= word(13) xor word(12) xor crc_imd(4) xor crc_imd(5);
							crc_imd(13) <= word(12) xor word(11) xor crc_imd(3) xor crc_imd(4);
							crc_imd(12) <= word(11) xor word(10) xor crc_imd(2) xor crc_imd(3);
							crc_imd(11) <= word(7) xor word(10) xor word(9) xor crc_imd(1) xor crc_imd(2) xor crc_imd(15);
							crc_imd(10) <= word(6) xor word(9) xor word(8) xor crc_imd(0) xor crc_imd(1) xor crc_imd(14);
							crc_imd(9) <= word(7) xor word(5) xor word(8) xor word(23) xor crc_imd(0) xor crc_imd(13) xor crc_imd(15);
							crc_imd(8) <= word(6) xor word(4) xor word(23) xor word(22) xor crc_imd(12) xor crc_imd(14);
							crc_imd(7) <= word(5) xor word(3) xor word(22) xor word(21) xor crc_imd(11) xor crc_imd(13);
							crc_imd(6) <= word(4) xor word(2) xor word(21) xor word(20) xor crc_imd(10) xor crc_imd(12);
							crc_imd(5) <= word(3) xor word(1) xor word(20) xor word(19) xor crc_imd(9) xor crc_imd(11);
							crc_imd(4) <= word(2) xor word(0) xor word(19) xor word(18) xor crc_imd(8) xor crc_imd(10);
							crc_imd(3) <= word(1) xor word(15) xor word(18) xor word(17) xor crc_imd(7) xor crc_imd(9);
							crc_imd(2) <= word(0) xor word(14) xor word(17) xor word(16) xor crc_imd(6) xor crc_imd(8);
							crc_imd(1) <= word(7) xor word(6) xor word(5) xor word(4) xor word(3) xor word(2) xor word(1) xor word(0) xor word(14) xor word(13) xor word(12) xor word(11) xor word(10) xor word(9) xor word(8) xor word(23) xor word(22) xor word(21) xor word(20) xor word(19) xor word(18) xor word(17) xor crc_imd(0) xor crc_imd(1) xor crc_imd(2) xor crc_imd(3) xor crc_imd(4) xor crc_imd(5) xor crc_imd(6) xor crc_imd(8) xor crc_imd(9) xor crc_imd(10) xor crc_imd(11) xor crc_imd(12) xor crc_imd(13) xor crc_imd(14) xor crc_imd(15);
							crc_imd(0) <= word(7) xor word(6) xor word(5) xor word(4) xor word(3) xor word(2) xor word(1) xor word(0) xor word(15) xor word(13) xor word(12) xor word(11) xor word(10) xor word(9) xor word(8) xor word(23) xor word(22) xor word(21) xor word(20) xor word(19) xor word(18) xor word(17) xor word(16) xor crc_imd(0) xor crc_imd(1) xor crc_imd(2) xor crc_imd(3) xor crc_imd(4) xor crc_imd(5) xor crc_imd(7) xor crc_imd(8) xor crc_imd(9) xor crc_imd(10) xor crc_imd(11) xor crc_imd(12) xor crc_imd(13) xor crc_imd(14) xor crc_imd(15);
							validCrc_sig <= '1';
						when "0011" =>
							crc_imd(15) <= word(7) xor word(6) xor word(4) xor word(3) xor word(2) xor word(1) xor word(0) xor word(15) xor word(14) xor word(13) xor word(12) xor word(11) xor word(10) xor word(9) xor word(8) xor crc_imd(0) xor crc_imd(1) xor crc_imd(2) xor crc_imd(3) xor crc_imd(4) xor crc_imd(5) xor crc_imd(6) xor crc_imd(7) xor crc_imd(8) xor crc_imd(9) xor crc_imd(10) xor crc_imd(11) xor crc_imd(12) xor crc_imd(14) xor crc_imd(15);
							crc_imd(14) <= word(5) xor word(4) xor crc_imd(12) xor crc_imd(13);
							crc_imd(13) <= word(4) xor word(3) xor crc_imd(11) xor crc_imd(12);
							crc_imd(12) <= word(3) xor word(2) xor crc_imd(10) xor crc_imd(11);
							crc_imd(11) <= word(2) xor word(1) xor crc_imd(9) xor crc_imd(10);
							crc_imd(10) <= word(1) xor word(0) xor crc_imd(8) xor crc_imd(9);
							crc_imd(9) <= word(0) xor word(15) xor crc_imd(7) xor crc_imd(8);
							crc_imd(8) <= word(15) xor word(14) xor crc_imd(6) xor crc_imd(7);
							crc_imd(7) <= word(14) xor word(13) xor crc_imd(5) xor crc_imd(6);
							crc_imd(6) <= word(13) xor word(12) xor crc_imd(4) xor crc_imd(5);
							crc_imd(5) <= word(12) xor word(11) xor crc_imd(3) xor crc_imd(4);
							crc_imd(4) <= word(11) xor word(10) xor crc_imd(2) xor crc_imd(3);
							crc_imd(3) <= word(7) xor word(10) xor word(9) xor crc_imd(1) xor crc_imd(2) xor crc_imd(15);
							crc_imd(2) <= word(6) xor word(9) xor word(8) xor crc_imd(0) xor crc_imd(1) xor crc_imd(14);
							crc_imd(1) <= word(6) xor word(5) xor word(4) xor word(3) xor word(2) xor word(1) xor word(0) xor word(15) xor word(14) xor word(13) xor word(12) xor word(11) xor word(10) xor word(9) xor crc_imd(1) xor crc_imd(2) xor crc_imd(3) xor crc_imd(4) xor crc_imd(5) xor crc_imd(6) xor crc_imd(7) xor crc_imd(8) xor crc_imd(9) xor crc_imd(10) xor crc_imd(11) xor crc_imd(12) xor crc_imd(13) xor crc_imd(14);
							crc_imd(0) <= word(7) xor word(5) xor word(4) xor word(3) xor word(2) xor word(1) xor word(0) xor word(15) xor word(14) xor word(13) xor word(12) xor word(11) xor word(10) xor word(9) xor word(8) xor crc_imd(0) xor crc_imd(1) xor crc_imd(2) xor crc_imd(3) xor crc_imd(4) xor crc_imd(5) xor crc_imd(6) xor crc_imd(7) xor crc_imd(8) xor crc_imd(9) xor crc_imd(10) xor crc_imd(11) xor crc_imd(12) xor crc_imd(13) xor crc_imd(15);
							validCrc_sig <= '1';
						when "0001" =>
							crc_imd(15) <= word(7) xor word(6) xor word(5) xor word(4) xor word(3) xor word(2) xor word(1) xor word(0) xor crc_imd(7) xor crc_imd(8) xor crc_imd(9) xor crc_imd(10) xor crc_imd(11) xor crc_imd(12) xor crc_imd(13) xor crc_imd(14) xor crc_imd(15);
							crc_imd(14) <= crc_imd(6);
							crc_imd(13) <= crc_imd(5);
							crc_imd(12) <= crc_imd(4);
							crc_imd(11) <= crc_imd(3);
							crc_imd(10) <= crc_imd(2);
							crc_imd(9) <= word(7) xor crc_imd(1) xor crc_imd(15);
							crc_imd(8) <= word(7) xor word(6) xor crc_imd(0) xor crc_imd(14) xor crc_imd(15);
							crc_imd(7) <= word(6) xor word(5) xor crc_imd(13) xor crc_imd(14);
							crc_imd(6) <= word(5) xor word(4) xor crc_imd(12) xor crc_imd(13);
							crc_imd(5) <= word(4) xor word(3) xor crc_imd(11) xor crc_imd(12);
							crc_imd(4) <= word(3) xor word(2) xor crc_imd(10) xor crc_imd(11);
							crc_imd(3) <= word(2) xor word(1) xor crc_imd(9) xor crc_imd(10);
							crc_imd(2) <= word(1) xor word(0) xor crc_imd(8) xor crc_imd(9);
							crc_imd(1) <= word(7) xor word(6) xor word(5) xor word(4) xor word(3) xor word(2) xor word(1) xor crc_imd(9) xor crc_imd(10) xor crc_imd(11) xor crc_imd(12) xor crc_imd(13) xor crc_imd(14) xor crc_imd(15);
							crc_imd(0) <= word(7) xor word(6) xor word(5) xor word(4) xor word(3) xor word(2) xor word(1) xor word(0) xor crc_imd(8) xor crc_imd(9) xor crc_imd(10) xor crc_imd(11) xor crc_imd(12) xor crc_imd(13) xor crc_imd(14) xor crc_imd(15);
							validCrc_sig <= '1';
						when others =>
							validCrc_sig <= '0';
					end case;

					first <= '0';

					if AXIS_tlast='1' then
						stateOp <= stateOpInit;
					end if;

				elsif AXIS_tlast='1' then
					validCrc_sig <= '0';

					stateOp <= stateOpInit;
				end if;
			end if;
		end if;
	end process;

end Rtl;


-- file Ddrif_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Ddrif_8c100ea18901433eb4f7c0fdbf115e06 ddrmux_Easy_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

-- module parameters:
-- memclkIntNotExt (memory clock origin): false
-- fMemclk: 250000
-- wA (AXI address width [bit]): 33
-- wAConst (constant portion of AXI address width [bit]): 7
-- aConst (constant portion of AXI address): 0000001
-- wD (AXI data width 128/512 [bit]): 512
-- NRd (number of read channels): 2
-- flexNBeatRds (read channel flexible beats per burst): false;false
-- NBeatRd (number of beats per read burst): 4
-- wDRds (read channel data widths <= wD [bit]): 128;128
-- clkRds (read channel clocks): memclk;memclk
-- ratioClkRds (read channel clock ratios wrt. memory clock): 1.0;1.0
-- NWr (number of write channels): 2
-- flexNBeatWrs (write channel flexible beats per burst): false;false
-- NBeatWr (number of beats per read burst): 4
-- wDWrs (write channel data widths <= wD [bit]): 128;128
-- clkWrs (write channel clocks): memclk;memclk
-- ratioClkWrs (write channel clock ratios wrt. memory clock): 1.0;1.0
-- phyNotAxi (interface level): false
-- wAPhy (PHY address width [bit]): 20
-- wDPhy (PHY data width [bit]): 16
-- memclk (memory clock): memclk
-- ratioMemclk (memory clock ratio wrt. master clock): 5.33

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Ddrif_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		resetMemclk: in std_logic;
		memclk: in std_logic;

		tkclk: in std_logic;

		getStatsNRdA: out std_logic_vector(31 downto 0);
		getStatsNRdB: out std_logic_vector(31 downto 0);
		getStatsNWrA: out std_logic_vector(31 downto 0);
		getStatsNWrB: out std_logic_vector(31 downto 0);

		reqRdA: in std_logic;
		ackRdA: out std_logic;

		rdAAXI_araddr: in std_logic_vector(17 downto 0);
		rdAAXI_arready: out std_logic;
		rdAAXI_arvalid: in std_logic;
		rdAAXI_rdata: out std_logic_vector(127 downto 0);
		rdAAXI_rlast: out std_logic;
		rdAAXI_rready: in std_logic;
		rdAAXI_rresp: out std_logic_vector(1 downto 0);
		rdAAXI_rvalid: out std_logic;

		reqRdB: in std_logic;
		ackRdB: out std_logic;

		rdBAXI_araddr: in std_logic_vector(17 downto 0);
		rdBAXI_arready: out std_logic;
		rdBAXI_arvalid: in std_logic;
		rdBAXI_rdata: out std_logic_vector(127 downto 0);
		rdBAXI_rlast: out std_logic;
		rdBAXI_rready: in std_logic;
		rdBAXI_rresp: out std_logic_vector(1 downto 0);
		rdBAXI_rvalid: out std_logic;

		reqWrA: in std_logic;
		ackWrA: out std_logic;

		wrAAXI_awaddr: in std_logic_vector(17 downto 0);
		wrAAXI_awready: out std_logic;
		wrAAXI_awvalid: in std_logic;
		wrAAXI_wdata: in std_logic_vector(127 downto 0);
		wrAAXI_wlast: in std_logic;
		wrAAXI_wready: out std_logic;
		wrAAXI_wvalid: in std_logic;

		reqWrB: in std_logic;
		ackWrB: out std_logic;

		wrBAXI_awaddr: in std_logic_vector(17 downto 0);
		wrBAXI_awready: out std_logic;
		wrBAXI_awvalid: in std_logic;
		wrBAXI_wdata: in std_logic_vector(127 downto 0);
		wrBAXI_wlast: in std_logic;
		wrBAXI_wready: out std_logic;
		wrBAXI_wvalid: in std_logic;

		ddrAXI_arid: out std_logic_vector(5 downto 0);
		ddrAXI_araddr: out std_logic_vector(32 downto 0);
		ddrAXI_arburst: out std_logic_vector(1 downto 0);
		ddrAXI_arcache: out std_logic_vector(3 downto 0);
		ddrAXI_arlen: out std_logic_vector(7 downto 0);
		ddrAXI_arlock: out std_logic_vector(0 downto 0);
		ddrAXI_arprot: out std_logic_vector(2 downto 0);
		ddrAXI_arqos: out std_logic_vector(3 downto 0);
		ddrAXI_arready: in std_logic;
		ddrAXI_arregion: out std_logic_vector(3 downto 0);
		ddrAXI_arsize: out std_logic_vector(2 downto 0);
		ddrAXI_arvalid: out std_logic;

		ddrAXI_rid: in std_logic_vector(5 downto 0);
		ddrAXI_rdata: in std_logic_vector(511 downto 0);
		ddrAXI_rlast: in std_logic;
		ddrAXI_rready: out std_logic;
		ddrAXI_rresp: in std_logic_vector(1 downto 0);
		ddrAXI_rvalid: in std_logic;

		ddrAXI_awid: out std_logic_vector(5 downto 0);
		ddrAXI_awaddr: out std_logic_vector(32 downto 0);
		ddrAXI_awburst: out std_logic_vector(1 downto 0);
		ddrAXI_awcache: out std_logic_vector(3 downto 0);
		ddrAXI_awlen: out std_logic_vector(7 downto 0);
		ddrAXI_awlock: out std_logic_vector(0 downto 0);
		ddrAXI_awprot: out std_logic_vector(2 downto 0);
		ddrAXI_awqos: out std_logic_vector(3 downto 0);
		ddrAXI_awready: in std_logic;
		ddrAXI_awregion: out std_logic_vector(3 downto 0);
		ddrAXI_awsize: out std_logic_vector(2 downto 0);
		ddrAXI_awvalid: out std_logic;

		ddrAXI_wdata: out std_logic_vector(511 downto 0);
		ddrAXI_wlast: out std_logic;
		ddrAXI_wready: in std_logic;
		ddrAXI_wstrb: out std_logic_vector(63 downto 0);
		ddrAXI_wvalid: out std_logic;

		ddrAXI_bid: in std_logic_vector(5 downto 0);
		ddrAXI_bready: out std_logic;
		ddrAXI_bresp: in std_logic_vector(1 downto 0);
		ddrAXI_bvalid: in std_logic
	);
end Ddrif_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Ddrif_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant wD: natural := 512;

	constant NBeatRd: natural := 4;
	constant NBeatWr: natural := 4;

	---- rdA geared egress operation (rdAGearEgr)
	type stateRdAGearEgr_t is (
		stateRdAGearEgrInit,
		stateRdAGearEgrIdle,
		stateRdAGearEgrAddr,
		stateRdAGearEgrWaitFull,
		stateRdAGearEgrXfer
	);
	signal stateRdAGearEgr: stateRdAGearEgr_t;

	constant rdAWD: natural := 128;

	signal rdAAXI_rdata_oprt: std_logic_vector(rdAWD-1 downto 0);
	signal rdAAXI_rlast_oprt: std_logic;

	signal rdAReady: boolean;
	signal rdAA: std_logic_vector(17 downto 0);

	-- IP sigs.rdAGearEgr.cust --- INSERT

	---- rdA geared ingress operation (rdAGearIgr)
	type stateRdAGearIgr_t is (
		stateRdAGearIgrInit,
		stateRdAGearIgrIdle,
		stateRdAGearIgrAddr,
		stateRdAGearIgrXfer
	);
	signal stateRdAGearIgr: stateRdAGearIgr_t;

	signal reqRdA_sig: std_logic;

	signal rdAAXI_araddr_sig: std_logic_vector(17 downto 0);
	signal rdAAXI_arvalid_sig: std_logic;
	signal rdAAXI_rready_sig: std_logic;

	signal rdAFull: boolean;
	type rdbuf_t is array (0 to NBeatRd-1) of std_logic_vector(wD-1 downto 0);
	signal rdABuf: rdbuf_t;

	-- IP sigs.rdAGearIgr.cust --- INSERT

	---- rdB geared egress operation (rdBGearEgr)
	type stateRdBGearEgr_t is (
		stateRdBGearEgrInit,
		stateRdBGearEgrIdle,
		stateRdBGearEgrAddr,
		stateRdBGearEgrWaitFull,
		stateRdBGearEgrXfer
	);
	signal stateRdBGearEgr: stateRdBGearEgr_t;

	constant rdBWD: natural := 128;

	signal rdBAXI_rdata_oprt: std_logic_vector(rdBWD-1 downto 0);
	signal rdBAXI_rlast_oprt: std_logic;

	signal rdBReady: boolean;
	signal rdBA: std_logic_vector(17 downto 0);

	-- IP sigs.rdBGearEgr.cust --- INSERT

	---- rdB geared ingress operation (rdBGearIgr)
	type stateRdBGearIgr_t is (
		stateRdBGearIgrInit,
		stateRdBGearIgrIdle,
		stateRdBGearIgrAddr,
		stateRdBGearIgrXfer
	);
	signal stateRdBGearIgr: stateRdBGearIgr_t;

	signal reqRdB_sig: std_logic;

	signal rdBAXI_araddr_sig: std_logic_vector(17 downto 0);
	signal rdBAXI_arvalid_sig: std_logic;
	signal rdBAXI_rready_sig: std_logic;

	signal rdBFull: boolean;
	signal rdBBuf: rdbuf_t;

	-- IP sigs.rdBGearIgr.cust --- INSERT

	---- read access negotiation (read)
	type stateRead_t is (
		stateReadInit,
		stateReadIdle,
		stateReadLocked
	);
	signal stateRead: stateRead_t;

	constant NRd: natural := 2;

	signal ddrAXI_arlen_sig: std_logic_vector(7 downto 0);
	signal ddrAXI_arvalid_sig: std_logic;

	signal ddrAXI_rready_sig: std_logic;
	signal abRd: natural range 0 to NRd-1;
	signal ackRd: std_logic;

	signal ackRdA_sig: std_logic;
	signal ackRdB_sig: std_logic;

	type mutex_t is (mutexIdle, mutexA, mutexB);
	signal rdmutex: mutex_t;
	signal strbRdlock: std_logic;

	type rdid_t is array (0 to 31) of mutex_t;
	signal rdid: rdid_t;
	signal ixRdid: natural range 0 to 31;
	signal ixRdidEgr: natural range 0 to 31;

	signal rdAAXI_arready_sig: std_logic;
	signal rdAAXI_rdata_sig: std_logic_vector(511 downto 0);
	signal rdAAXI_rlast_sig: std_logic;
	signal rdAAXI_rresp_sig: std_logic_vector(1 downto 0);
	signal rdAAXI_rvalid_sig: std_logic;

	signal rdBAXI_arready_sig: std_logic;
	signal rdBAXI_rdata_sig: std_logic_vector(511 downto 0);
	signal rdBAXI_rlast_sig: std_logic;
	signal rdBAXI_rresp_sig: std_logic_vector(1 downto 0);
	signal rdBAXI_rvalid_sig: std_logic;

	-- IP sigs.read.cust --- INSERT

	---- accumulate statistics (stats)
	type stateStats_t is (
		stateStatsCollectA, stateStatsCollectB
	);
	signal stateStats: stateStats_t;

	signal NRdA: std_logic_vector(31 downto 0);
	signal NRdB: std_logic_vector(31 downto 0);
	signal NWrA: std_logic_vector(31 downto 0);
	signal NWrB: std_logic_vector(31 downto 0);

	-- IP sigs.stats.cust --- INSERT

	---- wrA geared egress operation (wrAGearEgr)
	type stateWrAGearEgr_t is (
		stateWrAGearEgrInit,
		stateWrAGearEgrIdle,
		stateWrAGearEgrXfer
	);
	signal stateWrAGearEgr: stateWrAGearEgr_t;

	constant wrAWD: natural := 128;
	signal reqWrA_sig: std_logic;

	signal wrAAXI_awaddr_sig: std_logic_vector(17 downto 0);
	signal wrAAXI_awvalid_sig: std_logic;
	signal wrAAXI_wdata_sig: std_logic_vector(511 downto 0);
	signal wrAAXI_wlast_sig: std_logic;
	signal wrAAXI_wvalid_sig: std_logic;

	signal wrADoneA: boolean;
	signal wrADoneB: boolean;

	-- IP sigs.wrAGearEgr.cust --- INSERT

	---- wrA geared ingress operation (wrAGearIgr)
	type stateWrAGearIgr_t is (
		stateWrAGearIgrInit,
		stateWrAGearIgrIdle,
		stateWrAGearIgrAddr,
		stateWrAGearIgrXfer
	);
	signal stateWrAGearIgr: stateWrAGearIgr_t;

	signal wrAFillBNotA: boolean;

	signal wrAFullA: boolean;
	signal wrAFullB: boolean;

	signal wrAAa: std_logic_vector(17 downto 0);
	type wrbuf_t is array (0 to NBeatWr-1) of std_logic_vector(wD-1 downto 0);
	signal wrAAbuf: wrbuf_t;

	signal wrABa: std_logic_vector(17 downto 0);
	signal wrABbuf: wrbuf_t;

	-- IP sigs.wrAGearIgr.cust --- INSERT

	---- wrB geared egress operation (wrBGearEgr)
	type stateWrBGearEgr_t is (
		stateWrBGearEgrInit,
		stateWrBGearEgrIdle,
		stateWrBGearEgrXfer
	);
	signal stateWrBGearEgr: stateWrBGearEgr_t;

	constant wrBWD: natural := 128;
	signal reqWrB_sig: std_logic;

	signal wrBAXI_awaddr_sig: std_logic_vector(17 downto 0);
	signal wrBAXI_awvalid_sig: std_logic;
	signal wrBAXI_wdata_sig: std_logic_vector(511 downto 0);
	signal wrBAXI_wlast_sig: std_logic;
	signal wrBAXI_wvalid_sig: std_logic;

	signal wrBDoneA: boolean;
	signal wrBDoneB: boolean;

	-- IP sigs.wrBGearEgr.cust --- INSERT

	---- wrB geared ingress operation (wrBGearIgr)
	type stateWrBGearIgr_t is (
		stateWrBGearIgrInit,
		stateWrBGearIgrIdle,
		stateWrBGearIgrAddr,
		stateWrBGearIgrXfer
	);
	signal stateWrBGearIgr: stateWrBGearIgr_t;

	signal wrBFillBNotA: boolean;

	signal wrBFullA: boolean;
	signal wrBFullB: boolean;

	signal wrBAa: std_logic_vector(17 downto 0);
	signal wrBAbuf: wrbuf_t;

	signal wrBBa: std_logic_vector(17 downto 0);
	signal wrBBbuf: wrbuf_t;

	-- IP sigs.wrBGearIgr.cust --- INSERT

	---- write access negotiation (write)
	type stateWrite_t is (
		stateWriteInit,
		stateWriteIdle,
		stateWriteLocked
	);
	signal stateWrite: stateWrite_t;

	constant NWr: natural := 2;
	constant wtrmax: natural := 16;

	signal ddrAXI_awlen_sig: std_logic_vector(7 downto 0);
	signal ddrAXI_awvalid_sig: std_logic;

	signal ddrAXI_wlast_sig: std_logic;
	signal ddrAXI_wvalid_sig: std_logic;

	signal ddrAXI_bready_sig: std_logic;
	signal wtr: natural range 0 to wtrmax;
	signal abWr: natural range 0 to NWr-1;
	signal ackWr: std_logic;

	signal ackWrA_sig: std_logic;
	signal ackWrB_sig: std_logic;

	signal wrmutex: mutex_t;
	signal strbWrlock: std_logic;

	signal wrAAXI_awready_sig: std_logic;
	signal wrAAXI_wready_sig: std_logic;

	signal wrBAXI_awready_sig: std_logic;
	signal wrBAXI_wready_sig: std_logic;

	-- IP sigs.write.cust --- INSERT

	---- memclk to mclk CDC sampling (memclkToMclkSample)

	signal strbRdlock_mclk: std_logic;
	signal strbRdlock_to_mclkm1: std_logic;
	signal strbRdlock_to_mclkm2: std_logic;
	signal strbWrlock_mclk: std_logic;
	signal strbWrlock_to_mclkm1: std_logic;
	signal strbWrlock_to_mclkm2: std_logic;

	-- IP sigs.memclkToMclkSample.cust --- INSERT

	---- memclk to mclk CDC stretching (memclkToMclkStretch)

	signal strbRdlock_to_mclk: std_logic;
	signal strbWrlock_to_mclk: std_logic;

	-- IP sigs.memclkToMclkStretch.cust --- INSERT

	---- other
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- implementation: rdA geared egress operation (rdAGearEgr)
	------------------------------------------------------------------------

	-- IP impl.rdAGearEgr.wiring --- BEGIN
	ackRdA <= '1' when (stateRdAGearEgr=stateRdAGearEgrAddr or stateRdAGearEgr=stateRdAGearEgrWaitFull or stateRdAGearEgr=stateRdAGearEgrXfer) else '0';

	rdAAXI_arready <= '1' when stateRdAGearEgr=stateRdAGearEgrAddr else '0';
	rdAAXI_rdata <= rdAAXI_rdata_oprt;
	rdAAXI_rlast <= rdAAXI_rlast_oprt;
	rdAAXI_rvalid <= '1' when stateRdAGearEgr=stateRdAGearEgrXfer else '0';
	-- IP impl.rdAGearEgr.wiring --- END

	-- IP impl.rdAGearEgr.wiring.cust --- LINE

	-- IP impl.rdAGearEgr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.rdAGearEgr.vars --- BEGIN
		variable i: natural range 0 to NBeatRd-1;

		constant jmax: natural := wD/rdAWD-1;
		variable j: natural range 0 to jmax;
		-- IP impl.rdAGearEgr.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.rdAGearEgr.asyncrst --- BEGIN
			stateRdAGearEgr <= stateRdAGearEgrInit;
			rdAAXI_rdata_oprt <= (others => '0');
			rdAAXI_rlast_oprt <= '1';
			rdAReady <= false;
			rdAA <= (others => '0');

			i := 0;
			j := 0;
			-- IP impl.rdAGearEgr.asyncrst --- END
			-- IP impl.rdAGearEgr.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if stateRdAGearEgr=stateRdAGearEgrInit then
				-- IP impl.rdAGearEgr.syncrst --- BEGIN
				rdAAXI_rdata_oprt <= (others => '0');
				rdAAXI_rlast_oprt <= '1';
				rdAReady <= false;
				rdAA <= (others => '0');

				i := 0;
				j := 0;
				-- IP impl.rdAGearEgr.syncrst --- END
				-- IP impl.rdAGearEgr.syncrst.cust --- INSERT

				stateRdAGearEgr <= stateRdAGearEgrIdle;

			elsif stateRdAGearEgr=stateRdAGearEgrIdle then
				if reqRdA='1' and not rdAFull then
					stateRdAGearEgr <= stateRdAGearEgrAddr;
				end if;

			elsif stateRdAGearEgr=stateRdAGearEgrAddr then
				if rdAAXI_arvalid='1' then
					rdAA <= rdAAXI_araddr;
					rdAReady <= true;

					stateRdAGearEgr <= stateRdAGearEgrWaitFull;
				end if;

			elsif stateRdAGearEgr=stateRdAGearEgrWaitFull then
				if rdAFull then
					i := 0;
					j := 0;

					rdAAXI_rdata_oprt <= rdABuf(i)(rdAWD-1 downto 0);
					rdAAXI_rlast_oprt <= '0';

					stateRdAGearEgr <= stateRdAGearEgrXfer;
				end if;

			elsif stateRdAGearEgr=stateRdAGearEgrXfer then
				if rdAAXI_rready='1' then
					if j=jmax then
						j := 0;

						if i=NBeatRd-1 then
							rdAReady <= false;

							stateRdAGearEgr <= stateRdAGearEgrIdle;

						else
							i := i + 1;

							rdAAXI_rdata_oprt <= rdABuf(i)(rdAWD*(j+1)-1 downto rdAWD*j);

							stateRdAGearEgr <= stateRdAGearEgrXfer;
						end if;

					else
						j := j + 1;

						rdAAXI_rdata_oprt <= rdABuf(i)(rdAWD*(j+1)-1 downto rdAWD*j);

						if i=NBeatRd-1 and j=jmax then
							rdAAXI_rlast_oprt <= '1';
						end if;

						stateRdAGearEgr <= stateRdAGearEgrXfer;
					end if;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.rdAGearEgr.rising --- END

	------------------------------------------------------------------------
	-- implementation: rdA geared ingress operation (rdAGearIgr)
	------------------------------------------------------------------------

	-- IP impl.rdAGearIgr.wiring --- BEGIN
	reqRdA_sig <= '1' when (stateRdAGearIgr=stateRdAGearIgrAddr or stateRdAGearIgr=stateRdAGearIgrXfer) else '0';

	rdAAXI_arvalid_sig <= '1' when stateRdAGearIgr=stateRdAGearIgrAddr else '0';
	rdAAXI_rready_sig <= '1' when stateRdAGearIgr=stateRdAGearIgrXfer else '0';
	-- IP impl.rdAGearIgr.wiring --- END

	-- IP impl.rdAGearIgr.wiring.cust --- LINE

	-- IP impl.rdAGearIgr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.rdAGearIgr.vars --- BEGIN
		variable i: natural range 0 to NBeatRd-1;
		-- IP impl.rdAGearIgr.vars --- END

	begin
		if resetMemclk='1' then
			stateRdAGearIgr <= stateRdAGearIgrInit;
			rdAAXI_araddr_sig <= (others => '0');
			rdAFull <= false;
			for i in 0 to NBeatRd-1 loop
				rdABuf(i) <= (others => '0');
			end loop;
			-- IP impl.rdAGearIgr.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if not rdAReady and rdAFull then
				rdAFull <= false;
			end if;

			if stateRdAGearIgr=stateRdAGearIgrInit then
				rdAAXI_araddr_sig <= (others => '0');
				rdAFull <= false;
				for i in 0 to NBeatRd-1 loop
					rdABuf(i) <= (others => '0');
				end loop;
				-- IP impl.rdAGearIgr.syncrst.cust --- INSERT

				stateRdAGearIgr <= stateRdAGearIgrIdle;

			elsif stateRdAGearIgr=stateRdAGearIgrIdle then
				if rdAReady and not rdAFull then
					rdAAXI_araddr_sig <= rdAA;

					stateRdAGearIgr <= stateRdAGearIgrAddr;
				end if;

			elsif stateRdAGearIgr=stateRdAGearIgrAddr then
				if rdAAXI_arready_sig='1' then
					i := 0;

					stateRdAGearIgr <= stateRdAGearIgrXfer;
				end if;

			elsif stateRdAGearIgr=stateRdAGearIgrXfer then
				if rdAAXI_rvalid_sig='1' then
					rdABuf(i) <= rdAAXI_rdata_sig;

					if (i=NBeatRd-1 or rdAAXI_rlast_sig='1') then
						rdAFull <= true;

						stateRdAGearIgr <= stateRdAGearIgrIdle;

					else
						i := i + 1;

						stateRdAGearIgr <= stateRdAGearIgrXfer;
					end if;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.rdAGearIgr.rising --- END

	------------------------------------------------------------------------
	-- implementation: rdB geared egress operation (rdBGearEgr)
	------------------------------------------------------------------------

	-- IP impl.rdBGearEgr.wiring --- BEGIN
	ackRdB <= '1' when (stateRdBGearEgr=stateRdBGearEgrAddr or stateRdBGearEgr=stateRdBGearEgrWaitFull or stateRdBGearEgr=stateRdBGearEgrXfer) else '0';

	rdBAXI_arready <= '1' when stateRdBGearEgr=stateRdBGearEgrAddr else '0';
	rdBAXI_rdata <= rdBAXI_rdata_oprt;
	rdBAXI_rlast <= rdBAXI_rlast_oprt;
	rdBAXI_rvalid <= '1' when stateRdBGearEgr=stateRdBGearEgrXfer else '0';
	-- IP impl.rdBGearEgr.wiring --- END

	-- IP impl.rdBGearEgr.wiring.cust --- LINE

	-- IP impl.rdBGearEgr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.rdBGearEgr.vars --- BEGIN
		variable i: natural range 0 to NBeatRd-1;

		constant jmax: natural := wD/rdBWD-1;
		variable j: natural range 0 to jmax;
		-- IP impl.rdBGearEgr.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.rdBGearEgr.asyncrst --- BEGIN
			stateRdBGearEgr <= stateRdBGearEgrInit;
			rdBAXI_rdata_oprt <= (others => '0');
			rdBAXI_rlast_oprt <= '1';
			rdBReady <= false;
			rdBA <= (others => '0');

			i := 0;
			j := 0;
			-- IP impl.rdBGearEgr.asyncrst --- END
			-- IP impl.rdBGearEgr.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if stateRdBGearEgr=stateRdBGearEgrInit then
				-- IP impl.rdBGearEgr.syncrst --- BEGIN
				rdBAXI_rdata_oprt <= (others => '0');
				rdBAXI_rlast_oprt <= '1';
				rdBReady <= false;
				rdBA <= (others => '0');

				i := 0;
				j := 0;
				-- IP impl.rdBGearEgr.syncrst --- END
				-- IP impl.rdBGearEgr.syncrst.cust --- INSERT

				stateRdBGearEgr <= stateRdBGearEgrIdle;

			elsif stateRdBGearEgr=stateRdBGearEgrIdle then
				if reqRdB='1' and not rdBFull then
					stateRdBGearEgr <= stateRdBGearEgrAddr;
				end if;

			elsif stateRdBGearEgr=stateRdBGearEgrAddr then
				if rdBAXI_arvalid='1' then
					rdBA <= rdBAXI_araddr;
					rdBReady <= true;

					stateRdBGearEgr <= stateRdBGearEgrWaitFull;
				end if;

			elsif stateRdBGearEgr=stateRdBGearEgrWaitFull then
				if rdBFull then
					i := 0;
					j := 0;

					rdBAXI_rdata_oprt <= rdBBuf(i)(rdBWD-1 downto 0);
					rdBAXI_rlast_oprt <= '0';

					stateRdBGearEgr <= stateRdBGearEgrXfer;
				end if;

			elsif stateRdBGearEgr=stateRdBGearEgrXfer then
				if rdBAXI_rready='1' then
					if j=jmax then
						j := 0;

						if i=NBeatRd-1 then
							rdBReady <= false;

							stateRdBGearEgr <= stateRdBGearEgrIdle;

						else
							i := i + 1;

							rdBAXI_rdata_oprt <= rdBBuf(i)(rdBWD*(j+1)-1 downto rdBWD*j);

							stateRdBGearEgr <= stateRdBGearEgrXfer;
						end if;

					else
						j := j + 1;

						rdBAXI_rdata_oprt <= rdBBuf(i)(rdBWD*(j+1)-1 downto rdBWD*j);

						if i=NBeatRd-1 and j=jmax then
							rdBAXI_rlast_oprt <= '1';
						end if;

						stateRdBGearEgr <= stateRdBGearEgrXfer;
					end if;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.rdBGearEgr.rising --- END

	------------------------------------------------------------------------
	-- implementation: rdB geared ingress operation (rdBGearIgr)
	------------------------------------------------------------------------

	-- IP impl.rdBGearIgr.wiring --- BEGIN
	reqRdB_sig <= '1' when (stateRdBGearIgr=stateRdBGearIgrAddr or stateRdBGearIgr=stateRdBGearIgrXfer) else '0';

	rdBAXI_arvalid_sig <= '1' when stateRdBGearIgr=stateRdBGearIgrAddr else '0';
	rdBAXI_rready_sig <= '1' when stateRdBGearIgr=stateRdBGearIgrXfer else '0';
	-- IP impl.rdBGearIgr.wiring --- END

	-- IP impl.rdBGearIgr.wiring.cust --- LINE

	-- IP impl.rdBGearIgr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.rdBGearIgr.vars --- BEGIN
		variable i: natural range 0 to NBeatRd-1;
		-- IP impl.rdBGearIgr.vars --- END

	begin
		if resetMemclk='1' then
			stateRdBGearIgr <= stateRdBGearIgrInit;
			rdBAXI_araddr_sig <= (others => '0');
			rdBFull <= false;
			for i in 0 to NBeatRd-1 loop
				rdBBuf(i) <= (others => '0');
			end loop;
			-- IP impl.rdBGearIgr.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if not rdBReady and rdBFull then
				rdBFull <= false;
			end if;

			if stateRdBGearIgr=stateRdBGearIgrInit then
				rdBAXI_araddr_sig <= (others => '0');
				rdBFull <= false;
				for i in 0 to NBeatRd-1 loop
					rdBBuf(i) <= (others => '0');
				end loop;
				-- IP impl.rdBGearIgr.syncrst.cust --- INSERT

				stateRdBGearIgr <= stateRdBGearIgrIdle;

			elsif stateRdBGearIgr=stateRdBGearIgrIdle then
				if rdBReady and not rdBFull then
					rdBAXI_araddr_sig <= rdBA;

					stateRdBGearIgr <= stateRdBGearIgrAddr;
				end if;

			elsif stateRdBGearIgr=stateRdBGearIgrAddr then
				if rdBAXI_arready_sig='1' then
					i := 0;

					stateRdBGearIgr <= stateRdBGearIgrXfer;
				end if;

			elsif stateRdBGearIgr=stateRdBGearIgrXfer then
				if rdBAXI_rvalid_sig='1' then
					rdBBuf(i) <= rdBAXI_rdata_sig;

					if (i=NBeatRd-1 or rdBAXI_rlast_sig='1') then
						rdBFull <= true;

						stateRdBGearIgr <= stateRdBGearIgrIdle;

					else
						i := i + 1;

						stateRdBGearIgr <= stateRdBGearIgrXfer;
					end if;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.rdBGearIgr.rising --- END

	------------------------------------------------------------------------
	-- implementation: read access negotiation (read)
	------------------------------------------------------------------------

	-- IP impl.read.wiring --- BEGIN
	ddrAXI_arid <= "000000";
	ddrAXI_arburst <= "01"; -- INCR burst type
	ddrAXI_arcache <= "0000"; -- device non-bufferable memory type
	ddrAXI_arlen_sig <= std_logic_vector(to_unsigned(NBeatRd - 1, 8));
	ddrAXI_arlen <= ddrAXI_arlen_sig;
	ddrAXI_arlock <= "0"; -- non-exclusive access
	ddrAXI_arprot <= "010"; -- unprivileged, non-secure data access
	ddrAXI_arqos <= "1101"; -- not participating in QoS scheme
	ddrAXI_arregion <= "0000"; -- region feature not used
	ddrAXI_arsize <= "110"; -- 512-bit wide transfers

	ackRd <= '1' when stateRead=stateReadLocked else '0';

	ackRdA_sig <= ackRd when rdmutex=mutexA else '0';
	ackRdB_sig <= ackRd when rdmutex=mutexB else '0';

	rdAAXI_arready_sig <= ddrAXI_arready when rdmutex=mutexA else '0';
	rdAAXI_rdata_sig <= ddrAXI_rdata;
	rdAAXI_rlast_sig <= ddrAXI_rlast when rdid(ixRdidEgr)=mutexA else '1';
	rdAAXI_rresp_sig <= ddrAXI_rresp;
	rdAAXI_rvalid_sig <= ddrAXI_rvalid when rdid(ixRdidEgr)=mutexA else '0';

	rdBAXI_arready_sig <= ddrAXI_arready when rdmutex=mutexB else '0';
	rdBAXI_rdata_sig <= ddrAXI_rdata;
	rdBAXI_rlast_sig <= ddrAXI_rlast when rdid(ixRdidEgr)=mutexB else '1';
	rdBAXI_rresp_sig <= ddrAXI_rresp;
	rdBAXI_rvalid_sig <= ddrAXI_rvalid when rdid(ixRdidEgr)=mutexB else '0';
	-- IP impl.read.wiring --- END

	ddrAXI_araddr <= "0000001" & rdAAXI_araddr_sig & "00000000" when rdmutex=mutexA
				else "0000001" & rdBAXI_araddr_sig & "00000000" when rdmutex=mutexB
				else (others => '0');

	ddrAXI_arvalid <= ddrAXI_arvalid_sig;
	ddrAXI_arvalid_sig <= rdAAXI_arvalid_sig when rdmutex=mutexA
				else rdBAXI_arvalid_sig when rdmutex=mutexB
				else '0';

	ddrAXI_rready <= ddrAXI_rready_sig;
	ddrAXI_rready_sig <= rdAAXI_rready_sig when rdid(ixRdidEgr)=mutexA
				else rdBAXI_rready_sig when rdid(ixRdidEgr)=mutexB
				else '0';

	-- IP impl.read.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.read.vars --- BEGIN
		-- IP impl.read.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.read.asyncrst --- BEGIN
			stateRead <= stateReadInit;
			abRd <= 0;
			rdmutex <= mutexIdle;
			strbRdlock <= '0';
			rdid <= (others => mutexIdle);
			ixRdid <= 0;
			ixRdidEgr <= 0;

			-- IP impl.read.asyncrst --- END
			-- IP impl.read.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if ddrAXI_rready_sig='1' and ddrAXI_rvalid='1' and ddrAXI_rlast='1' then
				rdid(ixRdidEgr) <= mutexIdle;

				if ixRdidEgr=31 then
					ixRdidEgr <= 0;
				else
					ixRdidEgr <= ixRdidEgr + 1;
				end if;
			end if;

			if stateRead=stateReadInit then
				-- IP impl.read.syncrst --- BEGIN
				abRd <= 0;
				rdmutex <= mutexIdle;
				strbRdlock <= '0';
				rdid <= (others => mutexIdle);
				ixRdid <= 0;
				ixRdidEgr <= 0;

				-- IP impl.read.syncrst --- END
				-- IP impl.read.syncrst.cust --- INSERT

				stateRead <= stateReadIdle;

			elsif stateRead=stateReadIdle then
				if (reqRdA_sig='1' and ((abRd=0 and reqRdB_sig='0') or abRd=1) and rdid(ixRdid)=mutexIdle) then
					abRd <= 0;
					rdmutex <= mutexA;

					strbRdlock <= '1';

					rdid(ixRdid) <= mutexA;

					stateRead <= stateReadLocked;

				elsif (reqRdB_sig='1' and ((abRd=1 and reqRdA_sig='0') or abRd=0) and rdid(ixRdid)=mutexIdle) then
					abRd <= 1;
					rdmutex <= mutexB;

					strbRdlock <= '1';

					rdid(ixRdid) <= mutexB;

					stateRead <= stateReadLocked;
				end if;

			elsif stateRead=stateReadLocked then
				strbRdlock <= '0';

				if (ddrAXI_arready='1' and ddrAXI_arvalid_sig='1') then
					rdmutex <= mutexIdle;

					if ixRdid=31 then
						ixRdid <= 0;
					else
						ixRdid <= ixRdid + 1;
					end if;

					stateRead <= stateReadIdle;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.read.rising --- END

	------------------------------------------------------------------------
	-- implementation: accumulate statistics (stats)
	------------------------------------------------------------------------

	-- IP impl.stats.wiring --- BEGIN
	getStatsNRdA <= NRdA;
	getStatsNRdB <= NRdB;
	getStatsNWrA <= NWrA;
	getStatsNWrB <= NWrB;
	-- IP impl.stats.wiring --- END

	-- IP impl.stats.wiring.cust --- LINE

	-- IP impl.stats.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.stats.vars --- BEGIN
		constant imax: natural := 10000; -- 1 s
		variable i: natural range 0 to imax;

		variable NRdA_collect: std_logic_vector(31 downto 0);
		variable NRdB_collect: std_logic_vector(31 downto 0);
		variable NWrA_collect: std_logic_vector(31 downto 0);
		variable NWrB_collect: std_logic_vector(31 downto 0);
		-- IP impl.stats.vars --- END

	begin
		if reset='1' then
			-- IP impl.stats.asyncrst --- BEGIN
			stateStats <= stateStatsCollectA;
			NRdA <= (others => '0');
			NRdB <= (others => '0');
			NWrA <= (others => '0');
			NWrB <= (others => '0');

			i := 0;
			NRdA_collect := (others => '0');
			NRdB_collect := (others => '0');
			NWrA_collect := (others => '0');
			NWrB_collect := (others => '0');
			-- IP impl.stats.asyncrst --- END
			-- IP impl.stats.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if strbRdlock_mclk='1' then
				case rdmutex is
					when mutexA =>
						NRdA_collect := std_logic_vector(unsigned(NRdA_collect) + unsigned(ddrAXI_arlen_sig) + 1);
					when mutexB =>
						NRdB_collect := std_logic_vector(unsigned(NRdB_collect) + unsigned(ddrAXI_arlen_sig) + 1);
					when others =>
				end case;
			end if;

			if strbWrlock_mclk='1' then
				case wrmutex is
					when mutexA =>
						NWrA_collect := std_logic_vector(unsigned(NWrA_collect) + unsigned(ddrAXI_awlen_sig) + 1);
					when mutexB =>
						NWrB_collect := std_logic_vector(unsigned(NWrB_collect) + unsigned(ddrAXI_awlen_sig) + 1);
					when others =>
				end case;
			end if;

			if stateStats=stateStatsCollectA then
				if tkclk='1' then
					if i=imax then
						i := 0;

						NRdA <= NRdA_collect;
						NRdA_collect := (others => '0');

						NRdB <= NRdB_collect;
						NRdB_collect := (others => '0');

						NWrA <= NWrA_collect;
						NWrA_collect := (others => '0');

						NWrB <= NWrB_collect;
						NWrB_collect := (others => '0');
					end if;

					stateStats <= stateStatsCollectB;
				end if;

			elsif stateStats=stateStatsCollectB then
				if tkclk='0' then
					i := i + 1;

					stateStats <= stateStatsCollectA;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.stats.rising --- END

	------------------------------------------------------------------------
	-- implementation: wrA geared egress operation (wrAGearEgr)
	------------------------------------------------------------------------

	-- IP impl.wrAGearEgr.wiring --- BEGIN
	reqWrA_sig <= '1' when stateWrAGearEgr=stateWrAGearEgrXfer else '0';
	-- IP impl.wrAGearEgr.wiring --- END

	-- IP impl.wrAGearEgr.wiring.cust --- LINE

	-- IP impl.wrAGearEgr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.wrAGearEgr.vars --- BEGIN
		variable i: natural range 0 to NBeatWr-1;

		variable awdone: boolean;
		variable wdone: boolean;
		-- IP impl.wrAGearEgr.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.wrAGearEgr.asyncrst --- BEGIN
			stateWrAGearEgr <= stateWrAGearEgrInit;
			wrAAXI_awaddr_sig <= (others => '0');
			wrAAXI_awvalid_sig <= '0';
			wrAAXI_wdata_sig <= (others => '0');
			wrAAXI_wlast_sig <= '1';
			wrAAXI_wvalid_sig <= '0';
			wrADoneA <= false;
			wrADoneB <= false;

			i := 0;
			awdone := false;
			wdone := false;
			-- IP impl.wrAGearEgr.asyncrst --- END
			-- IP impl.wrAGearEgr.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if wrAFillBNotA and not wrAFullA and wrADoneA then
				wrADoneA <= false;
			end if;

			if not wrAFillBNotA and not wrAFullB and wrADoneB then
				wrADoneB <= false;
			end if;

			if stateWrAGearEgr=stateWrAGearEgrInit then
				wrAAXI_awaddr_sig <= (others => '0');
				wrAAXI_awvalid_sig <= '0';
				wrAAXI_wdata_sig <= (others => '0');
				wrAAXI_wlast_sig <= '1';
				wrAAXI_wvalid_sig <= '0';

				i := 0;
				awdone := false;
				wdone := false;
				-- IP impl.wrAGearEgr.syncrst.cust --- INSERT

				stateWrAGearEgr <= stateWrAGearEgrIdle;

			elsif stateWrAGearEgr=stateWrAGearEgrIdle then
				if wrAFillBNotA and wrAFullA and not wrADoneA then
					wrAAXI_awaddr_sig <= wrAAa;
					wrAAXI_awvalid_sig <= '1';

					wrAAXI_wdata_sig <= wrAAbuf(0);
					wrAAXI_wlast_sig <= '0';
					wrAAXI_wvalid_sig <= '1';

					i := 0;

					awdone := false;
					wdone := false;

					stateWrAGearEgr <= stateWrAGearEgrXfer;

				elsif not wrAFillBNotA and wrAFullB and not wrADoneB then
					wrAAXI_awaddr_sig <= wrABa;
					wrAAXI_awvalid_sig <= '1';

					wrAAXI_wdata_sig <= wrABbuf(0);
					wrAAXI_wlast_sig <= '0';
					wrAAXI_wvalid_sig <= '1';

					i := 0;

					awdone := false;
					wdone := false;

					stateWrAGearEgr <= stateWrAGearEgrXfer;
				end if;

			elsif stateWrAGearEgr=stateWrAGearEgrXfer then
				if not awdone and wrAAXI_awready_sig='1' then
					wrAAXI_awvalid_sig <= '0';

					awdone := true;
				end if;

				if not wdone and wrAAXI_wready_sig='1' then
					if wrAAXI_wlast_sig='1' then
						wrAAXI_wvalid_sig <= '0';

						wdone := true;
					else
						i := i + 1;

						if wrAFillBNotA then
							wrAAXI_wdata_sig <= wrAAbuf(i);
						else
							wrAAXI_wdata_sig <= wrABbuf(i);
						end if;

						if i=NBeatWr-1 then
							wrAAXI_wlast_sig <= '1';
						end if;
					end if;
				end if;

				if awdone and wdone then
					if wrAFillBNotA then
						wrADoneA <= true;
					else
						wrADoneB <= true;
					end if;

					stateWrAGearEgr <= stateWrAGearEgrIdle;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.wrAGearEgr.rising --- END

	------------------------------------------------------------------------
	-- implementation: wrA geared ingress operation (wrAGearIgr)
	------------------------------------------------------------------------

	-- IP impl.wrAGearIgr.wiring --- BEGIN
	ackWrA <= '1' when (stateWrAGearIgr=stateWrAGearIgrAddr or stateWrAGearIgr=stateWrAGearIgrXfer) else '0';

	wrAAXI_awready <= '1' when stateWrAGearIgr=stateWrAGearIgrAddr else '0';
	wrAAXI_wready <= '1' when stateWrAGearIgr=stateWrAGearIgrXfer else '0';
	-- IP impl.wrAGearIgr.wiring --- END

	-- IP impl.wrAGearIgr.wiring.cust --- LINE

	-- IP impl.wrAGearIgr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.wrAGearIgr.vars --- BEGIN
		variable i: natural range 0 to NBeatWr-1;

		constant jmax: natural := wD/wrAWD-1;
		variable j: natural range 0 to jmax;
		-- IP impl.wrAGearIgr.vars --- END

	begin
		if resetMemclk='1' then
			stateWrAGearIgr <= stateWrAGearIgrInit;
			wrAFillBNotA <= false;
			wrAFullA <= false;
			wrAFullB <= false;
			wrAAa <= (others => '0');
			for i in 0 to NBeatWr-1 loop
				wrAAbuf(i) <= (others => '0');
			end loop;
			wrABa <= (others => '0');
			for i in 0 to NBeatWr-1 loop
				wrABbuf(i) <= (others => '0');
			end loop;
			-- IP impl.wrAGearIgr.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if not wrAFillBNotA and wrAFullB and wrADoneB then
				wrAFullB <= false;
			end if;

			if wrAFillBNotA and wrAFullA and wrADoneA then
				wrAFullA <= false;
			end if;

			if stateWrAGearIgr=stateWrAGearIgrInit then
				wrAFillBNotA <= false;
				wrAAa <= (others => '0');
				for i in 0 to NBeatWr-1 loop
					wrAAbuf(i) <= (others => '0');
				end loop;
				wrABa <= (others => '0');
				for i in 0 to NBeatWr-1 loop
					wrABbuf(i) <= (others => '0');
				end loop;
				-- IP impl.wrAGearIgr.syncrst.cust --- INSERT

				stateWrAGearIgr <= stateWrAGearIgrIdle;

			elsif stateWrAGearIgr=stateWrAGearIgrIdle then
				if reqWrA='1' and ((not wrAFillBNotA and not wrAFullA) or (wrAFillBNotA and not wrAFullB)) then
					stateWrAGearIgr <= stateWrAGearIgrAddr;
				end if;

			elsif stateWrAGearIgr=stateWrAGearIgrAddr then
				if wrAAXI_awvalid='1' then
					if not wrAFillBNotA then
						wrAAa <= wrAAXI_awaddr;
					else
						wrABa <= wrAAXI_awaddr;
					end if;

					i := 0;
					j := 0;

					stateWrAGearIgr <= stateWrAGearIgrXfer;
				end if;

			elsif stateWrAGearIgr=stateWrAGearIgrXfer then
				if wrAAXI_wvalid='1' then
					if not wrAFillBNotA then
						wrAAbuf(i)(wrAWD*(j+1)-1 downto wrAWD*j) <= wrAAXI_wdata;
					else
						wrABbuf(i)(wrAWD*(j+1)-1 downto wrAWD*j) <= wrAAXI_wdata;
					end if;

					if j=jmax then
						j := 0;

						if i=NBeatWr-1 then
							if not wrAFillBNotA then
								wrAFullA <= true;
							else
								wrAFullB <= true;
							end if;

							wrAFillBNotA <= not wrAFillBNotA;

							stateWrAGearIgr <= stateWrAGearIgrIdle;

						else
							i := i + 1;

							stateWrAGearIgr <= stateWrAGearIgrXfer;
						end if;

					else
						j := j + 1;

						stateWrAGearIgr <= stateWrAGearIgrXfer;
					end if;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.wrAGearIgr.rising --- END

	------------------------------------------------------------------------
	-- implementation: wrB geared egress operation (wrBGearEgr)
	------------------------------------------------------------------------

	-- IP impl.wrBGearEgr.wiring --- BEGIN
	reqWrB_sig <= '1' when stateWrBGearEgr=stateWrBGearEgrXfer else '0';
	-- IP impl.wrBGearEgr.wiring --- END

	-- IP impl.wrBGearEgr.wiring.cust --- LINE

	-- IP impl.wrBGearEgr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.wrBGearEgr.vars --- BEGIN
		variable i: natural range 0 to NBeatWr-1;

		variable awdone: boolean;
		variable wdone: boolean;
		-- IP impl.wrBGearEgr.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.wrBGearEgr.asyncrst --- BEGIN
			stateWrBGearEgr <= stateWrBGearEgrInit;
			wrBAXI_awaddr_sig <= (others => '0');
			wrBAXI_awvalid_sig <= '0';
			wrBAXI_wdata_sig <= (others => '0');
			wrBAXI_wlast_sig <= '1';
			wrBAXI_wvalid_sig <= '0';
			wrBDoneA <= false;
			wrBDoneB <= false;

			i := 0;
			awdone := false;
			wdone := false;
			-- IP impl.wrBGearEgr.asyncrst --- END
			-- IP impl.wrBGearEgr.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if wrBFillBNotA and not wrBFullA and wrBDoneA then
				wrBDoneA <= false;
			end if;

			if not wrBFillBNotA and not wrBFullB and wrBDoneB then
				wrBDoneB <= false;
			end if;

			if stateWrBGearEgr=stateWrBGearEgrInit then
				wrBAXI_awaddr_sig <= (others => '0');
				wrBAXI_awvalid_sig <= '0';
				wrBAXI_wdata_sig <= (others => '0');
				wrBAXI_wlast_sig <= '1';
				wrBAXI_wvalid_sig <= '0';

				i := 0;
				awdone := false;
				wdone := false;
				-- IP impl.wrBGearEgr.syncrst.cust --- INSERT

				stateWrBGearEgr <= stateWrBGearEgrIdle;

			elsif stateWrBGearEgr=stateWrBGearEgrIdle then
				if wrBFillBNotA and wrBFullA and not wrBDoneA then
					wrBAXI_awaddr_sig <= wrBAa;
					wrBAXI_awvalid_sig <= '1';

					wrBAXI_wdata_sig <= wrBAbuf(0);
					wrBAXI_wlast_sig <= '0';
					wrBAXI_wvalid_sig <= '1';

					i := 0;

					awdone := false;
					wdone := false;

					stateWrBGearEgr <= stateWrBGearEgrXfer;

				elsif not wrBFillBNotA and wrBFullB and not wrBDoneB then
					wrBAXI_awaddr_sig <= wrBBa;
					wrBAXI_awvalid_sig <= '1';

					wrBAXI_wdata_sig <= wrBBbuf(0);
					wrBAXI_wlast_sig <= '0';
					wrBAXI_wvalid_sig <= '1';

					i := 0;

					awdone := false;
					wdone := false;

					stateWrBGearEgr <= stateWrBGearEgrXfer;
				end if;

			elsif stateWrBGearEgr=stateWrBGearEgrXfer then
				if not awdone and wrBAXI_awready_sig='1' then
					wrBAXI_awvalid_sig <= '0';

					awdone := true;
				end if;

				if not wdone and wrBAXI_wready_sig='1' then
					if wrBAXI_wlast_sig='1' then
						wrBAXI_wvalid_sig <= '0';

						wdone := true;
					else
						i := i + 1;

						if wrBFillBNotA then
							wrBAXI_wdata_sig <= wrBAbuf(i);
						else
							wrBAXI_wdata_sig <= wrBBbuf(i);
						end if;

						if i=NBeatWr-1 then
							wrBAXI_wlast_sig <= '1';
						end if;
					end if;
				end if;

				if awdone and wdone then
					if wrBFillBNotA then
						wrBDoneA <= true;
					else
						wrBDoneB <= true;
					end if;

					stateWrBGearEgr <= stateWrBGearEgrIdle;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.wrBGearEgr.rising --- END

	------------------------------------------------------------------------
	-- implementation: wrB geared ingress operation (wrBGearIgr)
	------------------------------------------------------------------------

	-- IP impl.wrBGearIgr.wiring --- BEGIN
	ackWrB <= '1' when (stateWrBGearIgr=stateWrBGearIgrAddr or stateWrBGearIgr=stateWrBGearIgrXfer) else '0';

	wrBAXI_awready <= '1' when stateWrBGearIgr=stateWrBGearIgrAddr else '0';
	wrBAXI_wready <= '1' when stateWrBGearIgr=stateWrBGearIgrXfer else '0';
	-- IP impl.wrBGearIgr.wiring --- END

	-- IP impl.wrBGearIgr.wiring.cust --- LINE

	-- IP impl.wrBGearIgr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.wrBGearIgr.vars --- BEGIN
		variable i: natural range 0 to NBeatWr-1;

		constant jmax: natural := wD/wrBWD-1;
		variable j: natural range 0 to jmax;
		-- IP impl.wrBGearIgr.vars --- END

	begin
		if resetMemclk='1' then
			stateWrBGearIgr <= stateWrBGearIgrInit;
			wrBFillBNotA <= false;
			wrBFullA <= false;
			wrBFullB <= false;
			wrBAa <= (others => '0');
			for i in 0 to NBeatWr-1 loop
				wrBAbuf(i) <= (others => '0');
			end loop;
			wrBBa <= (others => '0');
			for i in 0 to NBeatWr-1 loop
				wrBBbuf(i) <= (others => '0');
			end loop;
			-- IP impl.wrBGearIgr.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if not wrBFillBNotA and wrBFullB and wrBDoneB then
				wrBFullB <= false;
			end if;

			if wrBFillBNotA and wrBFullA and wrBDoneA then
				wrBFullA <= false;
			end if;

			if stateWrBGearIgr=stateWrBGearIgrInit then
				wrBFillBNotA <= false;
				wrBAa <= (others => '0');
				for i in 0 to NBeatWr-1 loop
					wrBAbuf(i) <= (others => '0');
				end loop;
				wrBBa <= (others => '0');
				for i in 0 to NBeatWr-1 loop
					wrBBbuf(i) <= (others => '0');
				end loop;
				-- IP impl.wrBGearIgr.syncrst.cust --- INSERT

				stateWrBGearIgr <= stateWrBGearIgrIdle;

			elsif stateWrBGearIgr=stateWrBGearIgrIdle then
				if reqWrB='1' and ((not wrBFillBNotA and not wrBFullA) or (wrBFillBNotA and not wrBFullB)) then
					stateWrBGearIgr <= stateWrBGearIgrAddr;
				end if;

			elsif stateWrBGearIgr=stateWrBGearIgrAddr then
				if wrBAXI_awvalid='1' then
					if not wrBFillBNotA then
						wrBAa <= wrBAXI_awaddr;
					else
						wrBBa <= wrBAXI_awaddr;
					end if;

					i := 0;
					j := 0;

					stateWrBGearIgr <= stateWrBGearIgrXfer;
				end if;

			elsif stateWrBGearIgr=stateWrBGearIgrXfer then
				if wrBAXI_wvalid='1' then
					if not wrBFillBNotA then
						wrBAbuf(i)(wrBWD*(j+1)-1 downto wrBWD*j) <= wrBAXI_wdata;
					else
						wrBBbuf(i)(wrBWD*(j+1)-1 downto wrBWD*j) <= wrBAXI_wdata;
					end if;

					if j=jmax then
						j := 0;

						if i=NBeatWr-1 then
							if not wrBFillBNotA then
								wrBFullA <= true;
							else
								wrBFullB <= true;
							end if;

							wrBFillBNotA <= not wrBFillBNotA;

							stateWrBGearIgr <= stateWrBGearIgrIdle;

						else
							i := i + 1;

							stateWrBGearIgr <= stateWrBGearIgrXfer;
						end if;

					else
						j := j + 1;

						stateWrBGearIgr <= stateWrBGearIgrXfer;
					end if;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.wrBGearIgr.rising --- END

	------------------------------------------------------------------------
	-- implementation: write access negotiation (write)
	------------------------------------------------------------------------

	-- IP impl.write.wiring --- BEGIN
	ddrAXI_awid <= "000000";
	ddrAXI_awburst <= "01"; -- INCR burst type
	ddrAXI_awcache <= "0000"; -- device non-bufferable memory type
	ddrAXI_awlen_sig <= std_logic_vector(to_unsigned(NBeatWr - 1, 8));
	ddrAXI_awlen <= ddrAXI_awlen_sig;
	ddrAXI_awlock <= "0"; -- non-exclusive access
	ddrAXI_awprot <= "010"; -- unprivileged, non-secure data access
	ddrAXI_awqos <= "1101"; -- not participating in QoS scheme
	ddrAXI_awregion <= "0000"; -- region feature not used
	ddrAXI_awsize <= "110"; -- 512-bit wide transfers

	ddrAXI_wstrb <= "1111111111111111111111111111111111111111111111111111111111111111"; -- no sparse tranfsers

	ddrAXI_bready <= ddrAXI_bready_sig;
	ackWr <= '1' when stateWrite=stateWriteLocked else '0';

	ackWrA_sig <= ackWr when wrmutex=mutexA else '0';
	ackWrB_sig <= ackWr when wrmutex=mutexB else '0';

	wrAAXI_awready_sig <= ddrAXI_awready when wrmutex=mutexA else '0';
	wrAAXI_wready_sig <= ddrAXI_wready when wrmutex=mutexA else '0';

	wrBAXI_awready_sig <= ddrAXI_awready when wrmutex=mutexB else '0';
	wrBAXI_wready_sig <= ddrAXI_wready when wrmutex=mutexB else '0';
	-- IP impl.write.wiring --- END

	ddrAXI_awaddr <= "0000001" & wrAAXI_awaddr_sig & "00000000" when wrmutex=mutexA
				else "0000001" & wrBAXI_awaddr_sig & "00000000" when wrmutex=mutexB
				else (others => '0');

	ddrAXI_awvalid <= ddrAXI_awvalid_sig;
	ddrAXI_awvalid_sig <= wrAAXI_awvalid_sig when wrmutex=mutexA
				else wrBAXI_awvalid_sig when wrmutex=mutexB
				else '0';

	ddrAXI_wdata <= wrAAXI_wdata_sig when wrmutex=mutexA
				else wrBAXI_wdata_sig when wrmutex=mutexB
				else (others => '0');

	ddrAXI_wlast <= ddrAXI_wlast_sig;
	ddrAXI_wlast_sig <= wrAAXI_wlast_sig when wrmutex=mutexA
				else wrBAXI_wlast_sig when wrmutex=mutexB
				else '1';

	ddrAXI_wvalid <= ddrAXI_wvalid_sig;
	ddrAXI_wvalid_sig <= wrAAXI_wvalid_sig when wrmutex=mutexA
				else wrBAXI_wvalid_sig when wrmutex=mutexB
				else '0';

	-- IP impl.write.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.write.vars --- BEGIN
		variable inc: boolean;
		variable dec: boolean;

		variable awdone: boolean;
		variable wdone: boolean;
		-- IP impl.write.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.write.asyncrst --- BEGIN
			stateWrite <= stateWriteInit;
			ddrAXI_bready_sig <= '0';
			wtr <= 0;
			abWr <= 0;
			wrmutex <= mutexIdle;
			strbWrlock <= '0';

			inc := false;
			dec := false;
			awdone := false;
			wdone := false;
			-- IP impl.write.asyncrst --- END
			-- IP impl.write.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			inc := false;
			if ddrAXI_bready_sig='1' and ddrAXI_bvalid='1' then
				dec := true;
			else
				dec := false;
			end if;

			if stateWrite=stateWriteInit then
				-- IP impl.write.syncrst --- BEGIN
				ddrAXI_bready_sig <= '0';
				wtr <= 0;
				abWr <= 0;
				wrmutex <= mutexIdle;
				strbWrlock <= '0';

				inc := false;
				dec := false;
				awdone := false;
				wdone := false;
				-- IP impl.write.syncrst --- END
				-- IP impl.write.syncrst.cust --- INSERT

				stateWrite <= stateWriteIdle;

			elsif stateWrite=stateWriteIdle then
				if wtr/=wtrmax then
					if (reqWrA_sig='1' and ((abWr=0 and reqWrB_sig='0') or abWr=1)) then
						abWr <= 0;
						wrmutex <= mutexA;

						strbWrlock <= '1';

						inc := true;

						awdone := false;
						wdone := false;

						stateWrite <= stateWriteLocked;

					elsif (reqWrB_sig='1' and ((abWr=1 and reqWrA_sig='0') or abWr=0)) then
						abWr <= 1;
						wrmutex <= mutexB;

						strbWrlock <= '1';

						inc := true;

						awdone := false;
						wdone := false;

						stateWrite <= stateWriteLocked;
					end if;
				end if;

			elsif stateWrite=stateWriteLocked then
				strbWrlock <= '0';

				if not awdone and ddrAXI_awready='1' and ddrAXI_awvalid_sig='1' then
					awdone := true;
				end if;

				if not wdone and ddrAXI_wready='1' and ddrAXI_wvalid_sig='1' and ddrAXI_wlast_sig='1' then
					wdone := true;
				end if;

				if awdone and wdone then
					wrmutex <= mutexIdle;

					stateWrite <= stateWriteIdle;
				end if;
			end if;

			if inc and not dec and wtr/=wtrmax then
				ddrAXI_bready_sig <= '1';
				wtr <= wtr + 1;

			elsif not inc and dec and wtr/=0 then
				if wtr=1 then
					ddrAXI_bready_sig <= '0';
				end if;

				wtr <= wtr - 1;
			end if;

		end if;
	end process;
	-- IP impl.write.rising --- END

	------------------------------------------------------------------------
	-- implementation: memclk to mclk CDC sampling (memclkToMclkSample)
	------------------------------------------------------------------------

	-- IP impl.memclkToMclkSample.wiring --- BEGIN
	-- IP impl.memclkToMclkSample.wiring --- END

	-- IP impl.memclkToMclkSample.wiring.cust --- LINE

	-- IP impl.memclkToMclkSample.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.memclkToMclkSample.vars --- BEGIN
		variable strbRdlock_wait: boolean;
		variable strbWrlock_wait: boolean;
		-- IP impl.memclkToMclkSample.vars --- END

	begin
		if reset='1' then
			-- IP impl.memclkToMclkSample.asyncrst --- BEGIN
			strbRdlock_mclk <= '0';
			strbRdlock_to_mclkm1 <= '0';
			strbRdlock_to_mclkm2 <= '0';
			strbWrlock_mclk <= '0';
			strbWrlock_to_mclkm1 <= '0';
			strbWrlock_to_mclkm2 <= '0';

			strbRdlock_wait := false;
			strbWrlock_wait := false;
			-- IP impl.memclkToMclkSample.asyncrst --- END
			-- IP impl.memclkToMclkSample.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if strbRdlock_mclk='1' then
				strbRdlock_mclk <= '0';
			elsif strbRdlock_to_mclkm1='1' and strbRdlock_to_mclkm2='1' and not strbRdlock_wait then
				strbRdlock_mclk <= '1';
				strbRdlock_wait := true;
			end if;
			if strbRdlock_to_mclkm1='0' and strbRdlock_to_mclkm2='0' and strbRdlock_wait then
				strbRdlock_wait := false;
			end if;
			strbRdlock_to_mclkm1 <= strbRdlock_to_mclk;
			strbRdlock_to_mclkm2 <= strbRdlock_to_mclkm1;

			if strbWrlock_mclk='1' then
				strbWrlock_mclk <= '0';
			elsif strbWrlock_to_mclkm1='1' and strbWrlock_to_mclkm2='1' and not strbWrlock_wait then
				strbWrlock_mclk <= '1';
				strbWrlock_wait := true;
			end if;
			if strbWrlock_to_mclkm1='0' and strbWrlock_to_mclkm2='0' and strbWrlock_wait then
				strbWrlock_wait := false;
			end if;
			strbWrlock_to_mclkm1 <= strbWrlock_to_mclk;
			strbWrlock_to_mclkm2 <= strbWrlock_to_mclkm1;

		end if;
	end process;
	-- IP impl.memclkToMclkSample.rising --- END

	------------------------------------------------------------------------
	-- implementation: memclk to mclk CDC stretching (memclkToMclkStretch)
	------------------------------------------------------------------------

	-- IP impl.memclkToMclkStretch.wiring --- BEGIN
	-- IP impl.memclkToMclkStretch.wiring --- END

	-- IP impl.memclkToMclkStretch.wiring.cust --- LINE

	-- IP impl.memclkToMclkStretch.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.memclkToMclkStretch.vars --- BEGIN
		constant imax: natural := 10;

		variable strbRdlock_i: natural range 0 to imax;
		variable strbWrlock_i: natural range 0 to imax;
		-- IP impl.memclkToMclkStretch.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.memclkToMclkStretch.asyncrst --- BEGIN
			strbRdlock_to_mclk <= '0';
			strbWrlock_to_mclk <= '0';

			strbRdlock_i := 0;
			strbWrlock_i := 0;
			-- IP impl.memclkToMclkStretch.asyncrst --- END
			-- IP impl.memclkToMclkStretch.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if strbRdlock='1' then
				strbRdlock_to_mclk <= '1';
				strbRdlock_i := 0;
			elsif strbRdlock_i=imax then
				strbRdlock_to_mclk <= '0';
			else
				strbRdlock_i := strbRdlock_i + 1;
			end if;

			if strbWrlock='1' then
				strbWrlock_to_mclk <= '1';
				strbWrlock_i := 0;
			elsif strbWrlock_i=imax then
				strbWrlock_to_mclk <= '0';
			else
				strbWrlock_i := strbWrlock_i + 1;
			end if;

		end if;
	end process;
	-- IP impl.memclkToMclkStretch.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	

end Rtl;


-- file Decim_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Decim_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Decim_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		vsync: in std_logic;
		ixTExp: in std_logic_vector(3 downto 0);

		NRow: in std_logic_vector(10 downto 0);
		NCol: in std_logic_vector(10 downto 0);

		grayFromVideoinAXIS_tready: out std_logic;
		grayFromVideoinAXIS_tvalid: in std_logic;
		grayFromVideoinAXIS_tdata: in std_logic_vector(71 downto 0);
		grayFromVideoinAXIS_tlast: in std_logic;

		rgbFromVideoinAXIS_tready: out std_logic;
		rgbFromVideoinAXIS_tvalid: in std_logic;
		rgbFromVideoinAXIS_tdata: in std_logic_vector(35 downto 0);
		rgbFromVideoinAXIS_tlast: in std_logic;

		reqInvAcquire: in std_logic;
		ackInvAcquire: out std_logic;

		acquireIxTExp: in std_logic_vector(7 downto 0);

		reqInvConfig: in std_logic;
		ackInvConfig: out std_logic;

		configRgbNotGray: in std_logic_vector(7 downto 0);
		configEdge: in std_logic_vector(7 downto 0);
		configEdge2: in std_logic_vector(15 downto 0);
		configNDecim: in std_logic_vector(15 downto 0);

		getInfoTixVState: out std_logic_vector(7 downto 0);
		getInfoTkst: out std_logic_vector(31 downto 0);

		reqInvSet: in std_logic;
		ackInvSet: out std_logic;

		setRng: in std_logic_vector(7 downto 0);

		reqInvUnlock: in std_logic;
		ackInvUnlock: out std_logic;

		tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0);

		reqPvwbufToHostif: in std_logic;
		ackPvwbufToHostif: out std_logic;
		dnePvwbufToHostif: in std_logic;
		avllenPvwbufToHostif: out std_logic_vector(31 downto 0);

		pvwbufToHostifAXIS_tready: in std_logic;
		pvwbufToHostifAXIS_tvalid: out std_logic;
		pvwbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
		pvwbufToHostifAXIS_tlast: out std_logic;

		stateStore_dbg: out std_logic_vector(7 downto 0);
		stateStream_dbg: out std_logic_vector(7 downto 0)
	);
end Decim_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Decim_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_size2kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(7 downto 0);
			drdA: out std_logic_vector(63 downto 0);
			dwrA: in std_logic_vector(63 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(7 downto 0);
			drdB: out std_logic_vector(63 downto 0);
			dwrB: in std_logic_vector(63 downto 0)
		);
	end component;

	component Dpbram_size32kB_a32b8_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(12 downto 0);
			drdA: out std_logic_vector(31 downto 0);
			dwrA: in std_logic_vector(31 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(14 downto 0);
			drdB: out std_logic_vector(7 downto 0);
			dwrB: in std_logic_vector(7 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant tixVStateIdle: std_logic_vector(7 downto 0) := x"00";
	constant tixVStateAcq: std_logic_vector(7 downto 0) := x"01";
	constant tixVStateLock: std_logic_vector(7 downto 0) := x"02";

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv,
		stateOpRun
	);
	signal stateOp: stateOp_t;

	signal ackInvAcquire_sig: std_logic;
	signal ackInvConfig_sig: std_logic;
	signal ackInvSet_sig: std_logic;
	signal ackInvUnlock_sig: std_logic;

	signal rng: std_logic;
	signal tixVState: std_logic_vector(7 downto 0);
	signal rgbNotGray: std_logic;

	signal edge: natural range 6 to 16;
	signal edge2: unsigned(10 downto 0); -- max. 1024, decim factor before >> 12 (or /4096)

	signal decimLast: natural range 0 to 32*1024-1; -- e.g. for RGB 11x11 of 1280x960, get 3*(1276*957/11/11)-1 = 30275

	-- IP sigs.op.cust --- INSERT

	---- preview buffer B/hostif-facing operation (pvwbufB)
	type statePvwbufB_t is (
		statePvwbufBInit,
		statePvwbufBIdle,
		statePvwbufBXferA, statePvwbufBXferB,
		statePvwbufBDone
	);
	signal statePvwbufB: statePvwbufB_t;

	signal enPvwbufB: std_logic;
	signal aPvwbufB: natural range 0 to 32*1024/4-1;
	signal aPvwbufB_vec: std_logic_vector(12 downto 0);

	-- IP sigs.pvwbufB.cust --- INSERT

	---- decimated value store operation (store)
	type stateStore_t is (
		stateStoreInit,
		stateStoreIdle,
		stateStoreWrite,
		stateStoreDone
	);
	signal stateStore: stateStore_t;

	signal enPvwbuf: std_logic;
	signal aPvwbuf: natural range 0 to 32*1024-1;
	signal aPvwbuf_vec: std_logic_vector(14 downto 0);
	signal dwrPvwbuf: std_logic_vector(7 downto 0);

	-- IP sigs.store.cust --- INSERT

	---- streaming operation (stream)
	type stateStream_t is (
		stateStreamInit,
		stateStreamRun,
		stateStreamEolA, stateStreamEolB,
		stateStreamEofA
	);
	signal stateStream: stateStream_t;

	signal tkst: std_logic_vector(31 downto 0);

	signal enAccbuf: std_logic;
	signal aAccbuf: natural range 0 to 255;
	signal aAccbuf_vec: std_logic_vector(7 downto 0);
	signal dwrAccbuf: std_logic_vector(63 downto 0);

	signal enAccbufB: std_logic;
	signal aAccbufB: natural range 0 to 255;
	signal aAccbufB_vec: std_logic_vector(7 downto 0);

	signal colacc: natural range 0 to 15;
	signal colaccLast: natural range 5 to 15;

	signal rowacc: natural range 0 to 15;
	signal rowaccLast: natural range 5 to 15;

	signal col: natural range 0 to 2000-1;
	signal row: natural range 0 to 1500-1;

	signal decim0: unsigned(30 downto 0);
	signal decim1: unsigned(30 downto 0);
	signal decim2: unsigned(30 downto 0);

	signal strbStore: std_logic;

	-- IP sigs.stream.cust --- INSERT

	---- myAccbuf
	signal drdAccbufB: std_logic_vector(63 downto 0);

	---- other
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myAccbuf : Dpbram_size2kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enAccbuf,
			weA => '1',

			aA => aAccbuf_vec,
			drdA => open,
			dwrA => dwrAccbuf,

			rstB => reset,
			clkB => mclk,

			enB => enAccbufB,
			weB => '0',

			aB => aAccbufB_vec,
			drdB => drdAccbufB,
			dwrB => (others => '0')
		);

	myPvwbuf : Dpbram_size32kB_a32b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enPvwbufB,
			weA => '0',

			aA => aPvwbufB_vec,
			drdA => pvwbufToHostifAXIS_tdata,
			dwrA => (others => '0'),

			rstB => reset,
			clkB => mclk,

			enB => enPvwbuf,
			weB => '1',

			aB => aPvwbuf_vec,
			drdB => open,
			dwrB => dwrPvwbuf
		);

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	ackInvAcquire <= ackInvAcquire_sig;
	ackInvConfig <= ackInvConfig_sig;
	ackInvSet <= ackInvSet_sig;
	ackInvUnlock <= ackInvUnlock_sig;

	getInfoTixVState <= tixVState;
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- LINE

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- RBEGIN
		variable ixTExp_lcl: std_logic_vector(3 downto 0);
		variable vsync_last: std_logic;
		-- IP impl.op.vars --- REND

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- BEGIN
			stateOp <= stateOpInit;
			ackInvAcquire_sig <= '0';
			ackInvConfig_sig <= '0';
			ackInvSet_sig <= '0';
			ackInvUnlock_sig <= '0';
			rng <= '0';
			tixVState <= (others => '0');
			rgbNotGray <= '0';
			edge <= 6;
			edge2 <= "00000100100";
			decimLast <= 0;

			-- IP impl.op.asyncrst --- END
			-- IP impl.op.asyncrst.cust --- IBEGIN
			ixTExp_lcl := (others => '0');
			vsync_last := '0';
			-- IP impl.op.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			if (stateOp=stateOpInit or (stateOp/=stateOpInv and (reqInvAcquire='1' or reqInvConfig='1' or reqInvSet='1' or reqInvUnlock='1'))) then
				if reqInvAcquire='1' then
					-- IP impl.op.init.invAcquire --- IBEGIN
					if rng='1' then
						tixVState <= tixVStateAcq;
						ixTExp_lcl := acquireIxTExp(3 downto 0);
					end if;

					ackInvAcquire_sig <= '1';
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvUnlock_sig <= '0';
					-- IP impl.op.init.invAcquire --- IEND

					stateOp <= stateOpInv;

				elsif reqInvConfig='1' then
					-- IP impl.op.init.invConfig --- IBEGIN
					if configRgbNotGray=tru8 then
						rgbNotGray <= '1';
					else
						rgbNotGray <= '0';
					end if;
					edge <= to_integer(unsigned(configEdge));
					edge2 <= unsigned(configEdge2(10 downto 0));
					decimLast <= to_integer(unsigned(configNDecim) - 1);

					ackInvAcquire_sig <= '0';
					ackInvConfig_sig <= '1';
					ackInvSet_sig <= '0';
					ackInvUnlock_sig <= '0';
					-- IP impl.op.init.invConfig --- IEND

					stateOp <= stateOpInv;

				elsif reqInvSet='1' then
					-- IP impl.op.init.invSet --- IBEGIN
					if setRng=tru8 then
						rng <= '1';
					else
						rng <= '0';
					end if;
					tixVState <= tixVStateIdle;

					ackInvAcquire_sig <= '0';
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '1';
					ackInvUnlock_sig <= '0';
					-- IP impl.op.init.invSet --- IEND

					stateOp <= stateOpInv;

				elsif reqInvUnlock='1' then
					-- IP impl.op.init.invUnlock --- IBEGIN
					if tixVState=tixVStateLock then
						tixVState <= tixVStateIdle;
					end if;

					ackInvAcquire_sig <= '0';
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvUnlock_sig <= '1';
					-- IP impl.op.init.invUnlock --- IEND

					stateOp <= stateOpInv;

				else
					-- IP impl.op.syncrst --- RBEGIN
					ackInvAcquire_sig <= '0';
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvUnlock_sig <= '0';

					-- IP impl.op.syncrst --- REND
					-- IP impl.op.syncrst.cust --- IBEGIN
					vsync_last := vsync;
					-- IP impl.op.syncrst.cust --- IEND

					if rng='1' then
						stateOp <= stateOpRun;

					else
						stateOp <= stateOpInit;
					end if;
				end if;

			elsif stateOp=stateOpInv then
				if ((reqInvAcquire='0' and ackInvAcquire_sig='1') or (reqInvConfig='0' and ackInvConfig_sig='1') or (reqInvSet='0' and ackInvSet_sig='1') or (reqInvUnlock='0' and ackInvUnlock_sig='1')) then
					-- IP impl.op.inv.reset --- IBEGIN
					ackInvAcquire_sig <= '0';
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvUnlock_sig <= '0';
					-- IP impl.op.inv.reset --- IEND

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpRun then
				-- IP impl.op.run --- IBEGIN
				if tixVState=tixVStateAcq and vsync_last='0' and vsync='1' and ixTExp=ixTExp_lcl then
					tixVState <= tixVStateLock;
				end if;

				vsync_last := vsync;
				-- IP impl.op.run --- IEND
			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: preview buffer B/hostif-facing operation (pvwbufB)
	------------------------------------------------------------------------

	-- IP impl.pvwbufB.wiring --- BEGIN
	ackPvwbufToHostif <= '1' when (statePvwbufB=statePvwbufBXferA or statePvwbufB=statePvwbufBXferB or statePvwbufB=statePvwbufBDone) else '0';

	pvwbufToHostifAXIS_tvalid <= '1' when statePvwbufB=statePvwbufBXferB else '0';
	pvwbufToHostifAXIS_tlast <= '0' when (statePvwbufB=statePvwbufBXferB and aPvwbufB/=32*1024/4-1) else '1';

	enPvwbufB <= '1' when statePvwbufB=statePvwbufBXferA else '0';
	aPvwbufB_vec <= std_logic_vector(to_unsigned(aPvwbufB, 13));
	-- IP impl.pvwbufB.wiring --- END

	-- IP impl.pvwbufB.wiring.cust --- RBEGIN
	avllenPvwbufToHostif <= std_logic_vector(to_unsigned(32*1024, 32)) when statePvwbufB=statePvwbufBIdle else (others => '0');
	-- IP impl.pvwbufB.wiring.cust --- REND

	-- IP impl.pvwbufB.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.pvwbufB.vars --- BEGIN
		-- IP impl.pvwbufB.vars --- END

	begin
		if reset='1' then
			-- IP impl.pvwbufB.asyncrst --- BEGIN
			statePvwbufB <= statePvwbufBInit;
			aPvwbufB <= 0;

			-- IP impl.pvwbufB.asyncrst --- END
			-- IP impl.pvwbufB.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if statePvwbufB=statePvwbufBInit then
				-- IP impl.pvwbufB.syncrst --- BEGIN
				aPvwbufB <= 0;

				-- IP impl.pvwbufB.syncrst --- END
				-- IP impl.pvwbufB.syncrst.cust --- INSERT

				if reqPvwbufToHostif='0' then
					statePvwbufB <= statePvwbufBIdle;
				end if;

			elsif statePvwbufB=statePvwbufBIdle then
				if reqPvwbufToHostif='1' then
					statePvwbufB <= statePvwbufBXferA;
				end if;

			elsif statePvwbufB=statePvwbufBXferA then
				statePvwbufB <= statePvwbufBXferB;

			elsif statePvwbufB=statePvwbufBXferB then
				if pvwbufToHostifAXIS_tready='1' then
					if aPvwbufB=32*1024/4-1 then
						statePvwbufB <= statePvwbufBDone;

					else
						aPvwbufB <= aPvwbufB + 1; -- IP impl.pvwbufB.xferB.inc --- ILINE

						statePvwbufB <= statePvwbufBXferA;
					end if;

				elsif reqPvwbufToHostif='0' then
					statePvwbufB <= statePvwbufBInit;
				end if;

			elsif statePvwbufB=statePvwbufBDone then
				if dnePvwbufToHostif='1' then
					statePvwbufB <= statePvwbufBInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.pvwbufB.rising --- END

	------------------------------------------------------------------------
	-- implementation: decimated value store operation (store)
	------------------------------------------------------------------------

	-- IP impl.store.wiring --- BEGIN
	enPvwbuf <= '1' when stateStore=stateStoreWrite else '0';
	aPvwbuf_vec <= std_logic_vector(to_unsigned(aPvwbuf, 15));
	-- IP impl.store.wiring --- END

	-- IP impl.store.wiring.cust --- LINE

	stateStore_dbg <= x"00" when stateStore=stateStoreInit
				else x"10" when stateStore=stateStoreIdle
				else x"20" when stateStore=stateStoreWrite
				else x"30" when stateStore=stateStoreDone
				else (others => '1');

	-- IP impl.store.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.store.vars --- RBEGIN
		constant imax: natural := 2;
		variable i: natural range 0 to imax;
		-- IP impl.store.vars --- REND

	begin
		if reset='1' then
			-- IP impl.store.asyncrst --- BEGIN
			stateStore <= stateStoreInit;
			aPvwbuf <= 0;
			dwrPvwbuf <= (others => '0');

			-- IP impl.store.asyncrst --- END
			-- IP impl.store.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateStore=stateStoreInit or rng='0') then
				-- IP impl.store.syncrst --- BEGIN
				aPvwbuf <= 0;
				dwrPvwbuf <= (others => '0');

				-- IP impl.store.syncrst --- END
				-- IP impl.store.syncrst.cust --- INSERT

				if (rng='1' and vsync='1') then
					stateStore <= stateStoreIdle;

				else
					stateStore <= stateStoreInit;
				end if;

			elsif stateStore=stateStoreIdle then
				if strbStore='1' then
					-- IP impl.store.idle.copy --- IBEGIN
					dwrPvwbuf <= std_logic_vector(decim0(12+11 downto 12+4));
					
					i := 0;
					-- IP impl.store.idle.copy --- IEND

					stateStore <= stateStoreWrite;
				end if;

			elsif stateStore=stateStoreWrite then
				if aPvwbuf=decimLast then
					stateStore <= stateStoreDone;

				else
					aPvwbuf <= aPvwbuf + 1; -- IP impl.store.write.inc --- ILINE

					if (rgbNotGray='1' and i<2) then
						-- IP impl.store.write.nextWord --- IBEGIN
						i := i + 1;

						case i is
							when 1 =>
								dwrPvwbuf <= std_logic_vector(decim1(12+11 downto 12+4));
							when 2 =>
								dwrPvwbuf <= std_logic_vector(decim2(12+11 downto 12+4));
							when others =>
						end case;
						-- IP impl.store.write.nextWord --- IEND

						stateStore <= stateStoreWrite;

					else
						stateStore <= stateStoreIdle;
					end if;
				end if;

			elsif stateStore=stateStoreDone then
				if vsync='1' then
					stateStore <= stateStoreInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.store.rising --- END

	------------------------------------------------------------------------
	-- implementation: streaming operation (stream)
	------------------------------------------------------------------------

	-- IP impl.stream.wiring --- BEGIN
	getInfoTkst <= tkst;

	aAccbuf_vec <= std_logic_vector(to_unsigned(aAccbuf, 8));

	enAccbufB <= '1' when stateStream=stateStreamRun else '0';
	aAccbufB_vec <= std_logic_vector(to_unsigned(aAccbufB, 8));
	-- IP impl.stream.wiring --- END

	-- IP impl.stream.wiring.cust --- LINE

	stateStream_dbg <= x"00" when stateStream=stateStreamInit
				else x"10" when stateStream=stateStreamRun
				else x"20" when stateStream=stateStreamEolA
				else x"21" when stateStream=stateStreamEolB
				else x"30" when stateStream=stateStreamEofA
				else (others => '1');

	-- IP impl.stream.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.stream.vars --- RBEGIN
		variable acc0, acc1, acc2: unsigned(19 downto 0);

		variable row_next: natural range 0 to 1500+16-1;
		variable col_next: natural range 0 to 2000+16-1;
		-- IP impl.stream.vars --- REND

	begin
		if reset='1' then
			-- IP impl.stream.asyncrst --- BEGIN
			stateStream <= stateStreamInit;
			tkst <= (others => '0');
			enAccbuf <= '0';
			aAccbuf <= 0;
			dwrAccbuf <= (others => '0');
			aAccbufB <= 0;
			colacc <= 0;
			colaccLast <= 5;
			rowacc <= 0;
			rowaccLast <= 5;
			col <= 0;
			row <= 0;
			decim0 <= (others => '0');
			decim1 <= (others => '0');
			decim2 <= (others => '0');
			strbStore <= '0';

			-- IP impl.stream.asyncrst --- END
			-- IP impl.stream.asyncrst.cust --- IBEGIN
			acc0 := (others => '0');
			acc1 := (others => '0');
			acc2 := (others => '0');

			row_next := 0;
			col_next := 0;
			-- IP impl.stream.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			if (stateStream=stateStreamInit or rng='0') then
				-- IP impl.stream.syncrst --- RBEGIN
				enAccbuf <= '0';
				aAccbuf <= 0;
				dwrAccbuf <= (others => '0');
				aAccbufB <= 0;
				colacc <= 0;
				rowacc <= 0;
				col <= 0;
				row <= 0;
				decim0 <= (others => '0');
				decim1 <= (others => '0');
				decim2 <= (others => '0');
				strbStore <= '0';

				-- IP impl.stream.syncrst --- REND
				-- IP impl.stream.syncrst.cust --- IBEGIN
				acc0 := (others => '0');
				acc1 := (others => '0');
				acc2 := (others => '0');
	
				row_next := 0;
				col_next := 0;
				-- IP impl.stream.syncrst.cust --- IEND

				if (rng='1' and (vsync='1' and tixVState/=tixVStateLock)) then
					-- IP impl.stream.init.start --- IBEGIN
					tkst <= tkclksrcGetTkstTkst;

					colaccLast <= edge-1;
					rowaccLast <= edge-1;
					-- IP impl.stream.init.start --- IEND

					stateStream <= stateStreamRun;

				else
					stateStream <= stateStreamInit;
				end if;

			elsif stateStream=stateStreamRun then
				-- IP impl.stream.run.pre --- IBEGIN
				if enAccbuf='1' then
					aAccbuf <= aAccbuf + 1;
				end if;
				-- IP impl.stream.run.pre --- IEND

				if ((rgbNotGray='0' and grayFromVideoinAXIS_tvalid='1') or (rgbNotGray='1' and rgbFromVideoinAXIS_tvalid='1')) then
					-- IP impl.stream.run.acc --- IBEGIN
					if colacc=0 then
						aAccbufB <= aAccbufB + 1;

						if rowacc=0 then
							acc0 := (others => '0');
							acc1 := (others => '0');
							acc2 := (others => '0');
						else
							acc0 := unsigned(drdAccbufB(19 downto 0));
							acc1 := unsigned(drdAccbufB(39 downto 20));
							acc2 := unsigned(drdAccbufB(59 downto 40));
						end if;
					end if;

					if rgbNotGray='0' then
						acc0 := acc0 + resize(unsigned(grayFromVideoinAXIS_tdata(11 downto 0)), 20);
					else
						acc2 := acc2 + resize(unsigned(rgbFromVideoinAXIS_tdata(35 downto 24)), 20);
						acc1 := acc1 + resize(unsigned(rgbFromVideoinAXIS_tdata(23 downto 12)), 20);
						acc0 := acc0 + resize(unsigned(rgbFromVideoinAXIS_tdata(11 downto 0)), 20);
					end if;
					-- IP impl.stream.run.acc --- IEND

					if colacc=colaccLast then
						-- IP impl.stream.run.colaccDone --- IBEGIN
						colacc <= 0;

						if rowacc=rowaccLast then
							decim2 <= edge2 * acc2;
							decim1 <= edge2 * acc1;
							decim0 <= edge2 * acc0;

							strbStore <= '1'; -- separate store FSM, aPvwbuf auto-increment

						else
							enAccbuf <= '1';

							dwrAccbuf(59 downto 40) <= std_logic_vector(acc2);
							dwrAccbuf(39 downto 20) <= std_logic_vector(acc1);
							dwrAccbuf(19 downto 0) <= std_logic_vector(acc0);

							strbStore <= '0';
						end if;

						col_next := col + edge;
						-- IP impl.stream.run.colaccDone --- IEND

						if col_next>=unsigned(NCol) then
							col <= 0; -- IP impl.stream.run.rowDone --- ILINE

							stateStream <= stateStreamEolA;

						else
							col <= col + 1; -- IP impl.stream.run.nextCol --- ILINE

							stateStream <= stateStreamRun;
						end if;

					else
						-- IP impl.stream.run.nextColacc --- IBEGIN
						colacc <= colacc + 1;
						col <= col + 1;

						strbStore <= '0';
						-- IP impl.stream.run.nextColacc --- IEND

						stateStream <= stateStreamRun;
					end if;

				else
					-- IP impl.stream.run.reset --- IBEGIN
					enAccbuf <= '0';

					strbStore <= '0';
					-- IP impl.stream.run.reset --- IEND

					stateStream <= stateStreamRun;
				end if;

			elsif stateStream=stateStreamEolA then
				-- IP impl.stream.eolA.pre --- IBEGIN
				enAccbuf <= '0';

				aAccbuf <= 0;
				aAccbufB <= 0;

				strbStore <= '0';
				-- IP impl.stream.eolA.pre --- IEND

				if rowacc=rowaccLast then
					-- IP impl.stream.eolA.rowaccDone --- IBEGIN
					rowacc <= 0;

					row_next := row + edge;
					-- IP impl.stream.eolA.rowaccDone --- IEND

					if row_next>=unsigned(NRow) then
						row <= 0; -- IP impl.stream.eolA.frameDone --- ILINE

						stateStream <= stateStreamEofA;

					else
						row <= row + 1; -- IP impl.stream.eolA.nextRow --- ILINE

						stateStream <= stateStreamEolB;
					end if;

				else
					-- IP impl.stream.eolA.nextRowacc --- IBEGIN
					rowacc <= rowacc + 1;
					row <= row + 1;
					-- IP impl.stream.eolA.nextRowacc --- IEND

					stateStream <= stateStreamEolB;
				end if;

			elsif stateStream=stateStreamEolB then
				if ((rgbNotGray='0' and grayFromVideoinAXIS_tlast='1') or (rgbNotGray='1' and rgbFromVideoinAXIS_tlast='1')) then
					stateStream <= stateStreamRun;
				end if;

			elsif stateStream=stateStreamEofA then
				if vsync='1' then
					stateStream <= stateStreamInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.stream.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;


-- file Director_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Director_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Director_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		NRowRaw: out std_logic_vector(11 downto 0);
		NColRaw: out std_logic_vector(11 downto 0);

		rng: out std_logic;

		reqInvConfig: in std_logic;
		ackInvConfig: out std_logic;

		configNRowRaw: in std_logic_vector(15 downto 0);
		configNColRaw: in std_logic_vector(15 downto 0);

		reqInvSet: in std_logic;
		ackInvSet: out std_logic;

		setRng: in std_logic_vector(7 downto 0)
	);
end Director_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Director_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv
	);
	signal stateOp: stateOp_t;

	signal ackInvConfig_sig: std_logic;
	signal ackInvSet_sig: std_logic;

	signal NRowRaw_sig: natural range 0 to 3000;
	signal NColRaw_sig: natural range 0 to 4000;
	signal rng_sig: std_logic;

	-- IP sigs.op.cust --- INSERT

	---- other
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	ackInvConfig <= ackInvConfig_sig;
	ackInvSet <= ackInvSet_sig;

	rng <= rng_sig;
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- RBEGIN
	NRowRaw <= std_logic_vector(to_unsigned(NRowRaw_sig, 12));
	NColRaw <= std_logic_vector(to_unsigned(NColRaw_sig, 12));
	-- IP impl.op.wiring.cust --- REND

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- BEGIN
		-- IP impl.op.vars --- END

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- BEGIN
			stateOp <= stateOpInit;
			ackInvConfig_sig <= '0';
			ackInvSet_sig <= '0';
			NRowRaw_sig <= 1944;
			NColRaw_sig <= 2592;
			rng_sig <= '0';

			-- IP impl.op.asyncrst --- END
			-- IP impl.op.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateOp=stateOpInit or (stateOp/=stateOpInv and (reqInvConfig='1' or reqInvSet='1'))) then
				if reqInvConfig='1' then
					-- IP impl.op.init.invConfig --- IBEGIN
					NRowRaw_sig <= to_integer(unsigned(configNRowRaw));
					NColRaw_sig <= to_integer(unsigned(configNColRaw));

					ackInvConfig_sig <= '1';
					ackInvSet_sig <= '0';
					-- IP impl.op.init.invConfig --- IEND

					stateOp <= stateOpInv;

				elsif reqInvSet='1' then
					-- IP impl.op.init.invSet --- IBEGIN
					if setRng=tru8 then
						rng_sig <= '1';
					else
						rng_sig <= '0';
					end if;

					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '1';
					-- IP impl.op.init.invSet --- IEND

					stateOp <= stateOpInv;

				else
					-- IP impl.op.syncrst --- RBEGIN
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '0';

					-- IP impl.op.syncrst --- REND
					-- IP impl.op.syncrst.cust --- INSERT

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpInv then
				if ((reqInvConfig='0' and ackInvConfig_sig='1') or (reqInvSet='0' and ackInvSet_sig='1')) then
					-- IP impl.op.inv.reset --- IBEGIN
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '0';
					-- IP impl.op.inv.reset --- IEND

					stateOp <= stateOpInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;


-- file Dpbram_size2kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Dpbram_size2kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06 dpbram_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 4 Nov 2025
-- IP header --- ABOVE

-- module parameters:
-- size (size [kB]): 2
-- wA (A-side width [bit]): 8
-- wB (B-side width [bit]): 8

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Dpbram_size2kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		rstA: in std_logic;
		clkA: in std_logic;

		enA: in std_logic;
		weA: in std_logic;

		aA: in std_logic_vector(10 downto 0);
		drdA: out std_logic_vector(7 downto 0);
		dwrA: in std_logic_vector(7 downto 0);

		rstB: in std_logic;
		clkB: in std_logic;

		enB: in std_logic;
		weB: in std_logic;

		aB: in std_logic_vector(10 downto 0);
		drdB: out std_logic_vector(7 downto 0);
		dwrB: in std_logic_vector(7 downto 0)
	);
end Dpbram_size2kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Dpbram_size2kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_efnx_size2kB_a8b8 is
		port (
			clk_a: in std_logic;

			addren_a: in std_logic;
			we_a: in std_logic_vector(0 downto 0);

			addr_a: in std_logic_vector(10 downto 0);
			rdata_a: out std_logic_vector(7 downto 0);
			wdata_a: in std_logic_vector(7 downto 0);

			clk_b: in std_logic;

			addren_b: in std_logic;
			we_b: in std_logic_vector(0 downto 0);

			addr_b: in std_logic_vector(10 downto 0);
			rdata_b: out std_logic_vector(7 downto 0);
			wdata_b: in std_logic_vector(7 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	signal we_a_sig: std_logic_vector(0 downto 0);
	signal we_b_sig: std_logic_vector(0 downto 0);
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myMnfcore : Dpbram_efnx_size2kB_a8b8
		port map (
			clk_a => clkA,

			addren_a => enA,
			we_a => we_a_sig,

			addr_a => aA,
			rdata_a => drdA,
			wdata_a => dwrA,

			clk_b => clkB,

			addren_b => enB,
			we_b => we_b_sig,

			addr_b => aB,
			rdata_b => drdB,
			wdata_b => dwrB
		);

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	we_a_sig(0) <= weA and enA;
	we_b_sig(0) <= weB and enB;

end Rtl;


-- file Dpbram_size2kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Dpbram_size2kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06 dpbram_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 4 Nov 2025
-- IP header --- ABOVE

-- module parameters:
-- size (size [kB]): 2
-- wA (A-side width [bit]): 32
-- wB (B-side width [bit]): 32

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Dpbram_size2kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		rstA: in std_logic;
		clkA: in std_logic;

		enA: in std_logic;
		weA: in std_logic;

		aA: in std_logic_vector(8 downto 0);
		drdA: out std_logic_vector(31 downto 0);
		dwrA: in std_logic_vector(31 downto 0);

		rstB: in std_logic;
		clkB: in std_logic;

		enB: in std_logic;
		weB: in std_logic;

		aB: in std_logic_vector(8 downto 0);
		drdB: out std_logic_vector(31 downto 0);
		dwrB: in std_logic_vector(31 downto 0)
	);
end Dpbram_size2kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Dpbram_size2kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_efnx_size2kB_a32b32 is
		port (
			clk_a: in std_logic;

			addren_a: in std_logic;
			we_a: in std_logic_vector(0 downto 0);

			addr_a: in std_logic_vector(8 downto 0);
			rdata_a: out std_logic_vector(31 downto 0);
			wdata_a: in std_logic_vector(31 downto 0);

			clk_b: in std_logic;

			addren_b: in std_logic;
			we_b: in std_logic_vector(0 downto 0);

			addr_b: in std_logic_vector(8 downto 0);
			rdata_b: out std_logic_vector(31 downto 0);
			wdata_b: in std_logic_vector(31 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	signal we_a_sig: std_logic_vector(0 downto 0);
	signal we_b_sig: std_logic_vector(0 downto 0);
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myMnfcore : Dpbram_efnx_size2kB_a32b32
		port map (
			clk_a => clkA,

			addren_a => enA,
			we_a => we_a_sig,

			addr_a => aA,
			rdata_a => drdA,
			wdata_a => dwrA,

			clk_b => clkB,

			addren_b => enB,
			we_b => we_b_sig,

			addr_b => aB,
			rdata_b => drdB,
			wdata_b => dwrB
		);

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	we_a_sig(0) <= weA and enA;
	we_b_sig(0) <= weB and enB;

end Rtl;


-- file Dpbram_size2kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Dpbram_size2kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06 dpbram_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 4 Nov 2025
-- IP header --- ABOVE

-- module parameters:
-- size (size [kB]): 2
-- wA (A-side width [bit]): 64
-- wB (B-side width [bit]): 64

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Dpbram_size2kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		rstA: in std_logic;
		clkA: in std_logic;

		enA: in std_logic;
		weA: in std_logic;

		aA: in std_logic_vector(7 downto 0);
		drdA: out std_logic_vector(63 downto 0);
		dwrA: in std_logic_vector(63 downto 0);

		rstB: in std_logic;
		clkB: in std_logic;

		enB: in std_logic;
		weB: in std_logic;

		aB: in std_logic_vector(7 downto 0);
		drdB: out std_logic_vector(63 downto 0);
		dwrB: in std_logic_vector(63 downto 0)
	);
end Dpbram_size2kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Dpbram_size2kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_efnx_size2kB_a64b64 is
		port (
			clk_a: in std_logic;

			addren_a: in std_logic;
			we_a: in std_logic_vector(0 downto 0);

			addr_a: in std_logic_vector(7 downto 0);
			rdata_a: out std_logic_vector(63 downto 0);
			wdata_a: in std_logic_vector(63 downto 0);

			clk_b: in std_logic;

			addren_b: in std_logic;
			we_b: in std_logic_vector(0 downto 0);

			addr_b: in std_logic_vector(7 downto 0);
			rdata_b: out std_logic_vector(63 downto 0);
			wdata_b: in std_logic_vector(63 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	signal we_a_sig: std_logic_vector(0 downto 0);
	signal we_b_sig: std_logic_vector(0 downto 0);
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myMnfcore : Dpbram_efnx_size2kB_a64b64
		port map (
			clk_a => clkA,

			addren_a => enA,
			we_a => we_a_sig,

			addr_a => aA,
			rdata_a => drdA,
			wdata_a => dwrA,

			clk_b => clkB,

			addren_b => enB,
			we_b => we_b_sig,

			addr_b => aB,
			rdata_b => drdB,
			wdata_b => dwrB
		);

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	we_a_sig(0) <= weA and enA;
	we_b_sig(0) <= weB and enB;

end Rtl;


-- file Dpbram_size4kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Dpbram_size4kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06 dpbram_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 4 Nov 2025
-- IP header --- ABOVE

-- module parameters:
-- size (size [kB]): 4
-- wA (A-side width [bit]): 32
-- wB (B-side width [bit]): 32

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Dpbram_size4kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		rstA: in std_logic;
		clkA: in std_logic;

		enA: in std_logic;
		weA: in std_logic;

		aA: in std_logic_vector(9 downto 0);
		drdA: out std_logic_vector(31 downto 0);
		dwrA: in std_logic_vector(31 downto 0);

		rstB: in std_logic;
		clkB: in std_logic;

		enB: in std_logic;
		weB: in std_logic;

		aB: in std_logic_vector(9 downto 0);
		drdB: out std_logic_vector(31 downto 0);
		dwrB: in std_logic_vector(31 downto 0)
	);
end Dpbram_size4kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Dpbram_size4kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_efnx_size4kB_a32b32 is
		port (
			clk_a: in std_logic;

			addren_a: in std_logic;
			we_a: in std_logic_vector(0 downto 0);

			addr_a: in std_logic_vector(9 downto 0);
			rdata_a: out std_logic_vector(31 downto 0);
			wdata_a: in std_logic_vector(31 downto 0);

			clk_b: in std_logic;

			addren_b: in std_logic;
			we_b: in std_logic_vector(0 downto 0);

			addr_b: in std_logic_vector(9 downto 0);
			rdata_b: out std_logic_vector(31 downto 0);
			wdata_b: in std_logic_vector(31 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	signal we_a_sig: std_logic_vector(0 downto 0);
	signal we_b_sig: std_logic_vector(0 downto 0);
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myMnfcore : Dpbram_efnx_size4kB_a32b32
		port map (
			clk_a => clkA,

			addren_a => enA,
			we_a => we_a_sig,

			addr_a => aA,
			rdata_a => drdA,
			wdata_a => dwrA,

			clk_b => clkB,

			addren_b => enB,
			we_b => we_b_sig,

			addr_b => aB,
			rdata_b => drdB,
			wdata_b => dwrB
		);

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	we_a_sig(0) <= weA and enA;
	we_b_sig(0) <= weB and enB;

end Rtl;


-- file Dpbram_size4kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Dpbram_size4kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06 dpbram_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 4 Nov 2025
-- IP header --- ABOVE

-- module parameters:
-- size (size [kB]): 4
-- wA (A-side width [bit]): 64
-- wB (B-side width [bit]): 64

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Dpbram_size4kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		rstA: in std_logic;
		clkA: in std_logic;

		enA: in std_logic;
		weA: in std_logic;

		aA: in std_logic_vector(8 downto 0);
		drdA: out std_logic_vector(63 downto 0);
		dwrA: in std_logic_vector(63 downto 0);

		rstB: in std_logic;
		clkB: in std_logic;

		enB: in std_logic;
		weB: in std_logic;

		aB: in std_logic_vector(8 downto 0);
		drdB: out std_logic_vector(63 downto 0);
		dwrB: in std_logic_vector(63 downto 0)
	);
end Dpbram_size4kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Dpbram_size4kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_efnx_size4kB_a64b64 is
		port (
			clk_a: in std_logic;

			addren_a: in std_logic;
			we_a: in std_logic_vector(0 downto 0);

			addr_a: in std_logic_vector(8 downto 0);
			rdata_a: out std_logic_vector(63 downto 0);
			wdata_a: in std_logic_vector(63 downto 0);

			clk_b: in std_logic;

			addren_b: in std_logic;
			we_b: in std_logic_vector(0 downto 0);

			addr_b: in std_logic_vector(8 downto 0);
			rdata_b: out std_logic_vector(63 downto 0);
			wdata_b: in std_logic_vector(63 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	signal we_a_sig: std_logic_vector(0 downto 0);
	signal we_b_sig: std_logic_vector(0 downto 0);
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myMnfcore : Dpbram_efnx_size4kB_a64b64
		port map (
			clk_a => clkA,

			addren_a => enA,
			we_a => we_a_sig,

			addr_a => aA,
			rdata_a => drdA,
			wdata_a => dwrA,

			clk_b => clkB,

			addren_b => enB,
			we_b => we_b_sig,

			addr_b => aB,
			rdata_b => drdB,
			wdata_b => dwrB
		);

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	we_a_sig(0) <= weA and enA;
	we_b_sig(0) <= weB and enB;

end Rtl;


-- file Dpbram_size8kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Dpbram_size8kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06 dpbram_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 4 Nov 2025
-- IP header --- ABOVE

-- module parameters:
-- size (size [kB]): 8
-- wA (A-side width [bit]): 32
-- wB (B-side width [bit]): 128

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Dpbram_size8kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		rstA: in std_logic;
		clkA: in std_logic;

		enA: in std_logic;
		weA: in std_logic;

		aA: in std_logic_vector(10 downto 0);
		drdA: out std_logic_vector(31 downto 0);
		dwrA: in std_logic_vector(31 downto 0);

		rstB: in std_logic;
		clkB: in std_logic;

		enB: in std_logic;
		weB: in std_logic;

		aB: in std_logic_vector(8 downto 0);
		drdB: out std_logic_vector(127 downto 0);
		dwrB: in std_logic_vector(127 downto 0)
	);
end Dpbram_size8kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Dpbram_size8kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_efnx_size8kB_a32b128 is
		port (
			clk_a: in std_logic;

			addren_a: in std_logic;
			we_a: in std_logic_vector(0 downto 0);

			addr_a: in std_logic_vector(10 downto 0);
			rdata_a: out std_logic_vector(31 downto 0);
			wdata_a: in std_logic_vector(31 downto 0);

			clk_b: in std_logic;

			addren_b: in std_logic;
			we_b: in std_logic_vector(0 downto 0);

			addr_b: in std_logic_vector(8 downto 0);
			rdata_b: out std_logic_vector(127 downto 0);
			wdata_b: in std_logic_vector(127 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	signal we_a_sig: std_logic_vector(0 downto 0);
	signal we_b_sig: std_logic_vector(0 downto 0);
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myMnfcore : Dpbram_efnx_size8kB_a32b128
		port map (
			clk_a => clkA,

			addren_a => enA,
			we_a => we_a_sig,

			addr_a => aA,
			rdata_a => drdA,
			wdata_a => dwrA,

			clk_b => clkB,

			addren_b => enB,
			we_b => we_b_sig,

			addr_b => aB,
			rdata_b => drdB,
			wdata_b => dwrB
		);

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	we_a_sig(0) <= weA and enA;
	we_b_sig(0) <= weB and enB;

end Rtl;


-- file Dpbram_size8kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Dpbram_size8kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06 dpbram_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 4 Nov 2025
-- IP header --- ABOVE

-- module parameters:
-- size (size [kB]): 8
-- wA (A-side width [bit]): 64
-- wB (B-side width [bit]): 64

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Dpbram_size8kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		rstA: in std_logic;
		clkA: in std_logic;

		enA: in std_logic;
		weA: in std_logic;

		aA: in std_logic_vector(9 downto 0);
		drdA: out std_logic_vector(63 downto 0);
		dwrA: in std_logic_vector(63 downto 0);

		rstB: in std_logic;
		clkB: in std_logic;

		enB: in std_logic;
		weB: in std_logic;

		aB: in std_logic_vector(9 downto 0);
		drdB: out std_logic_vector(63 downto 0);
		dwrB: in std_logic_vector(63 downto 0)
	);
end Dpbram_size8kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Dpbram_size8kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_efnx_size8kB_a64b64 is
		port (
			clk_a: in std_logic;

			addren_a: in std_logic;
			we_a: in std_logic_vector(0 downto 0);

			addr_a: in std_logic_vector(9 downto 0);
			rdata_a: out std_logic_vector(63 downto 0);
			wdata_a: in std_logic_vector(63 downto 0);

			clk_b: in std_logic;

			addren_b: in std_logic;
			we_b: in std_logic_vector(0 downto 0);

			addr_b: in std_logic_vector(9 downto 0);
			rdata_b: out std_logic_vector(63 downto 0);
			wdata_b: in std_logic_vector(63 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	signal we_a_sig: std_logic_vector(0 downto 0);
	signal we_b_sig: std_logic_vector(0 downto 0);
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myMnfcore : Dpbram_efnx_size8kB_a64b64
		port map (
			clk_a => clkA,

			addren_a => enA,
			we_a => we_a_sig,

			addr_a => aA,
			rdata_a => drdA,
			wdata_a => dwrA,

			clk_b => clkB,

			addren_b => enB,
			we_b => we_b_sig,

			addr_b => aB,
			rdata_b => drdB,
			wdata_b => dwrB
		);

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	we_a_sig(0) <= weA and enA;
	we_b_sig(0) <= weB and enB;

end Rtl;


-- file Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06 dpbram_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 4 Nov 2025
-- IP header --- ABOVE

-- module parameters:
-- size (size [kB]): 16
-- wA (A-side width [bit]): 8
-- wB (B-side width [bit]): 8

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		rstA: in std_logic;
		clkA: in std_logic;

		enA: in std_logic;
		weA: in std_logic;

		aA: in std_logic_vector(13 downto 0);
		drdA: out std_logic_vector(7 downto 0);
		dwrA: in std_logic_vector(7 downto 0);

		rstB: in std_logic;
		clkB: in std_logic;

		enB: in std_logic;
		weB: in std_logic;

		aB: in std_logic_vector(13 downto 0);
		drdB: out std_logic_vector(7 downto 0);
		dwrB: in std_logic_vector(7 downto 0)
	);
end Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_efnx_size16kB_a8b8 is
		port (
			clk_a: in std_logic;

			addren_a: in std_logic;
			we_a: in std_logic_vector(0 downto 0);

			addr_a: in std_logic_vector(13 downto 0);
			rdata_a: out std_logic_vector(7 downto 0);
			wdata_a: in std_logic_vector(7 downto 0);

			clk_b: in std_logic;

			addren_b: in std_logic;
			we_b: in std_logic_vector(0 downto 0);

			addr_b: in std_logic_vector(13 downto 0);
			rdata_b: out std_logic_vector(7 downto 0);
			wdata_b: in std_logic_vector(7 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	signal we_a_sig: std_logic_vector(0 downto 0);
	signal we_b_sig: std_logic_vector(0 downto 0);
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myMnfcore : Dpbram_efnx_size16kB_a8b8
		port map (
			clk_a => clkA,

			addren_a => enA,
			we_a => we_a_sig,

			addr_a => aA,
			rdata_a => drdA,
			wdata_a => dwrA,

			clk_b => clkB,

			addren_b => enB,
			we_b => we_b_sig,

			addr_b => aB,
			rdata_b => drdB,
			wdata_b => dwrB
		);

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	we_a_sig(0) <= weA and enA;
	we_b_sig(0) <= weB and enB;

end Rtl;


-- file Dpbram_size16kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Dpbram_size16kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06 dpbram_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 4 Nov 2025
-- IP header --- ABOVE

-- module parameters:
-- size (size [kB]): 16
-- wA (A-side width [bit]): 32
-- wB (B-side width [bit]): 128

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Dpbram_size16kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		rstA: in std_logic;
		clkA: in std_logic;

		enA: in std_logic;
		weA: in std_logic;

		aA: in std_logic_vector(11 downto 0);
		drdA: out std_logic_vector(31 downto 0);
		dwrA: in std_logic_vector(31 downto 0);

		rstB: in std_logic;
		clkB: in std_logic;

		enB: in std_logic;
		weB: in std_logic;

		aB: in std_logic_vector(9 downto 0);
		drdB: out std_logic_vector(127 downto 0);
		dwrB: in std_logic_vector(127 downto 0)
	);
end Dpbram_size16kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Dpbram_size16kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_efnx_size16kB_a32b128 is
		port (
			clk_a: in std_logic;

			addren_a: in std_logic;
			we_a: in std_logic_vector(0 downto 0);

			addr_a: in std_logic_vector(11 downto 0);
			rdata_a: out std_logic_vector(31 downto 0);
			wdata_a: in std_logic_vector(31 downto 0);

			clk_b: in std_logic;

			addren_b: in std_logic;
			we_b: in std_logic_vector(0 downto 0);

			addr_b: in std_logic_vector(9 downto 0);
			rdata_b: out std_logic_vector(127 downto 0);
			wdata_b: in std_logic_vector(127 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	signal we_a_sig: std_logic_vector(0 downto 0);
	signal we_b_sig: std_logic_vector(0 downto 0);
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myMnfcore : Dpbram_efnx_size16kB_a32b128
		port map (
			clk_a => clkA,

			addren_a => enA,
			we_a => we_a_sig,

			addr_a => aA,
			rdata_a => drdA,
			wdata_a => dwrA,

			clk_b => clkB,

			addren_b => enB,
			we_b => we_b_sig,

			addr_b => aB,
			rdata_b => drdB,
			wdata_b => dwrB
		);

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	we_a_sig(0) <= weA and enA;
	we_b_sig(0) <= weB and enB;

end Rtl;


-- file Dpbram_size32kB_a8b32.vhd
-- Dpbram_size32kB_a8b32 dpbram_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 4 Nov 2025
-- IP header --- ABOVE

-- module parameters:
-- size (size [kB]): 32
-- wA (A-side width [bit]): 32
-- wB (B-side width [bit]): 8

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Dpbram_size32kB_a32b8_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		rstA: in std_logic;
		clkA: in std_logic;

		enA: in std_logic;
		weA: in std_logic;

		aA: in std_logic_vector(12 downto 0);
		drdA: out std_logic_vector(31 downto 0);
		dwrA: in std_logic_vector(31 downto 0);

		rstB: in std_logic;
		clkB: in std_logic;

		enB: in std_logic;
		weB: in std_logic;

		aB: in std_logic_vector(14 downto 0);
		drdB: out std_logic_vector(7 downto 0);
		dwrB: in std_logic_vector(7 downto 0)
	);
end Dpbram_size32kB_a32b8_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Dpbram_size32kB_a32b8_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_efnx_size32kB_a32b8 is
		port (
			clk_a: in std_logic;

			addren_a: in std_logic;
			we_a: in std_logic_vector(0 downto 0);

			addr_a: in std_logic_vector(12 downto 0);
			rdata_a: out std_logic_vector(31 downto 0);
			wdata_a: in std_logic_vector(31 downto 0);

			clk_b: in std_logic;

			addren_b: in std_logic;
			we_b: in std_logic_vector(0 downto 0);

			addr_b: in std_logic_vector(14 downto 0);
			rdata_b: out std_logic_vector(7 downto 0);
			wdata_b: in std_logic_vector(7 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	signal we_a_sig: std_logic_vector(0 downto 0);
	signal we_b_sig: std_logic_vector(0 downto 0);
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myMnfcore : Dpbram_efnx_size32kB_a32b8
		port map (
			clk_a => clkA,

			addren_a => enA,
			we_a => we_a_sig,

			addr_a => aA,
			rdata_a => drdA,
			wdata_a => dwrA,

			clk_b => clkB,

			addren_b => enB,
			we_b => we_b_sig,

			addr_b => aB,
			rdata_b => drdB,
			wdata_b => dwrB
		);

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	we_a_sig(0) <= weA and enA;
	we_b_sig(0) <= weB and enB;

end Rtl;


-- file Hdreng_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Hdreng_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Hdreng_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		resetMemclk: in std_logic;
		memclk: in std_logic;

		hdrmemAXI_awaddr: out std_logic_vector(17 downto 0);
		hdrmemAXI_awready: in std_logic;
		hdrmemAXI_awvalid: out std_logic;
		hdrmemAXI_bready: out std_logic;
		hdrmemAXI_bresp: in std_logic_vector(1 downto 0);
		hdrmemAXI_bvalid: in std_logic;
		hdrmemAXI_wdata: out std_logic_vector(127 downto 0);
		hdrmemAXI_wlast: out std_logic;
		hdrmemAXI_wready: in std_logic;
		hdrmemAXI_wvalid: out std_logic;

		reqToDdrifWr: out std_logic;
		ackToDdrifWr: in std_logic;

		hdrmemAXI_araddr: out std_logic_vector(17 downto 0);
		hdrmemAXI_arready: in std_logic;
		hdrmemAXI_arvalid: out std_logic;
		hdrmemAXI_rdata: in std_logic_vector(127 downto 0);
		hdrmemAXI_rlast: in std_logic;
		hdrmemAXI_rready: out std_logic;
		hdrmemAXI_rresp: in std_logic_vector(1 downto 0);
		hdrmemAXI_rvalid: in std_logic;

		reqToDdrifRd: out std_logic;
		ackToDdrifRd: in std_logic;

		vsync: in std_logic;
		ixTExp: in std_logic_vector(3 downto 0);

		NRow: in std_logic_vector(10 downto 0);
		NCol: in std_logic_vector(10 downto 0);

		rgbFromVideoinAXIS_tready: out std_logic;
		rgbFromVideoinAXIS_tvalid: in std_logic;
		rgbFromVideoinAXIS_tdata: in std_logic_vector(35 downto 0);
		rgbFromVideoinAXIS_tlast: in std_logic;

		reqInvAssign: in std_logic;
		ackInvAssign: out std_logic;

		assignIxMem: in std_logic_vector(7 downto 0);

		getInfoTixVState: out std_logic_vector(7 downto 0);
		getInfoTkst: out std_logic_vector(31 downto 0);
		getInfoIxMem: out std_logic_vector(7 downto 0);
		getInfoIxMemAcq: out std_logic_vector(7 downto 0);

		reqInvSet: in std_logic;
		ackInvSet: out std_logic;

		setRng: in std_logic_vector(7 downto 0);

		tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0)
	);
end Hdreng_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Hdreng_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_size8kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(10 downto 0);
			drdA: out std_logic_vector(31 downto 0);
			dwrA: in std_logic_vector(31 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(8 downto 0);
			drdB: out std_logic_vector(127 downto 0);
			dwrB: in std_logic_vector(127 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant tixVStateIdle: std_logic_vector(7 downto 0) := x"00";

	constant ixMemInvalid: std_logic_vector(7 downto 0) := x"FF";

	constant tixVStateAcq: std_logic_vector(7 downto 0) := x"01";
	constant tixVStateStall: std_logic_vector(7 downto 0) := x"02";

	---- continuous streaming from buffers to DDR memory (egrstr)
	type stateEgrstr_t is (
		stateEgrstrInit,
		stateEgrstrIdle,
		stateEgrstrLoad,
		stateEgrstrRun,
		stateEgrstrDone
	);
	signal stateEgrstr: stateEgrstr_t;

	signal enRowbufBEgrstr: std_logic;
	signal enRowbufBEgrstrm1: std_logic;

	signal aRowbufBEgrstr: natural range 0 to 8*1024/16-1;
	signal drdRowbufB: std_logic_vector(127 downto 0);
	type egrfifo_t is array (0 to 2) of std_logic_vector(127 downto 0);
	signal egrfifo: egrfifo_t;

	signal ixRdEgrfifo: natural range 0 to 2;
	signal ixWrEgrfifo: natural range 0 to 2;

	signal egrAXIS_tdata: std_logic_vector(127 downto 0);
	signal egrAXIS_tlast: std_logic;

	-- IP sigs.egrstr.cust --- INSERT

	---- continuous streaming from DDR memory (igrstr)
	type stateIgrstr_t is (
		stateIgrstrInit,
		stateIgrstrIdle,
		stateIgrstrRun,
		stateIgrstrDone
	);
	signal stateIgrstr: stateIgrstr_t;

	signal aRowbufBIgrstr: natural;
	signal burstIgrstr: natural range 0 to 31;

	-- IP sigs.igrstr.cust --- INSERT

	---- live stream forwarding (livefwd)

	signal rgbFromVideoinAXIS_tvalidm1: std_logic;
	signal rgbFromVideoinAXIS_tvalidm2: std_logic;

	signal rgbFromVideoinAXIS_tdatam1: std_logic_vector(35 downto 0);
	signal rgbFromVideoinAXIS_tdatam2: std_logic_vector(35 downto 0);

	signal rgbFromVideoinAXIS_tlastm1: std_logic;
	signal rgbFromVideoinAXIS_tlastm2: std_logic;

	-- IP sigs.livefwd.cust --- INSERT

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv
	);
	signal stateOp: stateOp_t;

	signal ackInvAssign_sig: std_logic;
	signal ackInvSet_sig: std_logic;

	signal rng: std_logic;
	signal ixMemNext: std_logic_vector(7 downto 0);
	signal rowLast: natural range 0 to 1500-1;

	-- IP sigs.op.cust --- INSERT

	---- stock release from buffer operation (stockrls)
	type stateStockrls_t is (
		stateStockrlsInit,
		stateStockrlsRun,
		stateStockrlsEol
	);
	signal stateStockrls: stateStockrls_t;

	signal enRowbufStockrls: std_logic;
	signal aRowbufStockrls: natural range 0 to 8*1024/4-1;
	signal stock: std_logic_vector(31 downto 0);

	-- IP sigs.stockrls.cust --- INSERT

	---- streaming operation (stream)
	type stateStream_t is (
		stateStreamInit,
		stateStreamIdle,
		stateStreamRun,
		stateStreamEol
	);
	signal stateStream: stateStream_t;

	signal tixVState: std_logic_vector(7 downto 0);

	signal tkst: std_logic_vector(31 downto 0);
	signal ixMem: std_logic_vector(7 downto 0);

	signal tkstAcq: std_logic_vector(31 downto 0);
	signal ixMemAcq: std_logic_vector(7 downto 0);

	signal a0: std_logic_vector(4 downto 0); -- 12 slots with (8+4) MB spacing
	signal liveBNotA: std_logic;

	signal enRowAbuf: std_logic;
	signal enRowBbuf: std_logic;

	signal enRowbufStream: std_logic;

	signal weRowAbuf: std_logic;
	signal weRowBbuf: std_logic;

	signal aRowAbuf: std_logic_vector(10 downto 0);
	signal aRowBbuf: std_logic_vector(10 downto 0);

	signal aRowbufStream: natural range 0 to 8*1024/4-1;
	signal dwrRowbuf: std_logic_vector(31 downto 0);

	-- IP sigs.stream.cust --- INSERT

	---- stock buffer swap to-then-from DDR memory (swap)
	type stateSwap_t is (
		stateSwapInit,
		stateSwapStart,
		stateSwapIdle,
		stateSwapEgrA, stateSwapEgrB, stateSwapEgrC,
		stateSwapIgrA, stateSwapIgrB, stateSwapIgrC,
		stateSwapWaitA, stateSwapWaitB
	);
	signal stateSwap: stateSwap_t;

	signal addrEgr: std_logic_vector(12 downto 0);
	signal addrIgr: std_logic_vector(12 downto 0);

	signal a0Egrstr: natural range 0 to 511;
	signal lenEgrstr: natural range 0 to 16;

	signal burstSwap: natural range 0 to 31;
	signal burstSwapLast: natural range 0 to 31; -- for IMX335

	signal enRowbufB: std_logic;
	signal enRowAbufB: std_logic;
	signal enRowBbufB: std_logic;

	signal weRowbufB: std_logic;
	signal aRowbufB: std_logic_vector(8 downto 0);

	signal hdrmemAXI_awaddr_sig: std_logic_vector(17 downto 0);

	signal hdrmemAXI_araddr_sig: std_logic_vector(17 downto 0);

	-- IP sigs.swap.cust --- INSERT

	---- mclk to memclk CDC sampling (mclkToMemclkSample)

	signal rng_memclk: std_logic;
	signal rng_to_memclkm1: std_logic;
	signal rng_to_memclkm2: std_logic;
	signal a0_memclk: std_logic_vector(4 downto 0);
	signal a0_to_memclkm1: std_logic_vector(4 downto 0);
	signal a0_to_memclkm2: std_logic_vector(4 downto 0);
	signal liveBNotA_memclk: std_logic;
	signal liveBNotA_to_memclkm1: std_logic;
	signal liveBNotA_to_memclkm2: std_logic;
	signal rgbFromVideoinAXIS_tlast_sig_memclk: std_logic;
	signal rgbFromVideoinAXIS_tlast_sig_to_memclkm1: std_logic;
	signal rgbFromVideoinAXIS_tlast_sig_to_memclkm2: std_logic;
	signal vsync_sig_memclk: std_logic;
	signal vsync_sig_to_memclkm1: std_logic;
	signal vsync_sig_to_memclkm2: std_logic;

	-- IP sigs.mclkToMemclkSample.cust --- INSERT

	---- mclk to memclk CDC stretching (mclkToMemclkStretch)

	signal rng_to_memclk: std_logic;
	signal a0_to_memclk: std_logic_vector(4 downto 0);
	signal liveBNotA_to_memclk: std_logic;
	signal rgbFromVideoinAXIS_tlast_sig_to_memclk: std_logic;
	signal vsync_sig_to_memclk: std_logic;

	-- IP sigs.mclkToMemclkStretch.cust --- INSERT

	---- myRowAbuf
	signal drdRowAbuf: std_logic_vector(31 downto 0);
	signal drdRowAbufB: std_logic_vector(127 downto 0);

	---- myRowBbuf
	signal drdRowBbuf: std_logic_vector(31 downto 0);
	signal drdRowBbufB: std_logic_vector(127 downto 0);

	---- handshake
	-- swap to egrstr
	signal reqSwapToEgrstr: std_logic;
	signal ackSwapToEgrstr: std_logic;
	signal dneSwapToEgrstr: std_logic;

	-- swap to igrstr
	signal reqSwapToIgrstr: std_logic;
	signal ackSwapToIgrstr: std_logic;
	signal dneSwapToIgrstr: std_logic;

	-- swap to egrstr
	signal egrAXIS_tready: std_logic;
	signal egrAXIS_tvalid: std_logic;

	---- other
	signal vsync_sig: std_logic;
	signal rgbFromVideoinAXIS_tlast_sig: std_logic;
	-- IP sigs.oth.cust --- IBEGIN

	------------------------------------------------------------------------
	-- functional description
	------------------------------------------------------------------------

	-- each ixTExp increment corresponds to an eight-fold decrease in exposure time
	-- (longest exposure first)

	-- compare incoming live data to stock data

	-- output: 32-bit RGBE format with shared exponent

	function getExp8of12
		parameter (
			lin: unsigned(11 downto 0)
		)
	return natural is

		variable exp8: natural := 0;

	begin
		--if lin(11)='1' then
		--	exp8 := 4;
		--elsif lin(10)='1' then
		--	exp8 := 3;
		--elsif lin(9)='1' then
		--	exp8 := 2;
		--elsif lin(8)='1' then
		--	exp8 := 1;
		--else
		--	exp8 := 0;
		--end if;

		for i in 11 downto 8 loop
			if lin(i)='1' then
				exp8 := i-7;
				exit;
			end if;
		end loop;

		return exp8;
	end function;


	-- IP sigs.oth.cust --- IEND

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myRowAbuf : Dpbram_size8kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enRowAbuf,
			weA => weRowAbuf,

			aA => aRowAbuf,
			drdA => drdRowAbuf,
			dwrA => dwrRowbuf,

			rstB => resetMemclk,
			clkB => memclk,

			enB => enRowAbufB,
			weB => weRowbufB,

			aB => aRowbufB,
			drdB => drdRowAbufB,
			dwrB => hdrmemAXI_rdata
		);

	myRowBbuf : Dpbram_size8kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enRowBbuf,
			weA => weRowBbuf,

			aA => aRowBbuf,
			drdA => drdRowBbuf,
			dwrA => dwrRowbuf,

			rstB => resetMemclk,
			clkB => memclk,

			enB => enRowBbufB,
			weB => weRowbufB,

			aB => aRowbufB,
			drdB => drdRowBbufB,
			dwrB => hdrmemAXI_rdata
		);

	------------------------------------------------------------------------
	-- implementation: continuous streaming from buffers to DDR memory (egrstr)
	------------------------------------------------------------------------

	-- IP impl.egrstr.wiring --- BEGIN
	drdRowbufB <= drdRowAbufB when liveBNotA_memclk='1' else drdRowBbufB;

	ackSwapToEgrstr <= '1' when (stateEgrstr=stateEgrstrRun or stateEgrstr=stateEgrstrDone) else '0';
	dneSwapToEgrstr <= '1' when stateEgrstr=stateEgrstrDone else '0';

	egrAXIS_tvalid <= '1' when stateEgrstr=stateEgrstrRun else '0';
	-- IP impl.egrstr.wiring --- END

	-- IP impl.egrstr.wiring.cust --- LINE

	-- IP impl.egrstr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.egrstr.vars --- RBEGIN
		variable wordEgrLast: natural range 0 to 15;
		variable wordEgrRd: natural range 0 to 15;
		variable wordEgrWr: natural range 0 to 15;

		variable i: natural range 0 to 2; -- correct choice for register-less BlockRAM
		-- IP impl.egrstr.vars --- REND

	begin
		if resetMemclk='1' then
			-- IP impl.egrstr.asyncrst --- BEGIN
			stateEgrstr <= stateEgrstrInit;
			enRowbufBEgrstr <= '0';
			enRowbufBEgrstrm1 <= '0';
			aRowbufBEgrstr <= 0;
			egrfifo <= (others => (others => '0'));
			ixRdEgrfifo <= 0;
			ixWrEgrfifo <= 0;
			egrAXIS_tdata <= (others => '0');
			egrAXIS_tlast <= '1';

			-- IP impl.egrstr.asyncrst --- END
			-- IP impl.egrstr.asyncrst.cust --- IBEGIN
			wordEgrLast := 0;
			wordEgrRd := 0;
			wordEgrWr := 0;

			i := 0;
			-- IP impl.egrstr.asyncrst.cust --- IEND

		elsif rising_edge(memclk) then
			if stateEgrstr=stateEgrstrInit then
				-- IP impl.egrstr.syncrst --- BEGIN
				enRowbufBEgrstr <= '0';
				enRowbufBEgrstrm1 <= '0';
				aRowbufBEgrstr <= 0;
				egrfifo <= (others => (others => '0'));
				ixRdEgrfifo <= 0;
				ixWrEgrfifo <= 0;
				egrAXIS_tdata <= (others => '0');
				egrAXIS_tlast <= '1';

				-- IP impl.egrstr.syncrst --- END
				-- IP impl.egrstr.syncrst.cust --- IBEGIN
				wordEgrLast := 0;
				wordEgrRd := 0;
				wordEgrWr := 0;

				i := 0;
				-- IP impl.egrstr.syncrst.cust --- IEND

				stateEgrstr <= stateEgrstrIdle;

			elsif stateEgrstr=stateEgrstrIdle then
				if reqSwapToEgrstr='1' then
					-- IP impl.egrstr.idle.start --- IBEGIN
					enRowbufBEgrstr <= '1';
					aRowbufBEgrstr <= a0Egrstr;

					wordEgrLast := lenEgrstr - 1;
					wordEgrRd := 0;
					wordEgrWr := 0;

					i := 0;
					-- IP impl.egrstr.idle.start --- IEND

					stateEgrstr <= stateEgrstrLoad;
				end if;

			elsif stateEgrstr=stateEgrstrLoad then
				if i=0 then
					-- IP impl.egrstr.load.one --- IBEGIN
					enRowbufBEgrstr <= '1';
					aRowbufBEgrstr <= aRowbufBEgrstr + 1;

					i := i + 1;
					-- IP impl.egrstr.load.one --- IEND

					stateEgrstr <= stateEgrstrLoad;

				elsif i=1 then
					-- IP impl.egrstr.load.two --- IBEGIN
					enRowbufBEgrstr <= '1';
					aRowbufBEgrstr <= aRowbufBEgrstr + 1;

					egrfifo(ixWrEgrfifo) <= drdRowbufB;
					ixWrEgrfifo <= 1;

					i := i + 1;
					-- IP impl.egrstr.load.two --- IEND

					stateEgrstr <= stateEgrstrLoad;

				else
					-- IP impl.egrstr.load.done --- IBEGIN
					enRowbufBEgrstr <= '1';
					enRowbufBEgrstrm1 <= '1';

					aRowbufBEgrstr <= aRowbufBEgrstr + 1;

					egrfifo(ixWrEgrfifo) <= drdRowbufB;
					ixWrEgrfifo <= 2;

					egrAXIS_tdata <= egrfifo(ixRdEgrfifo);
					ixRdEgrfifo <= 1;

					egrAXIS_tlast <= '0';

					wordEgrRd := 0; -- corresponding to egrAXIS_tdata
					wordEgrWr := 3; -- corresponding to aRowbufBEgrstr
					-- IP impl.egrstr.load.done --- IEND

					stateEgrstr <= stateEgrstrRun;
				end if;

			elsif stateEgrstr=stateEgrstrRun then
				-- IP impl.egrstr.run.pre --- IBEGIN
				-- update post FIFO-to-stream
				if egrAXIS_tready='1' then
					if ixRdEgrfifo=2 then
						ixRdEgrfifo <= 0;
					else
						ixRdEgrfifo <= ixRdEgrfifo + 1;
					end if;
				end if;

				-- update post buf-to-FIFO
				if enRowbufBEgrstrm1='1' then
					egrfifo(ixWrEgrfifo) <= drdRowbufB;

					if ixWrEgrfifo=2 then
						ixWrEgrfifo <= 0;
					else
						ixWrEgrfifo <= ixWrEgrfifo + 1;
					end if;
				end if;
				-- IP impl.egrstr.run.pre --- IEND

				if (egrAXIS_tready='1' and egrAXIS_tlast='1') then
					-- IP impl.egrstr.run.done --- IBEGIN
					-- proceed
					enRowbufBEgrstr <= '0';
					-- IP impl.egrstr.run.done --- IEND

					stateEgrstr <= stateEgrstrDone;

				else
					-- IP impl.egrstr.run.nextWord --- IBEGIN
					if egrAXIS_tready='1' then
						-- initiate FIFO-to-stream
						egrAXIS_tdata <= egrfifo(ixRdEgrfifo);

						wordEgrRd := wordEgrRd + 1;

						if wordEgrRd=wordEgrLast then
							egrAXIS_tlast <= '1';
						end if;
					end if;

					-- initiate buf-to-FIFO
					enRowbufBEgrstrm1 <= enRowbufBEgrstr;

					if egrAXIS_tready='1' and wordEgrWr/=wordEgrLast then
						enRowbufBEgrstr <= '1';
						aRowbufBEgrstr <= aRowbufBEgrstr + 1;

						wordEgrWr := wordEgrWr + 1;

					else
						enRowbufBEgrstr <= '0';
					end if;
					-- IP impl.egrstr.run.nextWord --- IEND

					stateEgrstr <= stateEgrstrRun;
				end if;

			elsif stateEgrstr=stateEgrstrDone then
				if reqSwapToEgrstr='0' then
					stateEgrstr <= stateEgrstrInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.egrstr.rising --- END

	------------------------------------------------------------------------
	-- implementation: continuous streaming from DDR memory (igrstr)
	------------------------------------------------------------------------

	-- IP impl.igrstr.wiring --- BEGIN
	hdrmemAXI_rready <= '1' when stateIgrstr=stateIgrstrRun else '0';

	ackSwapToIgrstr <= '1' when (stateIgrstr=stateIgrstrRun or stateIgrstr=stateIgrstrDone) else '0';
	dneSwapToIgrstr <= '1' when stateIgrstr=stateIgrstrDone else '0';
	-- IP impl.igrstr.wiring --- END

	-- IP impl.igrstr.wiring.cust --- LINE

	-- IP impl.igrstr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.igrstr.vars --- BEGIN
		-- IP impl.igrstr.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.igrstr.asyncrst --- BEGIN
			stateIgrstr <= stateIgrstrInit;
			aRowbufBIgrstr <= 0;
			burstIgrstr <= 0;

			-- IP impl.igrstr.asyncrst --- END
			-- IP impl.igrstr.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if stateIgrstr=stateIgrstrInit then
				-- IP impl.igrstr.syncrst --- BEGIN
				aRowbufBIgrstr <= 0;
				burstIgrstr <= 0;

				-- IP impl.igrstr.syncrst --- END
				-- IP impl.igrstr.syncrst.cust --- INSERT

				stateIgrstr <= stateIgrstrIdle;

			elsif stateIgrstr=stateIgrstrIdle then
				if reqSwapToIgrstr='1' then
					stateIgrstr <= stateIgrstrRun;
				end if;

			elsif stateIgrstr=stateIgrstrRun then
				if hdrmemAXI_rvalid='1' then
					if (aRowbufBIgrstr=8*1024/16-1 or (burstIgrstr=burstSwap and hdrmemAXI_rlast='1')) then
						stateIgrstr <= stateIgrstrDone;

					else
						-- IP impl.igrstr.run.inc --- IBEGIN
						if hdrmemAXI_rlast='1' then
							burstIgrstr <= burstIgrstr + 1;
						end if;

						aRowbufBIgrstr <= aRowbufBIgrstr + 1;
						-- IP impl.igrstr.run.inc --- IEND

						stateIgrstr <= stateIgrstrRun;
					end if;
				end if;

			elsif stateIgrstr=stateIgrstrDone then
				if reqSwapToIgrstr='0' then
					stateIgrstr <= stateIgrstrInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.igrstr.rising --- END

	------------------------------------------------------------------------
	-- implementation: live stream forwarding (livefwd)
	------------------------------------------------------------------------

	-- IP impl.livefwd.wiring --- BEGIN
	-- IP impl.livefwd.wiring --- END

	-- IP impl.livefwd.wiring.cust --- LINE

	-- IP impl.livefwd.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.livefwd.vars --- BEGIN
		-- IP impl.livefwd.vars --- END

	begin
		if reset='1' then
			-- IP impl.livefwd.asyncrst --- BEGIN
			rgbFromVideoinAXIS_tvalidm1 <= '0';
			rgbFromVideoinAXIS_tvalidm2 <= '0';
			rgbFromVideoinAXIS_tdatam1 <= (others => '0');
			rgbFromVideoinAXIS_tdatam2 <= (others => '0');
			rgbFromVideoinAXIS_tlastm1 <= '1';
			rgbFromVideoinAXIS_tlastm2 <= '1';

			-- IP impl.livefwd.asyncrst --- END
			-- IP impl.livefwd.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			-- IP impl.livefwd --- IBEGIN
			rgbFromVideoinAXIS_tvalidm1 <= rgbFromVideoinAXIS_tvalid;
			rgbFromVideoinAXIS_tvalidm2 <= rgbFromVideoinAXIS_tvalidm1;
			rgbFromVideoinAXIS_tdatam1 <= rgbFromVideoinAXIS_tdata;
			rgbFromVideoinAXIS_tdatam2 <= rgbFromVideoinAXIS_tdatam1;
			rgbFromVideoinAXIS_tlastm1 <= rgbFromVideoinAXIS_tlast;
			rgbFromVideoinAXIS_tlastm2 <= rgbFromVideoinAXIS_tlastm1;
			-- IP impl.livefwd --- IEND
		end if;
	end process;
	-- IP impl.livefwd.rising --- END

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	ackInvAssign <= ackInvAssign_sig;
	ackInvSet <= ackInvSet_sig;

	rowLast <= to_integer(unsigned(NRow) - 1);
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- LINE

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- BEGIN
		-- IP impl.op.vars --- END

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- BEGIN
			stateOp <= stateOpInit;
			ackInvAssign_sig <= '0';
			ackInvSet_sig <= '0';
			rng <= '0';
			ixMemNext <= ixMemInvalid;

			-- IP impl.op.asyncrst --- END
			-- IP impl.op.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateOp=stateOpInit or (stateOp/=stateOpInv and (reqInvAssign='1' or reqInvSet='1'))) then
				if reqInvAssign='1' then
					-- IP impl.op.init.invAssign --- IBEGIN
					if rng='1' then
						ixMemNext <= assignIxMem;
					end if;

					ackInvAssign_sig <= '1';
					ackInvSet_sig <= '0';
					-- IP impl.op.init.invAssign --- IEND

					stateOp <= stateOpInv;

				elsif reqInvSet='1' then
					-- IP impl.op.init.invSet --- IBEGIN
					if setRng=tru8 then
						rng <= '1';
					else
						ixMemNext <= ixMemInvalid;
						rng <= '0';
					end if;

					ackInvAssign_sig <= '0';
					ackInvSet_sig <= '1';
					-- IP impl.op.init.invSet --- IEND

					stateOp <= stateOpInv;

				else
					-- IP impl.op.syncrst --- RBEGIN
					ackInvAssign_sig <= '0';
					ackInvSet_sig <= '0';

					-- IP impl.op.syncrst --- REND
					-- IP impl.op.syncrst.cust --- INSERT

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpInv then
				if ((reqInvAssign='0' and ackInvAssign_sig='1') or (reqInvSet='0' and ackInvSet_sig='1')) then
					-- IP impl.op.inv.reset --- IBEGIN
					ackInvAssign_sig <= '0';
					ackInvSet_sig <= '0';
					-- IP impl.op.inv.reset --- IEND

					stateOp <= stateOpInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: stock release from buffer operation (stockrls)
	------------------------------------------------------------------------

	-- IP impl.stockrls.wiring --- BEGIN
	enRowbufStockrls <= '1' when (stateStockrls=stateStockrlsRun or stateStockrls=stateStockrlsEol) else '0';
	stock <= drdRowAbuf when liveBNotA='1' else drdRowBbuf;
	-- IP impl.stockrls.wiring --- END

	-- IP impl.stockrls.wiring.cust --- LINE

	-- IP impl.stockrls.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.stockrls.vars --- BEGIN
		-- IP impl.stockrls.vars --- END

	begin
		if reset='1' then
			-- IP impl.stockrls.asyncrst --- BEGIN
			stateStockrls <= stateStockrlsInit;
			aRowbufStockrls <= 0;

			-- IP impl.stockrls.asyncrst --- END
			-- IP impl.stockrls.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateStockrls=stateStockrlsInit or rng='0') then
				-- IP impl.stockrls.syncrst --- BEGIN
				aRowbufStockrls <= 0;

				-- IP impl.stockrls.syncrst --- END
				-- IP impl.stockrls.syncrst.cust --- INSERT

				if (rng='1' and vsync='1' and unsigned(ixTExp)/=0) then
					stateStockrls <= stateStockrlsRun;

				else
					stateStockrls <= stateStockrlsInit;
				end if;

			elsif stateStockrls=stateStockrlsRun then
				if rgbFromVideoinAXIS_tvalid='1' then
					aRowbufStockrls <= aRowbufStockrls + 1; -- IP impl.stockrls.run.inc --- ILINE

					if rgbFromVideoinAXIS_tlast='1' then
						stateStockrls <= stateStockrlsEol;

					else
						stateStockrls <= stateStockrlsRun;
					end if;
				end if;

			elsif stateStockrls=stateStockrlsEol then
				if vsync='1' then
					stateStockrls <= stateStockrlsInit;

				else
					aRowbufStockrls <= 0; -- IP impl.stockrls.eol.reset --- ILINE

					stateStockrls <= stateStockrlsRun;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.stockrls.rising --- END

	------------------------------------------------------------------------
	-- implementation: streaming operation (stream)
	------------------------------------------------------------------------

	-- IP impl.stream.wiring --- BEGIN
	getInfoTixVState <= tixVState;

	getInfoTkst <= tkst;
	getInfoIxMem <= ixMem;

	getInfoIxMemAcq <= ixMemAcq;

	enRowAbuf <= '1' when ((liveBNotA='0' and enRowbufStream='1') or (liveBNotA='1' and enRowbufStockrls='1')) else '0';
	enRowBbuf <= '1' when ((liveBNotA='1' and enRowbufStream='1') or (liveBNotA='0' and enRowbufStockrls='1')) else '0';

	weRowAbuf <= '1' when liveBNotA='0' else '0';
	weRowBbuf <= '1' when liveBNotA='1' else '0';
	-- IP impl.stream.wiring --- END

	-- IP impl.stream.wiring.cust --- RBEGIN
	aRowAbuf <= std_logic_vector(to_unsigned(aRowbufStream, 11)) when liveBNotA='0'
				else std_logic_vector(to_unsigned(aRowbufStockrls, 11));

	aRowBbuf <= std_logic_vector(to_unsigned(aRowbufStream, 11)) when liveBNotA='1'
				else std_logic_vector(to_unsigned(aRowbufStockrls, 11));
	-- IP impl.stream.wiring.cust --- REND

	-- IP impl.stream.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.stream.vars --- RBEGIN
		variable col_lcl: natural range 0 to 2000;

		variable rshift: natural range 0 to 4;
		variable live: std_logic_vector(3*12-1 downto 0);
		variable r,g,b,pvt: unsigned(11 downto 0);
		variable exp: natural range 0 to 255;
		-- IP impl.stream.vars --- REND

	begin
		if reset='1' then
			-- IP impl.stream.asyncrst --- BEGIN
			stateStream <= stateStreamInit;
			tixVState <= tixVStateIdle;
			tkst <= (others => '0');
			ixMem <= ixMemInvalid;
			tkstAcq <= (others => '0');
			ixMemAcq <= ixMemInvalid;
			a0 <= (others => '0');
			liveBNotA <= '0';
			enRowbufStream <= '0';
			aRowbufStream <= 0;
			dwrRowbuf <= (others => '0');

			-- IP impl.stream.asyncrst --- END
			-- IP impl.stream.asyncrst.cust --- IBEGIN
			col_lcl := 0;
			-- IP impl.stream.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			if (stateStream=stateStreamInit or rng='0') then
				-- IP impl.stream.syncrst --- RBEGIN
				tkst <= (others => '0');
				ixMem <= ixMemInvalid;
				tkstAcq <= (others => '0');
				ixMemAcq <= ixMemInvalid;
				a0 <= (others => '0');
				liveBNotA <= '0';
				enRowbufStream <= '0';
				aRowbufStream <= 0;
				dwrRowbuf <= (others => '0');
	
				-- IP impl.stream.syncrst --- REND
				-- IP impl.stream.syncrst.cust --- IBEGIN
				col_lcl := 0;
				-- IP impl.stream.syncrst.cust --- IEND

				if rng='0' then
					tixVState <= tixVStateIdle; -- IP impl.stream.init.toIdle --- ILINE

					stateStream <= stateStreamInit;

				else
					stateStream <= stateStreamIdle;
				end if;

			elsif stateStream=stateStreamIdle then
				if (ixMemNext/=ixMemInvalid and ixMemNext/=ixMem and vsync='1' and unsigned(ixTExp)=0) then
					-- IP impl.stream.idle.start --- IBEGIN
					tkstAcq <= tkclksrcGetTkstTkst;
					ixMemAcq <= ixMemNext;
					a0 <= std_logic_vector( (unsigned(ixMemNext(3 downto 0)) & "0") + ("0" & unsigned(ixMemNext(3 downto 0))) );
					tixVState <= tixVStateAcq;
					-- IP impl.stream.idle.start --- IEND

					stateStream <= stateStreamRun;

				elsif ixMemNext=ixMem then
					tixVState <= tixVStateStall; -- IP impl.stream.idle.stall --- ILINE

					stateStream <= stateStreamIdle;
				end if;

			elsif stateStream=stateStreamRun then
				if rgbFromVideoinAXIS_tvalidm2='1' then
					-- IP impl.stream.run --- IBEGIN
					for i in 0 to 2 loop
						if rgbFromVideoinAXIS_tdatam2(12*i+11 downto 12*i+8)="1111" and unsigned(ixTExp)/=4 then -- first four bits one (>= 3840/4096 93.8%)
							live(12*i+12-1 downto 12*i) := (others => '1');
						elsif rgbFromVideoinAXIS_tdatam2(12*i+11 downto 12*i+8)="0000" and unsigned(ixTExp)/=0 then -- only last eight bits non-zero (< 256/4096 = 6.3%)
							live(12*i+12-1 downto 12*i) := (others => '0');
						else
							live(12*i+12-1 downto 12*i) := rgbFromVideoinAXIS_tdatam2(12*i+12-1 downto 12*i); -- TBD: work with _tdatam1 to simplify stockrls
						end if;
					end loop;

					-- detect "done" i.e. skip this ixTExp if none of the channels reads 1111_1111
					if stock(31 downto 24)="11111111" or stock(23 downto 16)="11111111" or stock(15 downto 8)="11111111" or unsigned(ixTExp)=0 then
						-- live is r & g & b
						r := unsigned(live(12*2+12-1 downto 12*2));
						g := unsigned(live(12*1+12-1 downto 12*1));
						b := unsigned(live(12*0+12-1 downto 12*0));

						if r>g and r>b then
							pvt := r;
						elsif g>b then
							pvt := g;
						else
							pvt := b;
						end if;

						if unsigned(ixTExp)=0 then
							exp := 0;
						else
							exp := to_integer(unsigned(stock(7 downto 0)) + 3);
						end if;

						rshift := getExp8of12(pvt);

						dwrRowbuf(31 downto 24) <= std_logic_vector(r(8+rshift-1 downto rshift));
						dwrRowbuf(23 downto 16) <= std_logic_vector(g(8+rshift-1 downto rshift));
						dwrRowbuf(15 downto 8) <= std_logic_vector(b(8+rshift-1 downto rshift));
						dwrRowbuf(7 downto 0) <= std_logic_vector(to_unsigned(exp + rshift, 8));

					else
						dwrRowbuf <= stock;
					end if;

					enRowbufStream <= '1';

					if col_lcl/=0 then
						aRowbufStream <= aRowbufStream + 1;
					end if;

					col_lcl := col_lcl + 1; -- in next clock cycle
					-- IP impl.stream.run --- IEND

					if col_lcl=unsigned(NCol) then
						stateStream <= stateStreamEol;

					else
						stateStream <= stateStreamRun;
					end if;

				else
					enRowbufStream <= '0'; -- IP impl.stream.run.reset --- ILINE

					stateStream <= stateStreamRun;
				end if;

			elsif stateStream=stateStreamEol then
				-- IP impl.stream.eol.pre --- IBEGIN
				enRowbufStream <= '0';
				aRowbufStream <= 0;

				col_lcl := 0;
				-- IP impl.stream.eol.pre --- IEND

				if vsync='1' then
					liveBNotA <= '0'; -- IP impl.stream.eol.expDone --- ILINE

					if unsigned(ixTExp)=0 then
						-- IP impl.stream.eol.done --- IBEGIN
						ixMem <= ixMemAcq;
						tkst <= tkstAcq;
						-- IP impl.stream.eol.done --- IEND

						stateStream <= stateStreamIdle;

					else
						stateStream <= stateStreamRun;
					end if;

				else
					-- IP impl.stream.eol.nextRow --- IBEGIN
					liveBNotA <= not liveBNotA;
					-- IP impl.stream.eol.nextRow --- IEND

					stateStream <= stateStreamRun;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.stream.rising --- END

	------------------------------------------------------------------------
	-- implementation: stock buffer swap to-then-from DDR memory (swap)
	------------------------------------------------------------------------

	-- IP impl.swap.wiring --- BEGIN
	enRowAbufB <= '1' when (liveBNotA_memclk='1' and enRowbufB='1') else '0';
	enRowBbufB <= '1' when (liveBNotA_memclk='0' and enRowbufB='1') else '0';

	weRowbufB <= '1' when (stateSwap=stateSwapIgrA or stateSwap=stateSwapIgrB) else '0';

	hdrmemAXI_awaddr <= hdrmemAXI_awaddr_sig;
	hdrmemAXI_awvalid <= '1' when stateSwap=stateSwapEgrB else '0';

	hdrmemAXI_wdata <= egrAXIS_tdata;
	hdrmemAXI_wlast <= '0' when ((reqSwapToEgrstr='1' and ackSwapToEgrstr='0') or egrAXIS_tlast='0') else '1';
	hdrmemAXI_wvalid <= egrAXIS_tvalid;

	reqToDdrifWr <= '1' when stateSwap=stateSwapEgrB else '0';

	hdrmemAXI_araddr <= hdrmemAXI_araddr_sig;
	hdrmemAXI_arvalid <= '1' when stateSwap=stateSwapIgrA else '0';

	reqToDdrifRd <= '1' when stateSwap=stateSwapIgrA else '0';

	reqSwapToEgrstr <= '1' when (stateSwap=stateSwapEgrB or stateSwap=stateSwapEgrC) else '0';

	reqSwapToIgrstr <= '1' when (stateSwap=stateSwapIgrA or stateSwap=stateSwapIgrB or stateSwap=stateSwapIgrC) else '0';

	egrAXIS_tready <= hdrmemAXI_wready;
	-- IP impl.swap.wiring --- END

	-- IP impl.swap.wiring.cust --- RBEGIN

	-- cf. source.egr (+ separate source.egrstr), pack.igr (+ separate pack.igrstr)

	-- sufficient DDR bandwidth for store-then-load

	---- shared buffer
	enRowbufB <= enRowbufBEgrstr when stateSwap=stateSwapEgrA or stateSwap=stateSwapEgrB or stateSwap=stateSwapEgrC
				else '1' when stateIgrstr=stateIgrstrRun
				else '0';

	aRowbufB <= std_logic_vector(to_unsigned(aRowbufBEgrstr, 9)) when stateSwap=stateSwapEgrA or stateSwap=stateSwapEgrB or stateSwap=stateSwapEgrC
					else std_logic_vector(to_unsigned(aRowbufBIgrstr, 9)) when stateSwap=stateSwapIgrA or stateSwap=stateSwapIgrB
					else (others => '0');

	---- egress portion

	-- buf size 8 kB or 32 bursts of 16x16 byte

	-- for now, up to 16 frames, fills 192/256 MByte

	-- one frame is 1024 + 512 = 1536 rows, or 12 MByte
	-- i.e. first frame from 0000_0000_0000 to 0101_1111_1111, second from 0110_0000_0000 to 1100_0000_0000
	-- addrEgr = (frame << 9) + (frame << 8) then increment by one each row

	-- ddrif adds 0000_0000 (16 beats per burst, 16 bytes / 4 words per beat)
	hdrmemAXI_awaddr_sig(4 downto 0) <= std_logic_vector(to_unsigned(burstSwap, 5));
	hdrmemAXI_awaddr_sig(17 downto 5) <= addrEgr; -- one row behind addrIgr

	---- ingress portion
	hdrmemAXI_araddr_sig(4 downto 0) <= std_logic_vector(to_unsigned(burstSwap, 5));
	hdrmemAXI_araddr_sig(17 downto 5) <= addrIgr; -- one row ahead of addrEgr
	-- IP impl.swap.wiring.cust --- REND

	-- IP impl.swap.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.swap.vars --- RBEGIN
		variable row_lcl: natural range 0 to 1499;

		constant imax: natural := 2;
		variable i: natural range 0 to imax;
		-- IP impl.swap.vars --- REND

	begin
		if resetMemclk='1' then
			-- IP impl.swap.asyncrst --- BEGIN
			stateSwap <= stateSwapInit;
			addrEgr <= (others => '0');
			addrIgr <= (others => '0');
			a0Egrstr <= 0;
			lenEgrstr <= 0;
			burstSwap <= 0;
			burstSwapLast <= 19;

			-- IP impl.swap.asyncrst --- END
			-- IP impl.swap.asyncrst.cust --- IBEGIN
			i := 0;
			-- IP impl.swap.asyncrst.cust --- IEND

		elsif rising_edge(memclk) then
			if stateSwap=stateSwapInit then
				-- IP impl.swap.syncrst --- RBEGIN
				-- IP impl.swap.syncrst --- REND
				-- IP impl.swap.syncrst.cust --- IBEGIN
				i := 0;
				-- IP impl.swap.syncrst.cust --- IEND

				if (rng_memclk='1' and vsync_sig_memclk='1' and rgbFromVideoinAXIS_tlast_sig_memclk='1') then
					stateSwap <= stateSwapStart;

				else
					stateSwap <= stateSwapInit;
				end if;

			elsif stateSwap=stateSwapStart then
				if rng_memclk='0' then
					stateSwap <= stateSwapInit;

				elsif i=imax then
					-- IP impl.swap.start.done --- IBEGIN
					addrEgr <= a0_memclk & "00000000";
					addrIgr <= a0_memclk & "00000000";

					row_lcl := 0;
					-- IP impl.swap.start.done --- IEND

					stateSwap <= stateSwapIgrA;

				else
					-- IP impl.swap.start.inc --- IBEGIN
					-- make sure a0_memclk CDC completes at ixTExp=0
					i := i + 1;
					-- IP impl.swap.start.inc --- IEND

					stateSwap <= stateSwapStart;
				end if;

			elsif stateSwap=stateSwapIdle then
				if rng_memclk='0' then
					stateSwap <= stateSwapInit;

				elsif rgbFromVideoinAXIS_tlast_sig_memclk='0' then
					stateSwap <= stateSwapEgrA;
				end if;

			elsif stateSwap=stateSwapEgrA then
				-- IP impl.swap.egrA.setAddr --- IBEGIN
				a0Egrstr <= to_integer(to_unsigned(burstSwap, 5) & "0000");
				lenEgrstr <= 16;
				-- IP impl.swap.egrA.setAddr --- IEND

				stateSwap <= stateSwapEgrB;

			elsif stateSwap=stateSwapEgrB then
				if (ackToDdrifWr='1' and hdrmemAXI_awready='1') then
					stateSwap <= stateSwapEgrC;
				end if;

			elsif stateSwap=stateSwapEgrC then
				if dneSwapToEgrstr='1' then
					addrEgr <= std_logic_vector(unsigned(addrEgr) + 1); -- IP impl.swap.egrC.inc --- ILINE

					if rng_memclk='0' then
						stateSwap <= stateSwapInit;

					elsif burstSwap=burstSwapLast then
						-- IP impl.swap.egrC.bufDone --- IBEGIN
						burstSwap <= 0;
						-- IP impl.swap.egrC.bufDone --- IEND

						if row_lcl=rowLast then
							stateSwap <= stateSwapInit;

						else
							stateSwap <= stateSwapIgrA;
						end if;

					else
						-- IP impl.swap.egrC.nextBurst --- IBEGIN
						burstSwap <= burstSwap + 1;
						-- IP impl.swap.egrC.nextBurst --- IEND

						stateSwap <= stateSwapEgrA;
					end if;
				end if;

			elsif stateSwap=stateSwapIgrA then
				if (ackToDdrifRd='1' and hdrmemAXI_arready='1') then
					stateSwap <= stateSwapIgrB;
				end if;

			elsif stateSwap=stateSwapIgrB then
				if burstSwap=burstSwapLast then
					stateSwap <= stateSwapIgrC;

				else
					burstSwap <= burstSwap + 1; -- IP impl.swap.igrB.nextBurst --- ILINE

					stateSwap <= stateSwapIgrA;
				end if;

			elsif stateSwap=stateSwapIgrC then
				if dneSwapToIgrstr='1' then
					-- IP impl.swap.igrC.done --- IBEGIN
					addrIgr <= std_logic_vector(unsigned(addrIgr) + 1);

					burstSwap <= 0;

					row_lcl := row_lcl + 1;
					-- IP impl.swap.igrC.done --- IEND

					if rng_memclk='0' then
						stateSwap <= stateSwapInit;

					elsif row_lcl=1 then
						stateSwap <= stateSwapWaitA;

					else
						stateSwap <= stateSwapWaitB;
					end if;
				end if;

			elsif stateSwap=stateSwapWaitA then
				if rgbFromVideoinAXIS_tlast_sig_memclk='0' then
					stateSwap <= stateSwapWaitB;
				end if;

			elsif stateSwap=stateSwapWaitB then
				if rgbFromVideoinAXIS_tlast_sig_memclk='1' then
					stateSwap <= stateSwapIdle;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.swap.rising --- END

	------------------------------------------------------------------------
	-- implementation: mclk to memclk CDC sampling (mclkToMemclkSample)
	------------------------------------------------------------------------

	-- IP impl.mclkToMemclkSample.wiring --- BEGIN
	-- IP impl.mclkToMemclkSample.wiring --- END

	-- IP impl.mclkToMemclkSample.wiring.cust --- LINE

	-- IP impl.mclkToMemclkSample.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.mclkToMemclkSample.vars --- BEGIN
		-- IP impl.mclkToMemclkSample.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.mclkToMemclkSample.asyncrst --- BEGIN
			rng_memclk <= '0';
			rng_to_memclkm1 <= '0';
			rng_to_memclkm2 <= '0';
			a0_memclk <= (others => '0');
			a0_to_memclkm1 <= (others => '0');
			a0_to_memclkm2 <= (others => '0');
			liveBNotA_memclk <= '0';
			liveBNotA_to_memclkm1 <= '0';
			liveBNotA_to_memclkm2 <= '0';
			rgbFromVideoinAXIS_tlast_sig_memclk <= '0';
			rgbFromVideoinAXIS_tlast_sig_to_memclkm1 <= '0';
			rgbFromVideoinAXIS_tlast_sig_to_memclkm2 <= '0';
			vsync_sig_memclk <= '0';
			vsync_sig_to_memclkm1 <= '0';
			vsync_sig_to_memclkm2 <= '0';

			-- IP impl.mclkToMemclkSample.asyncrst --- END
			-- IP impl.mclkToMemclkSample.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if rng_to_memclkm1=rng_to_memclkm2 then
				rng_memclk <= rng_to_memclkm2;
			end if;
			rng_to_memclkm1 <= rng_to_memclk;
			rng_to_memclkm2 <= rng_to_memclkm1;

			if a0_to_memclkm1=a0_to_memclkm2 then
				a0_memclk <= a0_to_memclkm2;
			end if;
			a0_to_memclkm1 <= a0_to_memclk;
			a0_to_memclkm2 <= a0_to_memclkm1;

			if liveBNotA_to_memclkm1=liveBNotA_to_memclkm2 then
				liveBNotA_memclk <= liveBNotA_to_memclkm2;
			end if;
			liveBNotA_to_memclkm1 <= liveBNotA_to_memclk;
			liveBNotA_to_memclkm2 <= liveBNotA_to_memclkm1;

			if rgbFromVideoinAXIS_tlast_sig_to_memclkm1=rgbFromVideoinAXIS_tlast_sig_to_memclkm2 then
				rgbFromVideoinAXIS_tlast_sig_memclk <= rgbFromVideoinAXIS_tlast_sig_to_memclkm2;
			end if;
			rgbFromVideoinAXIS_tlast_sig_to_memclkm1 <= rgbFromVideoinAXIS_tlast_sig_to_memclk;
			rgbFromVideoinAXIS_tlast_sig_to_memclkm2 <= rgbFromVideoinAXIS_tlast_sig_to_memclkm1;

			if vsync_sig_to_memclkm1=vsync_sig_to_memclkm2 then
				vsync_sig_memclk <= vsync_sig_to_memclkm2;
			end if;
			vsync_sig_to_memclkm1 <= vsync_sig_to_memclk;
			vsync_sig_to_memclkm2 <= vsync_sig_to_memclkm1;

		end if;
	end process;
	-- IP impl.mclkToMemclkSample.rising --- END

	------------------------------------------------------------------------
	-- implementation: mclk to memclk CDC stretching (mclkToMemclkStretch)
	------------------------------------------------------------------------

	-- IP impl.mclkToMemclkStretch.wiring --- BEGIN
	-- IP impl.mclkToMemclkStretch.wiring --- END

	-- IP impl.mclkToMemclkStretch.wiring.cust --- LINE

	-- IP impl.mclkToMemclkStretch.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.mclkToMemclkStretch.vars --- BEGIN
		constant imax: natural := 1;

		variable rng_i: natural range 0 to imax;
		variable a0_i: natural range 0 to imax;
		variable liveBNotA_i: natural range 0 to imax;
		variable rgbFromVideoinAXIS_tlast_sig_i: natural range 0 to imax;
		variable vsync_sig_i: natural range 0 to imax;
		-- IP impl.mclkToMemclkStretch.vars --- END

	begin
		if reset='1' then
			-- IP impl.mclkToMemclkStretch.asyncrst --- BEGIN
			rng_to_memclk <= '0';
			a0_to_memclk <= (others => '0');
			liveBNotA_to_memclk <= '0';
			rgbFromVideoinAXIS_tlast_sig_to_memclk <= '0';
			vsync_sig_to_memclk <= '0';

			rng_i := 0;
			a0_i := 0;
			liveBNotA_i := 0;
			rgbFromVideoinAXIS_tlast_sig_i := 0;
			vsync_sig_i := 0;
			-- IP impl.mclkToMemclkStretch.asyncrst --- END
			-- IP impl.mclkToMemclkStretch.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if rng_i=imax then
				if rng/=rng_to_memclk then
					rng_to_memclk <= rng;
					rng_i := 0;
				end if;
			else
				rng_i := rng_i + 1;
			end if;

			if a0_i=imax then
				if a0/=a0_to_memclk then
					a0_to_memclk <= a0;
					a0_i := 0;
				end if;
			else
				a0_i := a0_i + 1;
			end if;

			if liveBNotA_i=imax then
				if liveBNotA/=liveBNotA_to_memclk then
					liveBNotA_to_memclk <= liveBNotA;
					liveBNotA_i := 0;
				end if;
			else
				liveBNotA_i := liveBNotA_i + 1;
			end if;

			if rgbFromVideoinAXIS_tlast_sig_i=imax then
				if rgbFromVideoinAXIS_tlast_sig/=rgbFromVideoinAXIS_tlast_sig_to_memclk then
					rgbFromVideoinAXIS_tlast_sig_to_memclk <= rgbFromVideoinAXIS_tlast_sig;
					rgbFromVideoinAXIS_tlast_sig_i := 0;
				end if;
			else
				rgbFromVideoinAXIS_tlast_sig_i := rgbFromVideoinAXIS_tlast_sig_i + 1;
			end if;

			if vsync_sig_i=imax then
				if vsync_sig/=vsync_sig_to_memclk then
					vsync_sig_to_memclk <= vsync_sig;
					vsync_sig_i := 0;
				end if;
			else
				vsync_sig_i := vsync_sig_i + 1;
			end if;

		end if;
	end process;
	-- IP impl.mclkToMemclkStretch.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- IBEGIN
	vsync_sig <= vsync;
	rgbFromVideoinAXIS_tlast_sig <= rgbFromVideoinAXIS_tlast;
	-- IP impl.oth.cust --- IEND

end Rtl;


-- file Hostif_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Hostif_8c100ea18901433eb4f7c0fdbf115e06 hostif_Easy_v1_0 easy model host interface implementation
-- copyright: (C) 2017-2024 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

-- module parameters:
-- phytype (axi/spi/uart): axi
-- wA (address width for AXI [bit]): 32
-- wD (data width 16/32/64/128 for AXI [bit]): 32
-- fSclk (baud rate for SPI/UART [bps]): 115200

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Hostif_8c100ea18901433eb4f7c0fdbf115e06 is
	generic (
		fMclk: natural := 50000
	);
	port (
		reset: in std_logic;
		mclk: in std_logic;
		tkclk: in std_logic;
		commok: out std_logic;
		reqReset: out std_logic;

		identGetUnt: in std_logic_vector(95 downto 0);
		identGetVer: in std_logic_vector(63 downto 0);
		identGetHash: in std_logic_vector(63 downto 0);
		identGetWho: in std_logic_vector(63 downto 0);

		identGetCfgFMclk: in std_logic_vector(31 downto 0);
		identGetCfgFMemclk: in std_logic_vector(31 downto 0);

		reqInvCamifConfig: out std_logic;
		ackInvCamifConfig: in std_logic;

		camifConfigHdrNotFix: out std_logic_vector(7 downto 0);
		camifConfigSynthNotLive: out std_logic_vector(7 downto 0);

		reqInvCamifConfigSynth: out std_logic;
		ackInvCamifConfigSynth: in std_logic;

		camifConfigSynthTixVSynthmode: out std_logic_vector(7 downto 0);
		camifConfigSynthTFramepad: out std_logic_vector(15 downto 0);
		camifConfigSynthTLinepad: out std_logic_vector(7 downto 0);

		reqInvCamifSetReg: out std_logic;
		ackInvCamifSetReg: in std_logic;

		camifSetRegAddr: out std_logic_vector(15 downto 0);
		camifSetRegVal: out std_logic_vector(7 downto 0);

		reqInvCamifGetReg: out std_logic;
		ackInvCamifGetReg: in std_logic;

		camifGetRegAddr: out std_logic_vector(15 downto 0);
		camifGetRegVal: in std_logic_vector(7 downto 0);

		reqInvCamifModReg: out std_logic;
		ackInvCamifModReg: in std_logic;

		camifModRegAddr: out std_logic_vector(15 downto 0);
		camifModRegMask: out std_logic_vector(7 downto 0);
		camifModRegVal: out std_logic_vector(7 downto 0);

		reqInvCamifSetCorereg: out std_logic;
		ackInvCamifSetCorereg: in std_logic;

		camifSetCoreregAddr: out std_logic_vector(7 downto 0);
		camifSetCoreregVal: out std_logic_vector(31 downto 0);

		reqInvCamifGetCorereg: out std_logic;
		ackInvCamifGetCorereg: in std_logic;

		camifGetCoreregAddr: out std_logic_vector(7 downto 0);
		camifGetCoreregVal: in std_logic_vector(31 downto 0);

		reqInvCornerAcquire: out std_logic;
		ackInvCornerAcquire: in std_logic;

		reqInvCornerConfig: out std_logic;
		ackInvCornerConfig: in std_logic;

		cornerConfigLinNotLog: out std_logic_vector(7 downto 0);
		cornerConfigThd: out std_logic_vector(7 downto 0);
		cornerConfigRow0: out std_logic_vector(15 downto 0);
		cornerConfigRow1: out std_logic_vector(15 downto 0);
		cornerConfigCol0: out std_logic_vector(15 downto 0);
		cornerConfigCol1: out std_logic_vector(15 downto 0);

		cornerGetInfoTixVState: in std_logic_vector(7 downto 0);
		cornerGetInfoTkst: in std_logic_vector(31 downto 0);
		cornerGetInfoScoreMin: in std_logic_vector(7 downto 0);
		cornerGetInfoScoreMax: in std_logic_vector(7 downto 0);

		reqInvCornerSet: out std_logic;
		ackInvCornerSet: in std_logic;

		cornerSetRng: out std_logic_vector(7 downto 0);

		reqInvCornerUnlock: out std_logic;
		ackInvCornerUnlock: in std_logic;

		ddrifGetStatsNRdA: in std_logic_vector(31 downto 0);
		ddrifGetStatsNRdB: in std_logic_vector(31 downto 0);
		ddrifGetStatsNWrA: in std_logic_vector(31 downto 0);
		ddrifGetStatsNWrB: in std_logic_vector(31 downto 0);

		reqInvDecimAcquire: out std_logic;
		ackInvDecimAcquire: in std_logic;

		decimAcquireIxTExp: out std_logic_vector(7 downto 0);

		reqInvDecimConfig: out std_logic;
		ackInvDecimConfig: in std_logic;

		decimConfigRgbNotGray: out std_logic_vector(7 downto 0);
		decimConfigEdge: out std_logic_vector(7 downto 0);
		decimConfigEdge2: out std_logic_vector(15 downto 0);
		decimConfigNDecim: out std_logic_vector(15 downto 0);

		decimGetInfoTixVState: in std_logic_vector(7 downto 0);
		decimGetInfoTkst: in std_logic_vector(31 downto 0);

		reqInvDecimSet: out std_logic;
		ackInvDecimSet: in std_logic;

		decimSetRng: out std_logic_vector(7 downto 0);

		reqInvDecimUnlock: out std_logic;
		ackInvDecimUnlock: in std_logic;

		reqInvDirectorConfig: out std_logic;
		ackInvDirectorConfig: in std_logic;

		directorConfigNRowRaw: out std_logic_vector(15 downto 0);
		directorConfigNColRaw: out std_logic_vector(15 downto 0);

		reqInvDirectorSet: out std_logic;
		ackInvDirectorSet: in std_logic;

		directorSetRng: out std_logic_vector(7 downto 0);

		reqInvHdrengAssign: out std_logic;
		ackInvHdrengAssign: in std_logic;

		hdrengAssignIxMem: out std_logic_vector(7 downto 0);

		hdrengGetInfoTixVState: in std_logic_vector(7 downto 0);
		hdrengGetInfoTkst: in std_logic_vector(31 downto 0);
		hdrengGetInfoIxMem: in std_logic_vector(7 downto 0);
		hdrengGetInfoIxMemAcq: in std_logic_vector(7 downto 0);

		reqInvHdrengSet: out std_logic;
		ackInvHdrengSet: in std_logic;

		hdrengSetRng: out std_logic_vector(7 downto 0);

		reqInvLaserSet: out std_logic;
		ackInvLaserSet: in std_logic;

		laserSetL: out std_logic_vector(15 downto 0);
		laserSetR: out std_logic_vector(15 downto 0);

		reqInvRotaryConfig: out std_logic;
		ackInvRotaryConfig: in std_logic;

		rotaryConfigTixVStepmode: out std_logic_vector(7 downto 0);
		rotaryConfigTStep: out std_logic_vector(7 downto 0);

		rotaryGetInfoTixVState: in std_logic_vector(7 downto 0);
		rotaryGetInfoAngle: in std_logic_vector(15 downto 0);

		reqInvRotaryMoveto: out std_logic;
		ackInvRotaryMoveto: in std_logic;

		rotaryMovetoAngle: out std_logic_vector(15 downto 0);

		reqInvRotarySet: out std_logic;
		ackInvRotarySet: in std_logic;

		rotarySetRng: out std_logic_vector(7 downto 0);
		rotarySetCcwNotCw: out std_logic_vector(7 downto 0);

		reqInvRotaryZero: out std_logic;
		ackInvRotaryZero: in std_logic;

		reqInvStepmuxSet: out std_logic;
		ackInvStepmuxSet: in std_logic;

		stepmuxSetLinNotRot: out std_logic_vector(7 downto 0);

		tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0);

		reqInvTkclksrcSetTkst: out std_logic;
		ackInvTkclksrcSetTkst: in std_logic;

		tkclksrcSetTkstTkst: out std_logic_vector(31 downto 0);

		reqInvTraceAcquire: out std_logic;
		ackInvTraceAcquire: in std_logic;

		reqInvTraceConfig: out std_logic;
		ackInvTraceConfig: in std_logic;

		traceConfigTixVOrient: out std_logic_vector(7 downto 0);
		traceConfigRow0: out std_logic_vector(15 downto 0);
		traceConfigCol0: out std_logic_vector(15 downto 0);

		traceGetInfoTixVState: in std_logic_vector(7 downto 0);
		traceGetInfoTkst: in std_logic_vector(31 downto 0);

		reqInvTraceUnlock: out std_logic;
		ackInvTraceUnlock: in std_logic;

		cputrackGetInfoTixVState: in std_logic_vector(7 downto 0);
		cputrackGetInfoTCapt: in std_logic_vector(31 downto 0);
		cputrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

		reqInvCputrackSelect: out std_logic;
		ackInvCputrackSelect: in std_logic;

		cputrackSelectTixVCapture: out std_logic_vector(7 downto 0);
		cputrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);
		cputrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);
		cputrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);
		cputrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

		reqInvCputrackSet: out std_logic;
		ackInvCputrackSet: in std_logic;

		cputrackSetRng: out std_logic_vector(7 downto 0);
		cputrackSetTCaptMax: out std_logic_vector(31 downto 0);

		reqInvHshktrackClearMask: out std_logic;
		ackInvHshktrackClearMask: in std_logic;

		hshktrackGetInfoTixVState: in std_logic_vector(7 downto 0);
		hshktrackGetInfoTCapt: in std_logic_vector(31 downto 0);
		hshktrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

		reqInvHshktrackSelect: out std_logic;
		ackInvHshktrackSelect: in std_logic;

		hshktrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);
		hshktrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);
		hshktrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);
		hshktrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

		reqInvHshktrackSet: out std_logic;
		ackInvHshktrackSet: in std_logic;

		hshktrackSetRng: out std_logic_vector(7 downto 0);
		hshktrackSetTCaptMax: out std_logic_vector(31 downto 0);

		reqInvHshktrackSetMask: out std_logic;
		ackInvHshktrackSetMask: in std_logic;

		hshktrackSetMaskTixVCapture: out std_logic_vector(7 downto 0);

		reqInvMemtrackClearMask: out std_logic;
		ackInvMemtrackClearMask: in std_logic;

		memtrackGetInfoTixVState: in std_logic_vector(7 downto 0);
		memtrackGetInfoTCapt: in std_logic_vector(31 downto 0);
		memtrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

		reqInvMemtrackSelect: out std_logic;
		ackInvMemtrackSelect: in std_logic;

		memtrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);
		memtrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);
		memtrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);
		memtrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

		reqInvMemtrackSet: out std_logic;
		ackInvMemtrackSet: in std_logic;

		memtrackSetRng: out std_logic_vector(7 downto 0);
		memtrackSetTCaptMax: out std_logic_vector(31 downto 0);

		reqInvMemtrackSetMask: out std_logic;
		ackInvMemtrackSetMask: in std_logic;

		memtrackSetMaskTixVCapture: out std_logic_vector(7 downto 0);

		vidtrackGetInfoTixVState: in std_logic_vector(7 downto 0);
		vidtrackGetInfoTCapt: in std_logic_vector(31 downto 0);
		vidtrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

		reqInvVidtrackSelect: out std_logic;
		ackInvVidtrackSelect: in std_logic;

		vidtrackSelectTixVCapture: out std_logic_vector(7 downto 0);
		vidtrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);
		vidtrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);
		vidtrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);
		vidtrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

		reqInvVidtrackSet: out std_logic;
		ackInvVidtrackSet: in std_logic;

		vidtrackSetRng: out std_logic_vector(7 downto 0);
		vidtrackSetTCaptMax: out std_logic_vector(31 downto 0);

		reqPvwbufFromDecim: out std_logic;
		ackPvwbufFromDecim: in std_logic;
		dnePvwbufFromDecim: out std_logic;
		avllenPvwbufFromDecim: in std_logic_vector(31 downto 0);

		pvwbufFromDecimAXIS_tready: out std_logic;
		pvwbufFromDecimAXIS_tvalid: in std_logic;
		pvwbufFromDecimAXIS_tdata: in std_logic_vector(31 downto 0);
		pvwbufFromDecimAXIS_tlast: in std_logic;

		reqCoobufFromCorner: out std_logic;
		ackCoobufFromCorner: in std_logic;
		dneCoobufFromCorner: out std_logic;
		avllenCoobufFromCorner: in std_logic_vector(31 downto 0);

		reqFlgbufFromTrace: out std_logic;
		ackFlgbufFromTrace: in std_logic;

		coobufFromCornerAXIS_tready: out std_logic;
		coobufFromCornerAXIS_tvalid: in std_logic;
		coobufFromCornerAXIS_tdata: in std_logic_vector(31 downto 0);
		coobufFromCornerAXIS_tlast: in std_logic;

		dneFlgbufFromTrace: out std_logic;
		avllenFlgbufFromTrace: in std_logic_vector(31 downto 0);

		flgbufFromTraceAXIS_tready: out std_logic;
		flgbufFromTraceAXIS_tvalid: in std_logic;
		flgbufFromTraceAXIS_tdata: in std_logic_vector(31 downto 0);
		flgbufFromTraceAXIS_tlast: in std_logic;

		reqSeqbufFromCputrack: out std_logic;
		ackSeqbufFromCputrack: in std_logic;
		dneSeqbufFromCputrack: out std_logic;
		avllenSeqbufFromCputrack: in std_logic_vector(31 downto 0);

		seqbufFromCputrackAXIS_tready: out std_logic;
		seqbufFromCputrackAXIS_tvalid: in std_logic;
		seqbufFromCputrackAXIS_tdata: in std_logic_vector(31 downto 0);
		seqbufFromCputrackAXIS_tlast: in std_logic;

		reqSeqbufFromHshktrack: out std_logic;
		ackSeqbufFromHshktrack: in std_logic;
		dneSeqbufFromHshktrack: out std_logic;
		avllenSeqbufFromHshktrack: in std_logic_vector(31 downto 0);

		reqSeqbufFromMemtrack: out std_logic;
		ackSeqbufFromMemtrack: in std_logic;
		dneSeqbufFromMemtrack: out std_logic;
		avllenSeqbufFromMemtrack: in std_logic_vector(31 downto 0);

		seqbufFromHshktrackAXIS_tready: out std_logic;
		seqbufFromHshktrackAXIS_tvalid: in std_logic;
		seqbufFromHshktrackAXIS_tdata: in std_logic_vector(31 downto 0);
		seqbufFromHshktrackAXIS_tlast: in std_logic;

		seqbufFromMemtrackAXIS_tready: out std_logic;

		reqSeqbufFromVidtrack: out std_logic;
		ackSeqbufFromVidtrack: in std_logic;
		dneSeqbufFromVidtrack: out std_logic;
		avllenSeqbufFromVidtrack: in std_logic_vector(31 downto 0);

		seqbufFromMemtrackAXIS_tvalid: in std_logic;
		seqbufFromMemtrackAXIS_tdata: in std_logic_vector(31 downto 0);
		seqbufFromMemtrackAXIS_tlast: in std_logic;

		seqbufFromVidtrackAXIS_tready: out std_logic;
		seqbufFromVidtrackAXIS_tvalid: in std_logic;
		seqbufFromVidtrackAXIS_tdata: in std_logic_vector(31 downto 0);
		seqbufFromVidtrackAXIS_tlast: in std_logic;

		AXIL_araddr: in std_logic_vector(31 downto 0);
		AXIL_arprot: in std_logic_vector(2 downto 0);
		AXIL_arready: out std_logic;
		AXIL_arvalid: in std_logic;
		AXIL_rdata: out std_logic_vector(31 downto 0);
		AXIL_rready: in std_logic;
		AXIL_rresp: out std_logic_vector(1 downto 0);
		AXIL_rvalid: out std_logic;
		AXIL_rlast: out std_logic;
		AXIL_awaddr: in std_logic_vector(31 downto 0);
		AXIL_awprot: in std_logic_vector(2 downto 0);
		AXIL_awready: out std_logic;
		AXIL_awvalid: in std_logic;
		AXIL_wdata: in std_logic_vector(31 downto 0);
		AXIL_wready: out std_logic;
		AXIL_wstrb: in std_logic_vector(3 downto 0);
		AXIL_wvalid: in std_logic;
		AXIL_bready: in std_logic;
		AXIL_bresp: out std_logic_vector(1 downto 0);
		AXIL_bvalid: out std_logic;

		stateOp_dbg: out std_logic_vector(7 downto 0)
	);
end Hostif_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Hostif_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Axislave_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
		generic (
			fMclk: natural := 50000;

			wA: natural := 32;
			wD: natural := 32
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;

			req: in std_logic;
			ack: out std_logic;
			dne: out std_logic;

			sendNotRecv: in std_logic;
			len: in std_logic_vector(31 downto 0);

			recvAXIS_tready: in std_logic;
			recvAXIS_tvalid: out std_logic;
			recvAXIS_tdata: out std_logic_vector(wD-1 downto 0);
			recvAXIS_tlast: out std_logic;

			sendAXIS_tready: out std_logic;
			sendAXIS_tvalid: in std_logic;
			sendAXIS_tdata: in std_logic_vector(wD-1 downto 0);
			sendAXIS_tlast: in std_logic;

			AXIL_araddr: in std_logic_vector(wA-1 downto 0);
			AXIL_arprot: in std_logic_vector(2 downto 0);
			AXIL_arready: out std_logic;
			AXIL_arvalid: in std_logic;

			AXIL_rdata: out std_logic_vector(wD-1 downto 0);
			AXIL_rready: in std_logic;
			AXIL_rresp: out std_logic_vector(1 downto 0);
			AXIL_rvalid: out std_logic;
			AXIL_rlast: out std_logic;

			AXIL_awaddr: in std_logic_vector(wA-1 downto 0);
			AXIL_awprot: in std_logic_vector(2 downto 0);
			AXIL_awready: out std_logic;
			AXIL_awvalid: in std_logic;

			AXIL_wdata: in std_logic_vector(wD-1 downto 0);
			AXIL_wready: out std_logic;
			AXIL_wstrb: in std_logic_vector(wD/8-1 downto 0);
			AXIL_wvalid: in std_logic;

			AXIL_bready: in std_logic;
			AXIL_bresp: out std_logic_vector(1 downto 0);
			AXIL_bvalid: out std_logic
		);
	end component;

	component Crc8005_32_8c100ea18901433eb4f7c0fdbf115e06 is
		generic (
			initInvert: boolean := false;
			byteFlip: boolean := false;
			outFlip: boolean := false;
			outInvert: boolean := false
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;

			AXIS_tready: out std_logic;
			AXIS_tvalid: in std_logic;
			AXIS_tdata: in std_logic_vector(31 downto 0);
			AXIS_tkeep: in std_logic_vector(3 downto 0);
			AXIS_tlast: in std_logic;

			crc: out std_logic_vector(15 downto 0);
			validCrc: out std_logic
		);
	end component;

	component Timeout_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
		generic (
			twait: natural range 1 to 10000 := 100
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;
			tkclk: in std_logic;

			restart: in std_logic;
			timeout: out std_logic
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant wD: natural := 32;

	--- main operation
	type stateOp_t is (
		stateOpInit,
		stateOpIdle,
		stateOpRxopA, stateOpRxopB, stateOpRxopC, stateOpRxopD, stateOpRxopE,
		stateOpTxpollA, stateOpTxpollB, stateOpTxpollC, stateOpTxpollD, stateOpTxpollE, stateOpTxpollF, stateOpTxpollG,
		stateOpTxA, stateOpTxE, stateOpTxB, stateOpTxC, stateOpTxD, stateOpTxF, stateOpTxG,
		stateOpTxbufA, stateOpTxbufB, stateOpTxbufC, stateOpTxbufD, stateOpTxbufE, stateOpTxbufF, stateOpTxbufG, stateOpTxbufH,
		stateOpRxA, stateOpRxB, stateOpRxC, stateOpRxD,
		stateOpRxbufA, stateOpRxbufB, stateOpRxbufC, stateOpRxbufD, stateOpRxbufE, stateOpRxbufF,
		stateOpInv
	);
	signal stateOp: stateOp_t;

	constant sizeOpbuf: natural := 12;
	constant opbufLastAXIS_tkeep: std_logic_vector(wD/8-1 downto 0) := "0001";
	type opbuf_t is array (0 to sizeOpbuf-1) of std_logic_vector(7 downto 0);
	signal opbuf: opbuf_t;

	signal txNotRx: std_logic;

	signal reqRxtx: std_logic;
	signal ackRxtx: std_logic;
	signal dneRxtx: std_logic;

	signal rxtxlen: std_logic_vector(31 downto 0);

	signal tixVBuffer: std_logic_vector(7 downto 0);
	signal tixVController: std_logic_vector(7 downto 0); -- cmd
	signal tixVCommand: std_logic_vector(7 downto 0); -- cmd
	signal tixVBufxfop: std_logic_vector(7 downto 0); -- bufxf

	constant sizePollbuf: natural := 8;
	constant pollbufLastAXIS_tkeep: std_logic_vector(wD/8-1 downto 0) := "1111";
	type pollbuf_t is array (0 to sizePollbuf-1) of std_logic_vector(7 downto 0);
	signal pollbuf: pollbuf_t;

	constant sizeInvbuf: natural := 12; -- should include CRC
	type invbuf_t is array (0 to sizeInvbuf-1) of std_logic_vector(7 downto 0);
	signal invbuf: invbuf_t;

	constant sizeRetbuf: natural := 40; -- should include CRC
	type retbuf_t is array (0 to sizeRetbuf-1) of std_logic_vector(7 downto 0);
	signal retbuf: retbuf_t;

	signal commok_sig: std_logic;
	signal reqReset_sig: std_logic;

	signal cmdvalid: std_logic;

	signal lenRet: std_logic_vector(15 downto 0);

	signal lenInv: std_logic_vector(15 downto 0);

	signal reqInv: std_logic;
	signal ackInv: std_logic;

	signal txbufvalid: std_logic;

	signal reqTxbuf: std_logic;
	signal ackTxbuf: std_logic;
	signal dneTxbuf: std_logic;

	signal avllenTxbuf: std_logic_vector(31 downto 0);

	signal txbufAXIS_tready: std_logic;
	signal txbufAXIS_tvalid: std_logic;
	signal txbufAXIS_tdata: std_logic_vector(wD-1 downto 0);
	signal txbufAXIS_tlast: std_logic;

	signal rxbufvalid: std_logic;

	signal reqRxbuf: std_logic;
	signal ackRxbuf: std_logic;
	signal dneRxbuf: std_logic;

	signal avllenRxbuf: std_logic_vector(31 downto 0);

	signal rxbufAXIS_tready: std_logic;
	signal rxbufAXIS_tvalid: std_logic;
	signal rxbufAXIS_tdata: std_logic_vector(wD-1 downto 0);
	signal rxbufAXIS_tlast: std_logic;

	signal rxbuflast: std_logic;

	signal crcAXIS_tdata: std_logic_vector(wD-1 downto 0);
	signal crcAXIS_tkeep: std_logic_vector(wD/8-1 downto 0);
	signal crcAXIS_tlast: std_logic;
	signal crcAXIS_tlast_sig: std_logic;

	signal rxlen: std_logic_vector(31 downto 0);

	signal txlen: std_logic_vector(31 downto 0);

	signal txAXIS_tdata: std_logic_vector(wD-1 downto 0);
	signal txAXIS_tlast: std_logic;

	signal txlast: std_logic;

	signal restartWordto: std_logic;
	signal restartXferto: std_logic;

	---- myCrc
	signal crc: std_logic_vector(15 downto 0);
	signal validCrc: std_logic;

	---- myRx
	signal rxAXIS_tdata: std_logic_vector(wD-1 downto 0);
	signal rxAXIS_tlast: std_logic;

	---- myWordto
	signal wordto: std_logic;

	---- myXferto
	signal xferto: std_logic;

	---- handshake
	-- op to myCrc
	signal crcAXIS_tready: std_logic;
	signal crcAXIS_tvalid: std_logic;

	-- op to myRx
	signal reqRx: std_logic;
	signal ackRx: std_logic;
	signal dneRx: std_logic;

	signal rxAXIS_tready: std_logic;
	signal rxAXIS_tvalid: std_logic;

	-- op to myTx
	signal reqTx: std_logic;
	signal ackTx: std_logic;
	signal dneTx: std_logic;

	signal txAXIS_tready: std_logic;
	signal txAXIS_tvalid: std_logic;

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myCrc : Crc8005_32_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			reset => reset,
			mclk => mclk,

			AXIS_tready => crcAXIS_tready,
			AXIS_tvalid => crcAXIS_tvalid,
			AXIS_tdata => crcAXIS_tdata,
			AXIS_tkeep => crcAXIS_tkeep,
			AXIS_tlast => crcAXIS_tlast,

			crc => crc,
			validCrc => validCrc
		);

	myRxtx : Axislave_v1_0_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			fMclk => fMclk,

			wA => 32,
			wD => 32
		)
		port map(
			reset => reset,
			mclk => mclk,

			req => reqRxtx,
			ack => ackRxtx,
			dne => dneRxtx,

			sendNotRecv => txNotRx,
			len => rxtxlen,

			recvAXIS_tready => rxAXIS_tready,
			recvAXIS_tvalid => rxAXIS_tvalid,
			recvAXIS_tdata => rxAXIS_tdata,
			recvAXIS_tlast => rxAXIS_tlast,

			sendAXIS_tready => txAXIS_tready,
			sendAXIS_tvalid => txAXIS_tvalid,
			sendAXIS_tdata => txAXIS_tdata,
			sendAXIS_tlast => txAXIS_tlast,

			AXIL_araddr => AXIL_araddr,
			AXIL_arprot => AXIL_arprot,
			AXIL_arready => AXIL_arready,
			AXIL_arvalid => AXIL_arvalid,

			AXIL_rdata => AXIL_rdata,
			AXIL_rready => AXIL_rready,
			AXIL_rresp => AXIL_rresp,
			AXIL_rvalid => AXIL_rvalid,
			AXIL_rlast => AXIL_rlast,

			AXIL_awaddr => AXIL_awaddr,
			AXIL_awprot => AXIL_awprot,
			AXIL_awready => AXIL_awready,
			AXIL_awvalid => AXIL_awvalid,

			AXIL_wdata => AXIL_wdata,
			AXIL_wready => AXIL_wready,
			AXIL_wstrb => AXIL_wstrb,
			AXIL_wvalid => AXIL_wvalid,

			AXIL_bready => AXIL_bready,
			AXIL_bresp => AXIL_bresp,
			AXIL_bvalid => AXIL_bvalid
		);

	myWordto : Timeout_v1_0_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			twait => 100
		)
		port map (
			reset => reset,
			mclk => mclk,
			tkclk => tkclk,

			restart => restartWordto,
			timeout => wordto
		);

	myXferto : Timeout_v1_0_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			twait => 1000
		)
		port map (
			reset => reset,
			mclk => mclk,
			tkclk => tkclk,

			restart => restartXferto,
			timeout => xferto
		);

	------------------------------------------------------------------------
	-- implementation: main operation 
	------------------------------------------------------------------------

	commok <= commok_sig;
	reqReset <= reqReset_sig;

	txNotRx <= '1' when stateOp=stateOpRxopE
				or stateOp=stateOpTxpollA or stateOp=stateOpTxpollE or stateOp=stateOpTxpollB or stateOp=stateOpTxpollC or stateOp=stateOpTxpollD or stateOp=stateOpTxpollF
				or stateOp=stateOpTxA or stateOp=stateOpTxE or stateOp=stateOpTxB or stateOp=stateOpTxC or stateOp=stateOpTxD or stateOp=stateOpTxF
				or stateOp=stateOpTxbufA or stateOp=stateOpTxbufB or stateOp=stateOpTxbufC or stateOp=stateOpTxbufD or stateOp=stateOpTxbufE or stateOp=stateOpTxbufF
				or stateOp=stateOpRxD
				or stateOp=stateOpRxbufE or stateOp=stateOpRxbufF
				else '0';

	reqRxtx <= reqRx when txNotRx='0' else reqTx;

	ackRx <= ackRxtx when txNotRx='0' else '0';
	ackTx <= ackRxtx when txNotRx='1' else '0';

	dneRx <= dneRxtx when txNotRx='0' else '0';
	dneTx <= dneRxtx when txNotRx='1' else '0';

	rxtxlen <= rxlen when txNotRx='0' else txlen;

	-- command
	cmdvalid <= '1' when ( (tixVController=tixVTivspControllerHostif and tixVCommand=x"00")
				or (tixVController=tixVTivspControllerIdent and (tixVCommand=tixVIdentCommandGet or tixVCommand=tixVIdentCommandGetCfg))
				or (tixVController=tixVTivspControllerCamif and (tixVCommand=tixVCamifCommandConfig or tixVCommand=tixVCamifCommandConfigSynth or tixVCommand=tixVCamifCommandSetReg or tixVCommand=tixVCamifCommandGetReg or tixVCommand=tixVCamifCommandModReg or tixVCommand=tixVCamifCommandSetCorereg or tixVCommand=tixVCamifCommandGetCorereg))
				or (tixVController=tixVTivspControllerCorner and (tixVCommand=tixVCornerCommandAcquire or tixVCommand=tixVCornerCommandConfig or tixVCommand=tixVCornerCommandGetInfo or tixVCommand=tixVCornerCommandSet or tixVCommand=tixVCornerCommandUnlock))
				or (tixVController=tixVTivspControllerDdrif and tixVCommand=tixVDdrifCommandGetStats)
				or (tixVController=tixVTivspControllerDecim and (tixVCommand=tixVDecimCommandAcquire or tixVCommand=tixVDecimCommandConfig or tixVCommand=tixVDecimCommandGetInfo or tixVCommand=tixVDecimCommandSet or tixVCommand=tixVDecimCommandUnlock))
				or (tixVController=tixVTivspControllerDirector and (tixVCommand=tixVDirectorCommandConfig or tixVCommand=tixVDirectorCommandSet))
				or (tixVController=tixVTivspControllerHdreng and (tixVCommand=tixVHdrengCommandAssign or tixVCommand=tixVHdrengCommandGetInfo or tixVCommand=tixVHdrengCommandSet))
				or (tixVController=tixVTivspControllerLaser and tixVCommand=tixVLaserCommandSet)
				or (tixVController=tixVTivspControllerRotary and (tixVCommand=tixVRotaryCommandConfig or tixVCommand=tixVRotaryCommandGetInfo or tixVCommand=tixVRotaryCommandMoveto or tixVCommand=tixVRotaryCommandSet or tixVCommand=tixVRotaryCommandZero))
				or (tixVController=tixVTivspControllerStepmux and tixVCommand=tixVStepmuxCommandSet)
				or (tixVController=tixVTivspControllerTkclksrc and (tixVCommand=tixVTkclksrcCommandGetTkst or tixVCommand=tixVTkclksrcCommandSetTkst))
				or (tixVController=tixVTivspControllerTrace and (tixVCommand=tixVTraceCommandAcquire or tixVCommand=tixVTraceCommandConfig or tixVCommand=tixVTraceCommandGetInfo or tixVCommand=tixVTraceCommandUnlock))
				or (tixVController=tixVTivspControllerCputrack and (tixVCommand=tixVCputrackCommandGetInfo or tixVCommand=tixVCputrackCommandSelect or tixVCommand=tixVCputrackCommandSet))
				or (tixVController=tixVTivspControllerHshktrack and (tixVCommand=tixVHshktrackCommandClearMask or tixVCommand=tixVHshktrackCommandGetInfo or tixVCommand=tixVHshktrackCommandSelect or tixVCommand=tixVHshktrackCommandSet or tixVCommand=tixVHshktrackCommandSetMask))
				or (tixVController=tixVTivspControllerMemtrack and (tixVCommand=tixVMemtrackCommandClearMask or tixVCommand=tixVMemtrackCommandGetInfo or tixVCommand=tixVMemtrackCommandSelect or tixVCommand=tixVMemtrackCommandSet or tixVCommand=tixVMemtrackCommandSetMask))
				or (tixVController=tixVTivspControllerVidtrack and (tixVCommand=tixVVidtrackCommandGetInfo or tixVCommand=tixVVidtrackCommandSelect or tixVCommand=tixVVidtrackCommandSet))
				) else '0';

	-- tx/ret command
	lenRet <= x"0024" when (tixVController=tixVTivspControllerIdent and tixVCommand=tixVIdentCommandGet)
				else x"0008" when (tixVController=tixVTivspControllerIdent and tixVCommand=tixVIdentCommandGetCfg)
				else x"0001" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetReg)
				else x"0004" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetCorereg)
				else x"0007" when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandGetInfo)
				else x"0010" when (tixVController=tixVTivspControllerDdrif and tixVCommand=tixVDdrifCommandGetStats)
				else x"0005" when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandGetInfo)
				else x"0007" when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandGetInfo)
				else x"0003" when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandGetInfo)
				else x"0004" when (tixVController=tixVTivspControllerTkclksrc and tixVCommand=tixVTkclksrcCommandGetTkst)
				else x"0005" when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandGetInfo)
				else x"0007" when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandGetInfo)
				else x"0007" when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandGetInfo)
				else x"0007" when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandGetInfo)
				else x"0007" when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandGetInfo)
				else (others => '0');

	-- rx/inv command
	lenInv <= x"0002" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandConfig)
				else x"0004" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandConfigSynth)
				else x"0003" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandSetReg)
				else x"0002" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetReg)
				else x"0004" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandModReg)
				else x"0005" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandSetCorereg)
				else x"0001" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetCorereg)
				else x"000A" when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandConfig)
				else x"0001" when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandSet)
				else x"0001" when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandAcquire)
				else x"0006" when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandConfig)
				else x"0001" when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandSet)
				else x"0004" when (tixVController=tixVTivspControllerDirector and tixVCommand=tixVDirectorCommandConfig)
				else x"0001" when (tixVController=tixVTivspControllerDirector and tixVCommand=tixVDirectorCommandSet)
				else x"0001" when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandAssign)
				else x"0001" when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandSet)
				else x"0004" when (tixVController=tixVTivspControllerLaser and tixVCommand=tixVLaserCommandSet)
				else x"0002" when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandConfig)
				else x"0002" when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandMoveto)
				else x"0002" when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandSet)
				else x"0001" when (tixVController=tixVTivspControllerStepmux and tixVCommand=tixVStepmuxCommandSet)
				else x"0004" when (tixVController=tixVTivspControllerTkclksrc and tixVCommand=tixVTkclksrcCommandSetTkst)
				else x"0005" when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandConfig)
				else x"0005" when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandSelect)
				else x"0005" when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandSet)
				else x"0004" when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSelect)
				else x"0005" when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSet)
				else x"0001" when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSetMask)
				else x"0004" when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSelect)
				else x"0005" when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSet)
				else x"0001" when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSetMask)
				else x"0005" when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandSelect)
				else x"0005" when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandSet)
				else (others => '0');

	reqInv <= '1' when stateOp=stateOpInv else '0';

	reqInvCamifConfig <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandConfig) else '0';
	camifConfigHdrNotFix <= invbuf(0);
	camifConfigSynthNotLive <= invbuf(1);

	reqInvCamifConfigSynth <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandConfigSynth) else '0';
	camifConfigSynthTixVSynthmode <= invbuf(0);
	camifConfigSynthTFramepad <= invbuf(1) & invbuf(2);
	camifConfigSynthTLinepad <= invbuf(3);

	reqInvCamifSetReg <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandSetReg) else '0';
	camifSetRegAddr <= invbuf(0) & invbuf(1);
	camifSetRegVal <= invbuf(2);

	reqInvCamifGetReg <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetReg) else '0';
	camifGetRegAddr <= invbuf(0) & invbuf(1);

	reqInvCamifModReg <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandModReg) else '0';
	camifModRegAddr <= invbuf(0) & invbuf(1);
	camifModRegMask <= invbuf(2);
	camifModRegVal <= invbuf(3);

	reqInvCamifSetCorereg <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandSetCorereg) else '0';
	camifSetCoreregAddr <= invbuf(0);
	camifSetCoreregVal <= invbuf(1) & invbuf(2) & invbuf(3) & invbuf(4);

	reqInvCamifGetCorereg <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetCorereg) else '0';
	camifGetCoreregAddr <= invbuf(0);

	reqInvCornerAcquire <= reqInv when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandAcquire) else '0';

	reqInvCornerConfig <= reqInv when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandConfig) else '0';
	cornerConfigLinNotLog <= invbuf(0);
	cornerConfigThd <= invbuf(1);
	cornerConfigRow0 <= invbuf(2) & invbuf(3);
	cornerConfigRow1 <= invbuf(4) & invbuf(5);
	cornerConfigCol0 <= invbuf(6) & invbuf(7);
	cornerConfigCol1 <= invbuf(8) & invbuf(9);

	reqInvCornerSet <= reqInv when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandSet) else '0';
	cornerSetRng <= invbuf(0);

	reqInvCornerUnlock <= reqInv when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandUnlock) else '0';

	reqInvDecimAcquire <= reqInv when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandAcquire) else '0';
	decimAcquireIxTExp <= invbuf(0);

	reqInvDecimConfig <= reqInv when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandConfig) else '0';
	decimConfigRgbNotGray <= invbuf(0);
	decimConfigEdge <= invbuf(1);
	decimConfigEdge2 <= invbuf(2) & invbuf(3);
	decimConfigNDecim <= invbuf(4) & invbuf(5);

	reqInvDecimSet <= reqInv when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandSet) else '0';
	decimSetRng <= invbuf(0);

	reqInvDecimUnlock <= reqInv when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandUnlock) else '0';

	reqInvDirectorConfig <= reqInv when (tixVController=tixVTivspControllerDirector and tixVCommand=tixVDirectorCommandConfig) else '0';
	directorConfigNRowRaw <= invbuf(0) & invbuf(1);
	directorConfigNColRaw <= invbuf(2) & invbuf(3);

	reqInvDirectorSet <= reqInv when (tixVController=tixVTivspControllerDirector and tixVCommand=tixVDirectorCommandSet) else '0';
	directorSetRng <= invbuf(0);

	reqInvHdrengAssign <= reqInv when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandAssign) else '0';
	hdrengAssignIxMem <= invbuf(0);

	reqInvHdrengSet <= reqInv when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandSet) else '0';
	hdrengSetRng <= invbuf(0);

	reqInvLaserSet <= reqInv when (tixVController=tixVTivspControllerLaser and tixVCommand=tixVLaserCommandSet) else '0';
	laserSetL <= invbuf(0) & invbuf(1);
	laserSetR <= invbuf(2) & invbuf(3);

	reqInvRotaryConfig <= reqInv when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandConfig) else '0';
	rotaryConfigTixVStepmode <= invbuf(0);
	rotaryConfigTStep <= invbuf(1);

	reqInvRotaryMoveto <= reqInv when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandMoveto) else '0';
	rotaryMovetoAngle <= invbuf(0) & invbuf(1);

	reqInvRotarySet <= reqInv when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandSet) else '0';
	rotarySetRng <= invbuf(0);
	rotarySetCcwNotCw <= invbuf(1);

	reqInvRotaryZero <= reqInv when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandZero) else '0';

	reqInvStepmuxSet <= reqInv when (tixVController=tixVTivspControllerStepmux and tixVCommand=tixVStepmuxCommandSet) else '0';
	stepmuxSetLinNotRot <= invbuf(0);

	reqInvTkclksrcSetTkst <= reqInv when (tixVController=tixVTivspControllerTkclksrc and tixVCommand=tixVTkclksrcCommandSetTkst) else '0';
	tkclksrcSetTkstTkst <= invbuf(0) & invbuf(1) & invbuf(2) & invbuf(3);

	reqInvTraceAcquire <= reqInv when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandAcquire) else '0';

	reqInvTraceConfig <= reqInv when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandConfig) else '0';
	traceConfigTixVOrient <= invbuf(0);
	traceConfigRow0 <= invbuf(1) & invbuf(2);
	traceConfigCol0 <= invbuf(3) & invbuf(4);

	reqInvTraceUnlock <= reqInv when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandUnlock) else '0';

	reqInvCputrackSelect <= reqInv when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandSelect) else '0';
	cputrackSelectTixVCapture <= invbuf(0);
	cputrackSelectStaTixVTrigger <= invbuf(1);
	cputrackSelectStaFallingNotRising <= invbuf(2);
	cputrackSelectStoTixVTrigger <= invbuf(3);
	cputrackSelectStoFallingNotRising <= invbuf(4);

	reqInvCputrackSet <= reqInv when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandSet) else '0';
	cputrackSetRng <= invbuf(0);
	cputrackSetTCaptMax <= invbuf(1) & invbuf(2) & invbuf(3) & invbuf(4);

	reqInvHshktrackClearMask <= reqInv when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandClearMask) else '0';

	reqInvHshktrackSelect <= reqInv when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSelect) else '0';
	hshktrackSelectStaTixVTrigger <= invbuf(0);
	hshktrackSelectStaFallingNotRising <= invbuf(1);
	hshktrackSelectStoTixVTrigger <= invbuf(2);
	hshktrackSelectStoFallingNotRising <= invbuf(3);

	reqInvHshktrackSet <= reqInv when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSet) else '0';
	hshktrackSetRng <= invbuf(0);
	hshktrackSetTCaptMax <= invbuf(1) & invbuf(2) & invbuf(3) & invbuf(4);

	reqInvHshktrackSetMask <= reqInv when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSetMask) else '0';
	hshktrackSetMaskTixVCapture <= invbuf(0);

	reqInvMemtrackClearMask <= reqInv when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandClearMask) else '0';

	reqInvMemtrackSelect <= reqInv when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSelect) else '0';
	memtrackSelectStaTixVTrigger <= invbuf(0);
	memtrackSelectStaFallingNotRising <= invbuf(1);
	memtrackSelectStoTixVTrigger <= invbuf(2);
	memtrackSelectStoFallingNotRising <= invbuf(3);

	reqInvMemtrackSet <= reqInv when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSet) else '0';
	memtrackSetRng <= invbuf(0);
	memtrackSetTCaptMax <= invbuf(1) & invbuf(2) & invbuf(3) & invbuf(4);

	reqInvMemtrackSetMask <= reqInv when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSetMask) else '0';
	memtrackSetMaskTixVCapture <= invbuf(0);

	reqInvVidtrackSelect <= reqInv when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandSelect) else '0';
	vidtrackSelectTixVCapture <= invbuf(0);
	vidtrackSelectStaTixVTrigger <= invbuf(1);
	vidtrackSelectStaFallingNotRising <= invbuf(2);
	vidtrackSelectStoTixVTrigger <= invbuf(3);
	vidtrackSelectStoFallingNotRising <= invbuf(4);

	reqInvVidtrackSet <= reqInv when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandSet) else '0';
	vidtrackSetRng <= invbuf(0);
	vidtrackSetTCaptMax <= invbuf(1) & invbuf(2) & invbuf(3) & invbuf(4);

	ackInv <= ackInvCamifConfig when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandConfig)
				else ackInvCamifConfigSynth when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandConfigSynth)
				else ackInvCamifSetReg when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandSetReg)
				else ackInvCamifGetReg when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetReg)
				else ackInvCamifModReg when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandModReg)
				else ackInvCamifSetCorereg when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandSetCorereg)
				else ackInvCamifGetCorereg when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetCorereg)
				else ackInvCornerAcquire when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandAcquire)
				else ackInvCornerConfig when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandConfig)
				else ackInvCornerSet when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandSet)
				else ackInvCornerUnlock when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandUnlock)
				else ackInvDecimAcquire when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandAcquire)
				else ackInvDecimConfig when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandConfig)
				else ackInvDecimSet when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandSet)
				else ackInvDecimUnlock when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandUnlock)
				else ackInvDirectorConfig when (tixVController=tixVTivspControllerDirector and tixVCommand=tixVDirectorCommandConfig)
				else ackInvDirectorSet when (tixVController=tixVTivspControllerDirector and tixVCommand=tixVDirectorCommandSet)
				else ackInvHdrengAssign when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandAssign)
				else ackInvHdrengSet when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandSet)
				else ackInvLaserSet when (tixVController=tixVTivspControllerLaser and tixVCommand=tixVLaserCommandSet)
				else ackInvRotaryConfig when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandConfig)
				else ackInvRotaryMoveto when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandMoveto)
				else ackInvRotarySet when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandSet)
				else ackInvRotaryZero when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandZero)
				else ackInvStepmuxSet when (tixVController=tixVTivspControllerStepmux and tixVCommand=tixVStepmuxCommandSet)
				else ackInvTkclksrcSetTkst when (tixVController=tixVTivspControllerTkclksrc and tixVCommand=tixVTkclksrcCommandSetTkst)
				else ackInvTraceAcquire when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandAcquire)
				else ackInvTraceConfig when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandConfig)
				else ackInvTraceUnlock when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandUnlock)
				else ackInvCputrackSelect when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandSelect)
				else ackInvCputrackSet when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandSet)
				else ackInvHshktrackClearMask when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandClearMask)
				else ackInvHshktrackSelect when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSelect)
				else ackInvHshktrackSet when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSet)
				else ackInvHshktrackSetMask when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSetMask)
				else ackInvMemtrackClearMask when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandClearMask)
				else ackInvMemtrackSelect when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSelect)
				else ackInvMemtrackSet when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSet)
				else ackInvMemtrackSetMask when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSetMask)
				else ackInvVidtrackSelect when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandSelect)
				else ackInvVidtrackSet when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandSet)
				else '1';

	-- tx buffer
	txbufvalid <= '1' when tixVBuffer=tixVTivspBufferCoobufCornerToHostif or tixVBuffer=tixVTivspBufferFlgbufTraceToHostif or tixVBuffer=tixVTivspBufferPvwbufDecimToHostif or tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif or tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif or tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif or tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif else '0';

	reqTxbuf <= '1' when stateOp=stateOpTxbufA or stateOp=stateOpTxbufB or stateOp=stateOpTxbufC or stateOp=stateOpTxbufD or stateOp=stateOpTxbufE or stateOp=stateOpTxbufF or stateOp=stateOpTxbufG or stateOp=stateOpTxbufH else '0';

	reqCoobufFromCorner <= reqTxbuf when tixVBuffer=tixVTivspBufferCoobufCornerToHostif else '0';
	reqFlgbufFromTrace <= reqTxbuf when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif else '0';
	reqPvwbufFromDecim <= reqTxbuf when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif else '0';
	reqSeqbufFromMemtrack <= reqTxbuf when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif else '0';
	reqSeqbufFromCputrack <= reqTxbuf when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif else '0';
	reqSeqbufFromVidtrack <= reqTxbuf when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif else '0';
	reqSeqbufFromHshktrack <= reqTxbuf when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif else '0';

	ackTxbuf <= ackCoobufFromCorner when tixVBuffer=tixVTivspBufferCoobufCornerToHostif
				else ackFlgbufFromTrace when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif
				else ackPvwbufFromDecim when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif
				else ackSeqbufFromMemtrack when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif
				else ackSeqbufFromCputrack when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif
				else ackSeqbufFromVidtrack when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif
				else ackSeqbufFromHshktrack when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif
				else '0';

	dneTxbuf <= '1' when stateOp=stateOpTxbufE else '0';

	dneCoobufFromCorner <= dneTxbuf when tixVBuffer=tixVTivspBufferCoobufCornerToHostif else '0';
	dneFlgbufFromTrace <= dneTxbuf when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif else '0';
	dnePvwbufFromDecim <= dneTxbuf when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif else '0';
	dneSeqbufFromMemtrack <= dneTxbuf when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif else '0';
	dneSeqbufFromCputrack <= dneTxbuf when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif else '0';
	dneSeqbufFromVidtrack <= dneTxbuf when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif else '0';
	dneSeqbufFromHshktrack <= dneTxbuf when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif else '0';

	avllenTxbuf <= avllenCoobufFromCorner when tixVBuffer=tixVTivspBufferCoobufCornerToHostif
				else avllenFlgbufFromTrace when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif
				else avllenPvwbufFromDecim when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif
				else avllenSeqbufFromMemtrack when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif
				else avllenSeqbufFromCputrack when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif
				else avllenSeqbufFromVidtrack when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif
				else avllenSeqbufFromHshktrack when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif
				else (others => '0');

	txbufAXIS_tready <= '1' when stateOp=stateOpTxbufB else '0';

	coobufFromCornerAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferCoobufCornerToHostif else '0';
	flgbufFromTraceAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif else '0';
	pvwbufFromDecimAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif else '0';
	seqbufFromMemtrackAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif else '0';
	seqbufFromCputrackAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif else '0';
	seqbufFromVidtrackAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif else '0';
	seqbufFromHshktrackAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif else '0';

	txbufAXIS_tvalid <= coobufFromCornerAXIS_tvalid when tixVBuffer=tixVTivspBufferCoobufCornerToHostif
				else flgbufFromTraceAXIS_tvalid when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif
				else pvwbufFromDecimAXIS_tvalid when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif
				else seqbufFromMemtrackAXIS_tvalid when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif
				else seqbufFromCputrackAXIS_tvalid when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif
				else seqbufFromVidtrackAXIS_tvalid when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif
				else seqbufFromHshktrackAXIS_tvalid when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif
				else '0';

	txbufAXIS_tdata <= coobufFromCornerAXIS_tdata when tixVBuffer=tixVTivspBufferCoobufCornerToHostif
				else flgbufFromTraceAXIS_tdata when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif
				else pvwbufFromDecimAXIS_tdata when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif
				else seqbufFromMemtrackAXIS_tdata when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif
				else seqbufFromCputrackAXIS_tdata when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif
				else seqbufFromVidtrackAXIS_tdata when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif
				else seqbufFromHshktrackAXIS_tdata when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif
				else (others => '0');

	txbufAXIS_tlast <= coobufFromCornerAXIS_tlast when tixVBuffer=tixVTivspBufferCoobufCornerToHostif
				else flgbufFromTraceAXIS_tlast when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif
				else pvwbufFromDecimAXIS_tlast when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif
				else seqbufFromMemtrackAXIS_tlast when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif
				else seqbufFromCputrackAXIS_tlast when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif
				else seqbufFromVidtrackAXIS_tlast when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif
				else seqbufFromHshktrackAXIS_tlast when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif
				else '1';

	-- rx buffer
	rxbufvalid <=  '0';

	reqRxbuf <= '1' when stateOp=stateOpRxbufA or stateOp=stateOpRxbufB or stateOp=stateOpRxbufC or stateOp=stateOpRxbufD or stateOp=stateOpRxbufE or stateOp=stateOpRxbufF else '0';

	ackRxbuf <= '0';

	dneRxbuf <= '1' when stateOp=stateOpRxbufF else '0';

	avllenRxbuf <= (others => '0');

	rxbufAXIS_tvalid <= '1' when stateOp=stateOpRxbufC else '0';

	rxbufAXIS_tlast <= '1' when (stateOp=stateOpRxbufC and rxbuflast='1') else '0';

	rxbufAXIS_tready <= '0';

	crcAXIS_tvalid <= '1' when (stateOp=stateOpRxopB or stateOp=stateOpRxB or stateOp=stateOpRxbufB) and rxAXIS_tvalid='1' -- validate
				else '1' when (stateOp=stateOpTxpollC or stateOp=stateOpTxC or stateOp=stateOpTxbufC) -- calculate
				else '0';

	crcAXIS_tdata <= rxAXIS_tdata when (stateOp=stateOpRxopB or stateOp=stateOpRxB or stateOp=stateOpRxbufB)
				else txAXIS_tdata when (stateOp=stateOpTxpollC or stateOp=stateOpTxC or stateOp=stateOpTxbufC)
				else (others => '0');

	crcAXIS_tlast <= '1' when (stateOp=stateOpRxopB or stateOp=stateOpRxB or stateOp=stateOpRxbufB) and (crcAXIS_tlast_sig='0' and rxAXIS_tvalid='1' and rxAXIS_tlast='1')
				else crcAXIS_tlast_sig;

	reqRx <= '1' when stateOp=stateOpRxopB
				or stateOp=stateOpTxpollG
				or stateOp=stateOpTxG
				or stateOp=stateOpTxbufG
				or stateOp=stateOpRxB
				or stateOp=stateOpRxbufB or stateOp=stateOpRxbufC
				else '0';

	rxAXIS_tready <= '1' when stateOp=stateOpRxopB
				or stateOp=stateOpTxpollG
				or stateOp=stateOpTxG
				or stateOp=stateOpTxbufG
				or stateOp=stateOpRxB
				or stateOp=stateOpRxbufB
				else '0';

	restartWordto <= '0' when ((ackRx='1' and rxAXIS_tvalid='0' and (stateOp=stateOpRxopB or stateOp=stateOpRxB or stateOp=stateOpRxbufB))
				or (ackTx='1' and txAXIS_tready='0' and (stateOp=stateOpTxpollE or stateOp=stateOpTxE or stateOp=stateOpTxbufE)))
				else '1';

	restartXferto <= '0' when ((ackRx='0' and (stateOp=stateOpRxB or stateOp=stateOpRxbufB))
					or ((ackTx='0' and (stateOp=stateOpTxpollE or stateOp=stateOpTxE or stateOp=stateOpTxbufE)))
					or stateOp=stateOpRxopE or stateOp=stateOpTxpollG or stateOp=stateOpTxG or stateOp=stateOpTxbufG or stateOp=stateOpRxD or stateOp=stateOpRxbufE)
					else '1';

	reqTx <= '1' when stateOp=stateOpRxopE
				or stateOp=stateOpTxpollB or stateOp=stateOpTxpollC or stateOp=stateOpTxpollD or stateOp=stateOpTxpollE or stateOp=stateOpTxpollF
				or stateOp=stateOpTxE or stateOp=stateOpTxB or stateOp=stateOpTxC or stateOp=stateOpTxD or stateOp=stateOpTxF
				or stateOp=stateOpTxbufB or stateOp=stateOpTxbufC or stateOp=stateOpTxbufD or stateOp=stateOpTxbufE or stateOp=stateOpTxbufF
				or stateOp=stateOpRxD
				or stateOp=stateOpRxbufE
				else '0';

	txAXIS_tvalid <= '1' when stateOp=stateOpRxopE
				or stateOp=stateOpTxpollE
				or stateOp=stateOpTxE
				or stateOp=stateOpTxbufE
				or stateOp=stateOpRxD
				or stateOp=stateOpRxbufE
				else '0';
	
	txAXIS_tlast <= '1' when stateOp=stateOpRxopE
				or (stateOp=stateOpTxpollE and txlast='1')
				or (stateOp=stateOpTxE and txlast='1')
				or (stateOp=stateOpTxbufE and txlast='1')
				or stateOp=stateOpRxD
				or stateOp=stateOpRxbufE
				else '0';

	-- IP cust --- RBEGIN
	 stateOp_dbg <= x"00" when stateOp=stateOpInit
	 			else x"10" when stateOp=stateOpIdle
	 			else x"20" when stateOp=stateOpRxopA
	 			else x"21" when stateOp=stateOpRxopB
	 			else x"22" when stateOp=stateOpRxopC
	 			else x"23" when stateOp=stateOpRxopD
	 			else x"24" when stateOp=stateOpRxopE
	 			else x"30" when stateOp=stateOpTxpollA
	 			else x"31" when stateOp=stateOpTxpollB
	 			else x"32" when stateOp=stateOpTxpollC
	 			else x"33" when stateOp=stateOpTxpollD
	 			else x"34" when stateOp=stateOpTxpollE
	 			else x"35" when stateOp=stateOpTxpollF
	 			else x"36" when stateOp=stateOpTxpollG
	 			else x"40" when stateOp=stateOpTxA
	 			else x"41" when stateOp=stateOpTxB
	 			else x"42" when stateOp=stateOpTxC
	 			else x"43" when stateOp=stateOpTxD
	 			else x"44" when stateOp=stateOpTxE
	 			else x"45" when stateOp=stateOpTxF
	 			else x"46" when stateOp=stateOpTxG
	 			else x"50" when stateOp=stateOpTxbufA
	 			else x"51" when stateOp=stateOpTxbufB
	 			else x"52" when stateOp=stateOpTxbufC
	 			else x"53" when stateOp=stateOpTxbufD
	 			else x"54" when stateOp=stateOpTxbufE
	 			else x"55" when stateOp=stateOpTxbufF
	 			else x"56" when stateOp=stateOpTxbufG
	 			else x"57" when stateOp=stateOpTxbufH
	 			else x"60" when stateOp=stateOpRxA
	 			else x"61" when stateOp=stateOpRxB
	 			else x"62" when stateOp=stateOpRxC
	 			else x"63" when stateOp=stateOpRxD
	 			else x"70" when stateOp=stateOpRxbufA
	 			else x"71" when stateOp=stateOpRxbufB
	 			else x"72" when stateOp=stateOpRxbufC
	 			else x"73" when stateOp=stateOpRxbufD
	 			else x"74" when stateOp=stateOpRxbufE
	 			else x"75" when stateOp=stateOpRxbufF
	 			else x"80" when stateOp=stateOpInv
	 			else (others => '1');
	-- IP cust --- REND

	process (reset, mclk, stateOp)
		variable len: std_logic_vector(31 downto 0);

		variable full_vec: unsigned(31 downto 0);
		variable quot: natural;

		variable resid: natural range 0 to wD/8-1;
		variable residCrc: natural range 0 to wD/8-1;

		variable lastAXIS_tkeep: std_logic_vector(wD/8-1 downto 0);

		variable txAXIS_tdata_lcl: std_logic_vector(wD-1 downto 0);

		variable stateOp_next: stateOp_t;

		variable wordcnt: natural;
		variable wordcntLast: natural;
		variable wordcntCrcLast: natural range 0 to 16777216;

		variable ixRetbufCrc: natural range 0 to sizeRetbuf-2;

	begin
		if reset='1' then
			stateOp <= stateOpInit;
			opbuf <= (others => (others => '0'));
			tixVBuffer <= (others => '0');
			tixVController <= (others => '0');
			tixVCommand <= (others => '0');
			tixVBufxfop <= (others => '0');
			pollbuf <= (others => (others => '0'));
			invbuf <= (others => (others => '0'));
			retbuf <= (others => (others => '0'));
			commok_sig <= '1';
			reqReset_sig <= '0';
			rxbuflast <= '0';
			crcAXIS_tlast_sig <= '1';
			crcAXIS_tkeep <= (others => '1');
			rxlen <= (others => '0');
			txlen <= (others => '0');
			txAXIS_tdata <= (others => '0');
			txlast <= '0';

			len := (others => '0');
			full_vec := (others => '0');
			quot := 0;
			resid := 0;
			residCrc := 0;
			lastAXIS_tkeep := (others => '1');
			txAXIS_tdata_lcl := (others => '0');
			stateOp_next := stateOpInit;
			wordcnt := 0;
			wordcntLast := 0;
			wordcntCrcLast := 0;
			ixRetbufCrc := 0;

		elsif rising_edge(mclk) then
			if stateOp=stateOpInit or wordto='1' or xferto='1' then
				opbuf <= (others => (others => '0'));
				tixVBuffer <= (others => '0');
				tixVController <= (others => '0');
				tixVCommand <= (others => '0');
				tixVBufxfop <= (others => '0');
				pollbuf <= (others => (others => '0'));
				invbuf <= (others => (others => '0'));
				retbuf <= (others => (others => '0'));
				reqReset_sig <= '0';
				rxbuflast <= '0';
				crcAXIS_tlast_sig <= '1';
				crcAXIS_tkeep <= (others => '1');
				rxlen <= (others => '0');
				txlen <= (others => '0');
				txAXIS_tdata <= (others => '0');
				txlast <= '0';

				len := (others => '0');
				full_vec := (others => '0');
				quot := 0;
				resid := 0;
				residCrc := 0;
				lastAXIS_tkeep := (others => '1');
				txAXIS_tdata_lcl := (others => '0');
				stateOp_next := stateOpInit;
				wordcnt := 0;
				wordcntLast := 0;
				wordcntCrcLast := 0;
				ixRetbufCrc := 0;

				if wordto='1' or xferto='1' then
					commok_sig <= '0';

					stateOp <= stateOpInit;

				else
					stateOp <= stateOpIdle;
				end if;

			elsif stateOp=stateOpIdle then
				crcAXIS_tlast_sig <= '0';

				stateOp <= stateOpRxopA;

-- RX OP BEGIN
			elsif stateOp=stateOpRxopA then
				if wD=128 then
					rxlen <= (others => '0');

					crcAXIS_tlast_sig <= '1';
					crcAXIS_tkeep <= opbufLastAXIS_tkeep;
	
					wordcntLast := 0;

				else
					rxlen <= std_logic_vector(to_unsigned(sizeOpbuf/(wD/8)-1, 32));
					wordcntLast := sizeOpbuf/(wD/8) - 1;
				end if;

				wordcnt := 0;

				stateOp <= stateOpRxopB;

			elsif stateOp=stateOpRxopB then -- reqRx='1', rxAXIS_tready='1'
				if rxAXIS_tvalid='1' then
					commok_sig <= '1';

					for i in 0 to wD/8-1 loop
						opbuf(wordcnt*wD/8+i) <= rxAXIS_tdata(8*(i+1)-1 downto 8*i);
					end loop;

					if wordcnt=wordcntLast then
						crcAXIS_tlast_sig <= '1';

						stateOp <= stateOpRxopC;

					else
						if wordcnt=wordcntLast-1 then
							crcAXIS_tkeep <= opbufLastAXIS_tkeep;
						end if;
						
						wordcnt := wordcnt + 1;
					end if;
				end if;

			elsif stateOp=stateOpRxopC then
				crcAXIS_tkeep <= (others => '1');

				if crc=x"0000" then
					tixVBuffer <= opbuf(ixOpbufBuffer);
					if opbuf(ixOpbufBuffer)/=tixVTivspBufferCmdretToHostif or opbuf(ixOpbufBufxfBufxfop)/=tixVBufxfopPoll then
						tixVController <= opbuf(ixOpbufController);
						tixVCommand <= opbuf(ixOpbufCmdCommand);
					end if;
					tixVBufxfop <= opbuf(ixOpbufBufxfBufxfop);

					len := opbuf(ixOpbufLen) & opbuf(ixOpbufLen+1) & opbuf(ixOpbufLen+2) & opbuf(ixOpbufLen+3);

					stateOp <= stateOpRxopD;
				
				else
					commok_sig <= '0';

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpRxopD then
				stateOp_next := stateOpInit;

				if tixVBuffer=tixVTivspBufferCmdretToHostif and tixVBufxfop=tixVBufxfopPoll and len(7 downto 0)=x"04" then
					stateOp_next := stateOpTxpollA;

				elsif tixVBuffer=tixVTivspBufferHostifToCmdinv and cmdvalid='1' and len(15 downto 0)=lenInv then
					if unsigned(lenInv)=0 then
						stateOp_next := stateOpInv;
					else
						stateOp_next := stateOpRxA;
					end if;

				elsif (txbufvalid='1' or rxbufvalid='1') and tixVBufxfop=tixVBufxfopPoll then
					stateOp_next := stateOpTxpollA;

				elsif txbufvalid='1' and tixVBufxfop=tixVBufxfopXfer and len=avllenTxbuf and unsigned(len)/=0 then
					if wD=8 or (wD=16 and len(0)='0') or (wD=32 and len(1 downto 0)="00") or (wD=64 and len(2 downto 0)="000") or (wD=128 and len(3 downto 0)="0000") then
						stateOp_next := stateOpTxbufA;
					end if;

				elsif rxbufvalid='1' and tixVBufxfop=tixVBufxfopXfer and unsigned(len)<=unsigned(avllenRxbuf) and unsigned(len)/=0 then
					if wD=8 or (wD=16 and len(0)='0') or (wD=32 and len(1 downto 0)="00") or (wD=64 and len(2 downto 0)="000") or (wD=128 and len(3 downto 0)="0000") then
						stateOp_next := stateOpRxbufA;
					end if;
				end if;

				txlen <= (others => '0');
				txlast <= '1';

				if stateOp_next=stateOpInit then
					txAXIS_tdata(7 downto 0) <= fls8;
				else
					txAXIS_tdata(7 downto 0) <= tru8;
				end if;

				stateOp <= stateOpRxopE;

			elsif stateOp=stateOpRxopE then -- reqTx='1', txAXIS_tvalid='1', txAXIS_tlast='1'
				if dneTx='1' then
					if stateOp_next/=stateOpInit then
						crcAXIS_tlast_sig <= '0';
					end if;

					stateOp <= stateOp_next;
				end if;

-- RX OP END, TX POLL BEGIN
			elsif stateOp=stateOpTxpollA then
				if tixVBuffer=tixVTivspBufferCmdretToHostif then
					pollbuf(ixPollbufCmdController) <= tixVController;
					pollbuf(ixPollbufCmdCommand) <= tixVCommand;
					pollbuf(ixPollbufCmdLen) <= lenRet(15 downto 8);
					pollbuf(ixPollbufCmdLen+1) <= lenRet(7 downto 0);
				elsif txbufvalid='1' then
					pollbuf(ixPollbufBufxfAvllen) <= avllenTxbuf(31 downto 24);
					pollbuf(ixPollbufBufxfAvllen+1) <= avllenTxbuf(23 downto 16);
					pollbuf(ixPollbufBufxfAvllen+2) <= avllenTxbuf(15 downto 8);
					pollbuf(ixPollbufBufxfAvllen+3) <= avllenTxbuf(7 downto 0);
				elsif rxbufvalid='1' then
					pollbuf(ixPollbufBufxfAvllen) <= avllenRxbuf(31 downto 24);
					pollbuf(ixPollbufBufxfAvllen+1) <= avllenRxbuf(23 downto 16);
					pollbuf(ixPollbufBufxfAvllen+2) <= avllenRxbuf(15 downto 8);
					pollbuf(ixPollbufBufxfAvllen+3) <= avllenRxbuf(7 downto 0);
				end if;

				if wD=64 or wD=128 then
					txlen <= (others => '0');
					txlast <= '1';

					wordcntLast := 0;

				else
					txlen <= std_logic_vector(to_unsigned(sizePollbuf/(wD/8)-1, 32));
					txlast <= '0';

					wordcntLast := sizePollbuf/(wD/8)-1;
				end if;

				wordcnt := 0;

				stateOp <= stateOpTxpollB;

			elsif stateOp=stateOpTxpollB then -- load into txAXIS_tdata
				for i in 0 to wD/8-1 loop
					txAXIS_tdata(8*(i+1)-1 downto 8*i) <= pollbuf(wordcnt*wD/8+i);
				end loop;

				if (wD=64 or wD=128) or ((wD=8 or wD=16 or wD=32) and wordcnt=ixPollbufCrc/(wD/8)-1) then
					crcAXIS_tlast_sig <= '1';
					crcAXIS_tkeep <= pollbufLastAXIS_tkeep;
				end if;

				stateOp <= stateOpTxpollC;

			elsif stateOp=stateOpTxpollC then -- calc CRC on txAXIS_tdata
				if crcAXIS_tlast_sig='1' then
					stateOp <= stateOpTxpollD;
				else
					stateOp <= stateOpTxpollE;
				end if;

			elsif stateOp=stateOpTxpollD then -- update pollbuf or txAXIS_tdata
				if wD=64 or wD=128 then
					txAXIS_tdata(5*8-1 downto 4*8) <= crc(15 downto 8);
					txAXIS_tdata(6*8-1 downto 5*8) <= crc(7 downto 0);

				else
					pollbuf(ixPollbufCrc) <= crc(15 downto 8);
					pollbuf(ixPollbufCrc + 1) <= crc(7 downto 0);
				end if;

				stateOp <= stateOpTxpollE;

			elsif stateOp=stateOpTxpollE then
				if txAXIS_tready='1' then
					if wordcnt=wordcntLast then
						crcAXIS_tkeep <= (others => '1');

						stateOp <= stateOpTxpollF;
					
					else
						wordcnt := wordcnt + 1;

						if wordcnt=wordcntLast then
							txlast <= '1';
						end if;

						stateOp <= stateOpTxpollB;
					end if;
				end if;

			elsif stateOp=stateOpTxpollF then
				if dneTx='1' then
					rxlen <= (others => '0');

					stateOp <= stateOpTxpollG;
				end if;

			elsif stateOp=stateOpTxpollG then -- reqRx='1', rxAXIS_tready'1'
				if rxAXIS_tvalid='1' then
					if rxAXIS_tdata(7 downto 0)/=tru8 then
						stateOp <= stateOpInit;

					else
						if tixVBuffer=tixVTivspBufferCmdretToHostif then
							crcAXIS_tlast_sig <= '0';

							stateOp <= stateOpTxA;

						else
							stateOp <= stateOpInit;
						end if;
					end if;
				end if;

-- TX POLL END, TX BEGIN
			elsif stateOp=stateOpTxA then
				ixRetbufCrc := to_integer(unsigned(lenRet));

				full_vec := resize(unsigned(lenRet), 32) + 1; -- +2 (for CRC) -1

				if wD=8 then
					resid := 1;

					txlen <= std_logic_vector(full_vec);
					wordcntLast := to_integer(full_vec);

					wordcntCrcLast := to_integer(unsigned(lenRet) - 1);
					lastAXIS_tkeep := (others => '1');

				else
					if wD=16 then
						quot := to_integer(full_vec(31 downto 1));
						resid := to_integer(unsigned(full_vec(0 downto 0)));
					elsif wD=32 then
						quot := to_integer(full_vec(31 downto 2));
						resid := to_integer(unsigned(full_vec(1 downto 0)));
					elsif wD=64 then
						quot := to_integer(full_vec(31 downto 3));
						resid := to_integer(unsigned(full_vec(2 downto 0)));
					elsif wD=128 then
						quot := to_integer(full_vec(31 downto 4));
						resid := to_integer(unsigned(full_vec(3 downto 0)));
					end if;

					txlen <= std_logic_vector(to_unsigned(quot, 32));
					wordcntLast := quot;

					if resid=0 then
						wordcntCrcLast := quot - 1;
						residCrc := wD/8 - 2;
					elsif resid=1 then
						wordcntCrcLast := quot - 1;
						residCrc := wD/8 - 1;
					else
						wordcntCrcLast := quot;
						residCrc := resid - 2;
					end if;

					for i in 0 to wD/8-1 loop
						if residCrc>=i then
							lastAXIS_tkeep(i) := '1';
						else
							lastAXIS_tkeep(i) := '0';
						end if;
					end loop;
				end if;

				if wordcntLast=0 then
					txlast <= '1';
				else
					txlast <= '0';
				end if;

				wordcnt := 0;
				
				stateOp <= stateOpTxB;

			elsif stateOp=stateOpTxB then -- load into txAXIS_tdata
				for i in 0 to wD/8-1 loop
					txAXIS_tdata(8*(i+1)-1 downto 8*i) <= retbuf(wordcnt*wD/8+i);
				end loop;

				if wordcnt=wordcntCrcLast then
					crcAXIS_tlast_sig <= '1';
					crcAXIS_tkeep <= lastAXIS_tkeep;
				end if;

				stateOp <= stateOpTxC;

			elsif stateOp=stateOpTxC then
				if crcAXIS_tlast_sig='1' then
					stateOp <= stateOpTxD;
				
				else
					stateOp <= stateOpTxE;
				end if;

			elsif stateOp=stateOpTxD then
				if resid=0 then
					txAXIS_tdata(wD-1 downto wD-8) <= crc(15 downto 8);
					retbuf(ixRetbufCrc + 1) <= crc(7 downto 0);

				elsif resid=1 then
					retbuf(ixRetbufCrc) <= crc(15 downto 8);
					retbuf(ixRetbufCrc + 1) <= crc(7 downto 0);

				else
					-- ex. wD = 32, resid = 2, i.e. -CCX => crc(15..8) into 15..8; crc(7..0) into 23..16
					txAXIS_tdata(resid*8-1 downto (resid-1)*8) <= crc(15 downto 8);
					txAXIS_tdata((resid+1)*8-1 downto resid*8) <= crc(7 downto 0);
				end if;

				stateOp <= stateOpTxE;

			elsif stateOp=stateOpTxE then
				if txAXIS_tready='1' then
					if wordcnt=wordcntLast then
						crcAXIS_tkeep <= (others => '1');
						txlast <= '0';

						stateOp <= stateOpTxF;
					
					else
						wordcnt := wordcnt + 1;

						if wordcnt=wordcntLast then
							txlast <= '1';
						end if;

						stateOp <= stateOpTxB;
					end if;
				end if;

			elsif stateOp=stateOpTxF then
				if dneTx='1' then
					rxlen <= (others => '0');

					stateOp <= stateOpTxG;
				end if;

			elsif stateOp=stateOpTxG then -- reqRx='1', rxAXIS_tready'1'
				if rxAXIS_tvalid='1' then
					if rxAXIS_tdata(7 downto 0)/=tru8 then
						stateOp <= stateOpIdle; -- offer chance to re-retrieve the return of a command
					else
						stateOp <= stateOpInit;
					end if;
				end if;

-- TX END, TX BUF BEGIN
			elsif stateOp=stateOpTxbufA then -- reqTxbuf='1'
				if ackTxbuf='1' then
					full_vec := resize(unsigned(len), 32) + 1; -- +2 (for CRC) -1

					if wD=8 then
						txlen <= std_logic_vector(full_vec);
						wordcntLast := to_integer(full_vec);
						wordcntCrcLast := to_integer(unsigned(len) - 1);
					elsif wD=16 then
						txlen <= "0" & std_logic_vector(full_vec(31 downto 1));
						wordcntLast := to_integer(full_vec(31 downto 1));
						wordcntCrcLast := to_integer(full_vec(31 downto 1) - 1);
					elsif wD=32 then
						txlen <= "00" & std_logic_vector(full_vec(31 downto 2));
						wordcntLast := to_integer(full_vec(31 downto 2));
						wordcntCrcLast := to_integer(full_vec(31 downto 2) - 1);
					elsif wD=64 then
						txlen <= "000" & std_logic_vector(full_vec(31 downto 3));
						wordcntLast := to_integer(full_vec(31 downto 3));
						wordcntCrcLast := to_integer(full_vec(31 downto 3) - 1);
					elsif wD=128 then
						txlen <= "0000" & std_logic_vector(full_vec(31 downto 4));
						wordcntLast := to_integer(full_vec(31 downto 4));
						wordcntCrcLast := to_integer(full_vec(31 downto 4) - 1);
					end if;

					txlast <= '0';

					wordcnt := 0;

					stateOp <= stateOpTxbufB;
				end if;

			elsif stateOp=stateOpTxbufB then -- load into txAXIS_tdata
				if txbufAXIS_tvalid='1' then
					txAXIS_tdata <= txbufAXIS_tdata;

					if wordcnt=wordcntCrcLast then
						crcAXIS_tlast_sig <= '1';
					end if;

					stateOp <= stateOpTxbufC;
				end if;

			elsif stateOp=stateOpTxbufC then -- calc CRC on txAXIS_tdata
				stateOp <= stateOpTxbufE;

			elsif stateOp=stateOpTxbufD then
				if wD=8 and wordcnt=wordcntLast-1 then
					txAXIS_tdata <= crc(15 downto 8);
				elsif wD=8 and wordcnt=wordcntLast then
					txAXIS_tdata <= crc(7 downto 0);
				else
					txAXIS_tdata(7 downto 0) <= crc(15 downto 8);
					txAXIS_tdata(15 downto 8) <= crc(7 downto 0);
				end if;

				stateOp <= stateOpTxbufE;

			elsif stateOp=stateOpTxbufE then
				if txAXIS_tready='1' then
					if wordcnt=wordcntLast then
						txlast <= '0';

						stateOp <= stateOpTxbufF;
					
					else
						wordcnt := wordcnt + 1;

						if wordcnt=wordcntLast then
							txlast <= '1';
						end if;

						if wordcnt>wordcntCrcLast then
							stateOp <= stateOpTxbufD;
						else
							stateOp <= stateOpTxbufB;
						end if;
					end if;
				end if;

			elsif stateOp=stateOpTxbufF then
				if dneTx='1' then
					rxlen <= (others => '0');

					stateOp <= stateOpTxbufG;
				end if;

			elsif stateOp=stateOpTxbufG then -- reqRx='1', rxAXIS_tready'1'
				if rxAXIS_tvalid='1' then
					if rxAXIS_tdata(7 downto 0)/=tru8 then
						stateOp <= stateOpInit;
					else
						stateOp <= stateOpTxbufH;
					end if;
				end if;

			elsif stateOp=stateOpTxbufH then -- dneTxbuf='1'
				if ackTxbuf='0' then
					stateOp <= stateOpInit;
				end if;

-- TX BUF END, RX BEGIN
			elsif stateOp=stateOpRxA then
				full_vec := resize(unsigned(lenInv), 32) + 1; -- +2 (for CRC) -1
				if wD=8 then
					rxlen <= std_logic_vector(full_vec);
					wordcntLast := to_integer(full_vec);

				else
					if wD=16 then
						quot := to_integer(full_vec(31 downto 1));
						resid := to_integer(unsigned(full_vec(0 downto 0)));
					elsif wD=32 then
						quot := to_integer(full_vec(31 downto 2));
						resid := to_integer(unsigned(full_vec(1 downto 0)));
					elsif wD=64 then
						quot := to_integer(full_vec(31 downto 3));
						resid := to_integer(unsigned(full_vec(2 downto 0)));
					elsif wD=128 then
						quot := to_integer(full_vec(31 downto 4));
						resid := to_integer(unsigned(full_vec(3 downto 0)));
					end if;

					rxlen <= std_logic_vector(to_unsigned(quot, 32));

					for i in 0 to wD/8-1 loop
						if resid>=i then
							lastAXIS_tkeep(i) := '1';
						else
							lastAXIS_tkeep(i) := '0';
						end if;
					end loop;

					wordcntLast := quot;

					if wordcntLast=0 then
						crcAXIS_tlast_sig <= '1';
						crcAXIS_tkeep <= lastAXIS_tkeep;
					end if;
				end if;

				wordcnt := 0;

				stateOp <= stateOpRxB;

			elsif stateOp=stateOpRxB then -- reqRx='1', rxAXIS_tready='1'
				if rxAXIS_tvalid='1' then
					for i in 0 to wD/8-1 loop
						invbuf(wordcnt*wD/8+i) <= rxAXIS_tdata(8*(i+1)-1 downto 8*i);
					end loop;

					if wordcnt=wordcntLast then
						crcAXIS_tlast_sig <= '1';

						stateOp <= stateOpRxC;

					else
						if wordcnt=wordcntLast-1 then
							crcAXIS_tkeep <= lastAXIS_tkeep;
						end if;

						wordcnt := wordcnt + 1;
					end if;
				end if;

			elsif stateOp=stateOpRxC then
				crcAXIS_tkeep <= (others => '1');

				if crc=x"0000" then
					txlen <= (others => '0');
					txlast <= '1';

					txAXIS_tdata(7 downto 0) <= tru8;

					stateOp <= stateOpRxD;
				
				else
					commok_sig <= '0';

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpRxD then -- reqTx='1', txAXIS_tvalid='1', txAXIS_tlast='1'
				if dneTx='1' then
					stateOp <= stateOpInv;
				end if;

-- RX END, RX BUF BEGIN
			elsif stateOp=stateOpRxbufA then -- reqRxbuf='1'
				if ackRxbuf='1' then
					full_vec := resize(unsigned(len), 32) + 1; -- +2 (for CRC) -1
					if wD=8 then
						rxlen <= std_logic_vector(full_vec);
						wordcntLast := to_integer(full_vec);

					else
						if wD=16 then
							quot := to_integer(full_vec(31 downto 1));
							resid := to_integer(unsigned(full_vec(0 downto 0)));
						elsif wD=32 then
							quot := to_integer(full_vec(31 downto 2));
							resid := to_integer(unsigned(full_vec(1 downto 0)));
						elsif wD=64 then
							quot := to_integer(full_vec(31 downto 3));
							resid := to_integer(unsigned(full_vec(2 downto 0)));
						elsif wD=128 then
							quot := to_integer(full_vec(31 downto 4));
							resid := to_integer(unsigned(full_vec(3 downto 0)));
						end if;

						rxlen <= std_logic_vector(to_unsigned(quot, 32));

						for i in 0 to wD/8-1 loop
							if resid>=i then
								lastAXIS_tkeep(i) := '1';
							else
								lastAXIS_tkeep(i) := '0';
							end if;
						end loop;

						wordcntLast := quot;
					end if;

					wordcnt := 0;

					stateOp <= stateOpRxbufB;
				end if;

			elsif stateOp=stateOpRxbufB then -- reqRx='1', rxAXIS_tready='1'
				if rxAXIS_tvalid='1' then
					rxbufAXIS_tdata <= rxAXIS_tdata;

					if wordcnt=wordcntLast-2 and wD=8 then
						rxbuflast <= '1';

						wordcnt := wordcnt + 1;

						stateOp <= stateOpRxbufC;

					elsif wordcnt=wordcntLast-1 then
						rxbuflast <= '1';

						crcAXIS_tkeep <= lastAXIS_tkeep;

						wordcnt := wordcnt + 1;

						if wD=8 then
							stateOp <= stateOpRxbufB;
						else
							stateOp <= stateOpRxbufC;
						end if;

					elsif wordcnt=wordcntLast then
						crcAXIS_tlast_sig <= '1';

						stateOp <= stateOpRxbufD;

					else
						wordcnt := wordcnt + 1;

						stateOp <= stateOpRxbufC;
					end if;
				end if;

			elsif stateOp=stateOpRxbufC then -- rxbufAXIS_tvalid='1'
				if rxbufAXIS_tready='1' then
					stateOp <= stateOpRxbufB;
				end if;

			elsif stateOp=stateOpRxbufD then
				crcAXIS_tkeep <= (others => '1');

				if crc=x"0000" then
					txlen <= (others => '0');
					txlast <= '1';

					txAXIS_tdata(7 downto 0) <= tru8;

					stateOp <= stateOpRxbufE;
				
				else
					commok_sig <= '0';

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpRxbufE then -- reqTx='1', txAXIS_tvalid='1', txAXIS_tlast='1'
				if dneTx='1' then
					stateOp <= stateOpRxbufF;
				end if;

			elsif stateOp=stateOpRxbufF then -- reqRxbuf='1', dneRxbuf='1'
				if ackRxbuf='0' then
					stateOp <= stateOpInit;
				end if;
-- RX BUF END

			elsif stateOp=stateOpInv then -- reqInv='1
				if tixVController=tixVTivspControllerHostif and tixVCommand=x"00" then
					reqReset_sig <= '1';

				elsif ackInv='1' then
					if tixVController=tixVTivspControllerIdent then
						if tixVCommand=tixVIdentCommandGet then
							for i in 0 to 11 loop
								retbuf(11-i) <= identGetUnt((12-i)*8-1 downto (11-i)*8);
							end loop;
							for i in 0 to 7 loop
								retbuf(12+7-i) <= identGetVer((8-i)*8-1 downto (7-i)*8);
							end loop;
							for i in 0 to 7 loop
								retbuf(20+7-i) <= identGetHash((8-i)*8-1 downto (7-i)*8);
							end loop;
							for i in 0 to 7 loop
								retbuf(28+7-i) <= identGetWho((8-i)*8-1 downto (7-i)*8);
							end loop;
						elsif tixVCommand=tixVIdentCommandGetCfg then
							for i in 0 to 3 loop
								retbuf(i) <= identGetCfgFMclk((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 3 loop
								retbuf(4+i) <= identGetCfgFMemclk((4-i)*8-1 downto (3-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerCamif then
						if tixVCommand=tixVCamifCommandGetReg then
							retbuf(0) <= camifGetRegVal;
						elsif tixVCommand=tixVCamifCommandGetCorereg then
							for i in 0 to 3 loop
								retbuf(i) <= camifGetCoreregVal((4-i)*8-1 downto (3-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerCorner then
						if tixVCommand=tixVCornerCommandGetInfo then
							retbuf(0) <= cornerGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= cornerGetInfoTkst((4-i)*8-1 downto (3-i)*8);
							end loop;
							retbuf(5) <= cornerGetInfoScoreMin;
							retbuf(6) <= cornerGetInfoScoreMax;
						end if;

					elsif tixVController=tixVTivspControllerDdrif then
						if tixVCommand=tixVDdrifCommandGetStats then
							for i in 0 to 3 loop
								retbuf(i) <= ddrifGetStatsNRdA((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 3 loop
								retbuf(4+i) <= ddrifGetStatsNRdB((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 3 loop
								retbuf(8+i) <= ddrifGetStatsNWrA((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 3 loop
								retbuf(12+i) <= ddrifGetStatsNWrB((4-i)*8-1 downto (3-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerDecim then
						if tixVCommand=tixVDecimCommandGetInfo then
							retbuf(0) <= decimGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= decimGetInfoTkst((4-i)*8-1 downto (3-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerHdreng then
						if tixVCommand=tixVHdrengCommandGetInfo then
							retbuf(0) <= hdrengGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= hdrengGetInfoTkst((4-i)*8-1 downto (3-i)*8);
							end loop;
							retbuf(5) <= hdrengGetInfoIxMem;
							retbuf(6) <= hdrengGetInfoIxMemAcq;
						end if;

					elsif tixVController=tixVTivspControllerRotary then
						if tixVCommand=tixVRotaryCommandGetInfo then
							retbuf(0) <= rotaryGetInfoTixVState;
							for i in 0 to 1 loop
								retbuf(1+i) <= rotaryGetInfoAngle((2-i)*8-1 downto (1-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerTkclksrc then
						if tixVCommand=tixVTkclksrcCommandGetTkst then
							for i in 0 to 3 loop
								retbuf(i) <= tkclksrcGetTkstTkst((4-i)*8-1 downto (3-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerTrace then
						if tixVCommand=tixVTraceCommandGetInfo then
							retbuf(0) <= traceGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= traceGetInfoTkst((4-i)*8-1 downto (3-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerCputrack then
						if tixVCommand=tixVCputrackCommandGetInfo then
							retbuf(0) <= cputrackGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= cputrackGetInfoTCapt((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 1 loop
								retbuf(5+i) <= cputrackGetInfoPtr0Seqbuf((2-i)*8-1 downto (1-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerHshktrack then
						if tixVCommand=tixVHshktrackCommandGetInfo then
							retbuf(0) <= hshktrackGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= hshktrackGetInfoTCapt((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 1 loop
								retbuf(5+i) <= hshktrackGetInfoPtr0Seqbuf((2-i)*8-1 downto (1-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerMemtrack then
						if tixVCommand=tixVMemtrackCommandGetInfo then
							retbuf(0) <= memtrackGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= memtrackGetInfoTCapt((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 1 loop
								retbuf(5+i) <= memtrackGetInfoPtr0Seqbuf((2-i)*8-1 downto (1-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerVidtrack then
						if tixVCommand=tixVVidtrackCommandGetInfo then
							retbuf(0) <= vidtrackGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= vidtrackGetInfoTCapt((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 1 loop
								retbuf(5+i) <= vidtrackGetInfoPtr0Seqbuf((2-i)*8-1 downto (1-i)*8);
							end loop;
						end if;

					end if;

					stateOp <= stateOpIdle; -- not init, so cmdretToHostif (maintaining tixVController/tixVCommand) can be run
				end if;
			end if;
		end if;
	end process;

end Rtl;


-- file Hshktrack_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Hshktrack_8c100ea18901433eb4f7c0fdbf115e06 gptrack_Easy_v1_0 easy model debug controller implementation
-- copyright: (C) 2023 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 28 Jun 2025
-- IP header --- ABOVE

-- module parameters:
-- trkclk (clock): mclk
-- ratioTrkclk (track clock ratio wrt. master clock): 1
-- capts (signals to be captured): vsync;cornerGetInfoTixVState[1..0];reqInvRotarySet;rotaryToStepmuxStep
-- trigs (triggers): trigA;trigB;trigC;trigD
-- sizeSeqbuf (sequence buffer size [kB]): 4

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Hshktrack_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		trigA: in std_logic;
		trigB: in std_logic;
		trigC: in std_logic;
		trigD: in std_logic;

		reqInvClearMask: in std_logic;
		ackInvClearMask: out std_logic;

		getInfoTixVState: out std_logic_vector(7 downto 0);
		getInfoTCapt: out std_logic_vector(31 downto 0);
		getInfoPtr0Seqbuf: out std_logic_vector(15 downto 0);

		reqInvSelect: in std_logic;
		ackInvSelect: out std_logic;

		selectStaTixVTrigger: in std_logic_vector(7 downto 0);
		selectStaFallingNotRising: in std_logic_vector(7 downto 0);
		selectStoTixVTrigger: in std_logic_vector(7 downto 0);
		selectStoFallingNotRising: in std_logic_vector(7 downto 0);

		reqInvSet: in std_logic;
		ackInvSet: out std_logic;

		setRng: in std_logic_vector(7 downto 0);
		setTCaptMax: in std_logic_vector(31 downto 0);

		reqInvSetMask: in std_logic;
		ackInvSetMask: out std_logic;

		setMaskTixVCapture: in std_logic_vector(7 downto 0);

		reqSeqbufToHostif: in std_logic;
		ackSeqbufToHostif: out std_logic;
		dneSeqbufToHostif: in std_logic;
		avllenSeqbufToHostif: out std_logic_vector(31 downto 0);

		seqbufToHostifAXIS_tready: in std_logic;
		seqbufToHostifAXIS_tvalid: out std_logic;
		seqbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
		seqbufToHostifAXIS_tlast: out std_logic;

		vsync: in std_logic;
		cornerGetInfoTixVState: in std_logic_vector(1 downto 0);
		reqInvRotarySet: in std_logic;
		rotaryToStepmuxStep: in std_logic
	);
end Hshktrack_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Hshktrack_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_size4kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(9 downto 0);
			drdA: out std_logic_vector(31 downto 0);
			dwrA: in std_logic_vector(31 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(9 downto 0);
			drdB: out std_logic_vector(31 downto 0);
			dwrB: in std_logic_vector(31 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant wD: natural := 32;
	constant logWD: natural := 2;

	constant sizeSeqbuf: natural := 4096;
	constant logSizeSeqbuf: natural := 12;

	constant tixVCaptureVsync: std_logic_vector(7 downto 0) := x"00";
	constant tixVCaptureCornerGetInfoTixVState0: std_logic_vector(7 downto 0) := x"01";
	constant tixVCaptureCornerGetInfoTixVState1: std_logic_vector(7 downto 0) := x"02";
	constant tixVCaptureReqInvRotarySet: std_logic_vector(7 downto 0) := x"03";
	constant tixVCaptureRotaryToStepmuxStep: std_logic_vector(7 downto 0) := x"04";

	constant tixVStateIdle: std_logic_vector(7 downto 0) := x"00";
	constant tixVStateArm: std_logic_vector(7 downto 0) := x"01";
	constant tixVStateAcq: std_logic_vector(7 downto 0) := x"02";
	constant tixVStateDone: std_logic_vector(7 downto 0) := x"03";

	constant tixVTriggerVoid: std_logic_vector(7 downto 0) := x"00";
	constant tixVTriggerTrigA: std_logic_vector(7 downto 0) := x"01";
	constant tixVTriggerTrigB: std_logic_vector(7 downto 0) := x"02";
	constant tixVTriggerTrigC: std_logic_vector(7 downto 0) := x"03";
	constant tixVTriggerTrigD: std_logic_vector(7 downto 0) := x"04";

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv,
		stateOpIdle,
		stateOpStart,
		stateOpRun,
		stateOpStop,
		stateOpClear
	);
	signal stateOp: stateOp_t;

	signal ackInvClearMask_sig: std_logic;
	signal ackInvSelect_sig: std_logic;
	signal ackInvSet_sig: std_logic;
	signal ackInvSetMask_sig: std_logic;

	signal staTixVTrigger: std_logic_vector(7 downto 0);
	signal staFallingNotRising: boolean;

	signal stoTixVTrigger: std_logic_vector(7 downto 0);
	signal stoFallingNotRising: boolean;

	signal mask: std_logic_vector(14 downto 0);

	signal strbStart: std_logic;
	signal strbStop: std_logic;

	---- sequence operation (seq)
	type stateSeq_t is (
		stateSeqInit,
		stateSeqIdle,
		stateSeqRun,
		stateSeqDone,
		stateSeqClear,
		stateSeqAckClear
	);
	signal stateSeq: stateSeq_t;

	signal rdySeq: std_logic;
	signal dneSeq: std_logic;

	signal TCapt: std_logic_vector(31 downto 0);

	signal ptr0SeqbufTrackNotFixed: std_logic;
	signal ptr0Seqbuf: natural range 0 to sizeSeqbuf/4-1;

	signal enSeqbuf: std_logic;

	signal aSeqbuf: natural range 0 to sizeSeqbuf/4-1;
	signal aSeqbuf_vec: std_logic_vector(logSizeSeqbuf-2-1 downto 0);

	signal dwrSeqbuf: std_logic_vector(31 downto 0);

	---- sequence buffer B/hostif-facing operation (seqbufB)
	type stateSeqbufB_t is (
		stateSeqbufBInit,
		stateSeqbufBIdle,
		stateSeqbufBXferA, stateSeqbufBXferB,
		stateSeqbufBDone,
		stateSeqbufBClear
	);
	signal stateSeqbufB: stateSeqbufB_t;

	signal enSeqbufB: std_logic;

	signal aSeqbufB: natural range 0 to sizeSeqbuf/(wD/8)-1;
	signal aSeqbufB_vec: std_logic_vector(logSizeSeqbuf-logWD-1 downto 0);

	---- sampling operation (sample)
	signal capt: std_logic_vector(14 downto 0);

	signal start: std_logic;
	signal stop: std_logic;

	---- handshake

	-- op to seq
	signal reqOpToSeqClear: std_logic;

	-- seqbufB to seq
	signal reqSeqbufBToSeqClear: std_logic;
	signal ackSeqbufBToSeqClear: std_logic;

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	mySeqbuf : Dpbram_size4kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enSeqbuf,
			weA => '1',

			aA => aSeqbuf_vec,
			drdA => open,
			dwrA => dwrSeqbuf,

			rstB => reset,
			clkB => mclk,

			enB => enSeqbufB,
			weB => '0',

			aB => aSeqbufB_vec,
			drdB => seqbufToHostifAXIS_tdata,
			dwrB => (others => '0')
		);

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	ackInvClearMask <= ackInvClearMask_sig;
	ackInvSelect <= ackInvSelect_sig;
	ackInvSet <= ackInvSet_sig;
	ackInvSetMask <= ackInvSetMask_sig;

	getInfoTixVState <= tixVStateArm when stateOp=stateOpIdle
				else tixVStateAcq when stateOp=stateOpRun
				else tixVStateDone when stateOp=stateOpStop
				else tixVStateIdle;
	getInfoTCapt <= TCapt;
	getInfoPtr0Seqbuf <= std_logic_vector(to_unsigned(ptr0Seqbuf, 16));

	strbStart <= '1' when stateOp=stateOpStart else '0';

	reqOpToSeqClear <= '1' when stateOp=stateOpClear else '0';

	process (reset, mclk, stateOp)
		variable rng: boolean;
		variable restart: boolean;

		variable TCaptMax: std_logic_vector(31 downto 0);

		variable ixMask: natural range 0 to 14;

		variable strb_last: std_logic;

	begin
		if reset='1' then
			stateOp <= stateOpInit;
			ackInvClearMask_sig <= '0';
			ackInvSelect_sig <= '0';
			ackInvSet_sig <= '0';
			ackInvSetMask_sig <= '0';
			staTixVTrigger <= tixVTriggerVoid;
			staFallingNotRising <= false;
			stoTixVTrigger <= tixVTriggerVoid;
			stoFallingNotRising <= false;
			mask <= (others => '0');
			strbStop <= '0';

			rng := false;
			restart := false;
			TCaptMax := (others => '0');
			strb_last := '0';

		elsif rising_edge(mclk) then
			if stateOp=stateOpInit or (stateOp/=stateOpInv and (reqInvClearMask='1' or reqInvSelect='1' or reqInvSet='1' or reqInvSetMask='1'))  then
				strbStop <= '0';

				if reqInvClearMask='1' then
					mask <= (others => '0');

					ackInvClearMask_sig <= '1';
					stateOp <= stateOpInv;

				elsif reqInvSelect='1' then
					staTixVTrigger <= selectStaTixVTrigger;
					staFallingNotRising <= (selectStaFallingNotRising=tru8);
					stoTixVTrigger <= selectStoTixVTrigger;
					stoFallingNotRising <= (selectStoFallingNotRising=tru8);

					ackInvSelect_sig <= '1';
					stateOp <= stateOpInv;

				elsif reqInvSet='1' then
					if setRng=tru8 then
						rng := true;
					else
						rng := false;
					end if;
					TCaptMax := setTCaptMax;

					ackInvSet_sig <= '1';
					stateOp <= stateOpInv;

				elsif reqInvSetMask='1' then
					ixMask := to_integer(unsigned(setMaskTixVCapture));
					mask(ixMask) <= '1';

					ackInvSetMask_sig <= '1';
					stateOp <= stateOpInv;

				else
					restart := false;

					if rng then
						strb_last := start;

						stateOp <= stateOpIdle;

					else
						stateOp <= stateOpInit;
					end if;
				end if;

			elsif stateOp=stateOpInv then
				if (reqInvClearMask='0' and ackInvClearMask_sig='1') or (reqInvSet='0' and ackInvSet_sig='1') or (reqInvSelect='0' and ackInvSelect_sig='1') or (reqInvSetMask='0' and ackInvSetMask_sig='1') then
					ackInvClearMask_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvSelect_sig <= '0';
					ackInvSetMask_sig <= '0';

					strbStop <= '1';

					restart := true;

					stateOp <= stateOpStop;
				end if;

			elsif stateOp=stateOpIdle then
				if staTixVTrigger=tixVTriggerVoid or (not staFallingNotRising and strb_last='0' and start='1') or (staFallingNotRising and strb_last='1' and start='0') then
					stateOp <= stateOpStart;
				else
					strb_last := start;
				end if;

			elsif stateOp=stateOpStart then -- strbStart='1'
				strb_last := stop;

				stateOp <= stateOpRun;

			elsif stateOp=stateOpRun then
				if (stoTixVTrigger=tixVTriggerVoid and unsigned(TCaptMax)/=0 and (unsigned(TCapt)>=unsigned(TCaptMax) or dneSeq='1')) or unsigned(TCapt)>=x"FFFFFF00" or (not stoFallingNotRising and strb_last='0' and stop='1') or (stoFallingNotRising and strb_last='1' and stop='0') then
					strbStop <= '1';

					stateOp <= stateOpStop;

				else
					strb_last := stop;
				end if;

			elsif stateOp=stateOpStop then
				strbStop <= '0';

				if restart then
					stateOp <= stateOpClear;

				else
					if rdySeq='1' then
						stateOp <= stateOpInit;
					end if;
				end if;

			elsif stateOp=stateOpClear then -- reqOpToSeqClear='1'
				if rdySeq='1' then
					stateOp <= stateOpInit;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: sampling operation (sample)
	------------------------------------------------------------------------

	process (reset, mclk)

	begin
		if reset='1' then
			capt <= (others => '0');
			start <= '0';
			stop <= '0';

		elsif rising_edge(mclk) then
			capt <= ("0000000000" & rotaryToStepmuxStep & reqInvRotarySet & cornerGetInfoTixVState & vsync) and not mask;

			case staTixVTrigger is
				when tixVTriggerTrigA =>
					start <= trigA;
				when tixVTriggerTrigB =>
					start <= trigB;
				when tixVTriggerTrigC =>
					start <= trigC;
				when tixVTriggerTrigD =>
					start <= trigD;
				when others =>
					start <= '0';
			end case;

			case stoTixVTrigger is
				when tixVTriggerTrigA =>
					stop <= trigA;
				when tixVTriggerTrigB =>
					stop <= trigB;
				when tixVTriggerTrigC =>
					stop <= trigC;
				when tixVTriggerTrigD =>
					stop <= trigD;
				when others =>
					stop <= '0';
			end case;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: sequence operation (seq)
	------------------------------------------------------------------------

	rdySeq <= '1' when stateSeq=stateSeqIdle else '0';
	dneSeq <= '1' when stateSeq=stateSeqDone else '0';

	ptr0Seqbuf <= aSeqbuf when ptr0SeqbufTrackNotFixed='1' else 0;

	aSeqbuf_vec <= std_logic_vector(to_unsigned(aSeqbuf, logSizeSeqbuf-2));

	ackSeqbufBToSeqClear <= '1' when stateSeq=stateSeqAckClear else '0';

	process (reset, mclk, stateSeq)
		variable quad: std_logic_vector(31 downto 0);

		variable i: natural range 0 to 3;

		variable first: boolean;
		variable stop_lcl: boolean;

		variable burstCapt: std_logic_vector(14 downto 0);
		variable burstCnt: natural range 0 to 65535;

	begin
		if reset='1' then
			stateSeq <= stateSeqInit;
			TCapt <= (others => '0');
			ptr0SeqbufTrackNotFixed <= '0';
			enSeqbuf <= '0';
			aSeqbuf <= 0;
			dwrSeqbuf <= (others => '0');

			quad := (others => '0');
			i := 0;
			first := true;
			stop_lcl := false;
			burstCapt := (others => '0');
			burstCnt := 0;

		elsif rising_edge(mclk) then
			if stateSeq=stateSeqInit then
				TCapt <= (others => '0');
				ptr0SeqbufTrackNotFixed <= '0';
				enSeqbuf <= '0';
				aSeqbuf <= 0;
				dwrSeqbuf <= (others => '0');

				quad := (others => '0');
				i := 0;
				first := true;
				stop_lcl := false;
				burstCapt := (others => '0');
				burstCnt := 0;

				stateSeq <= stateSeqIdle;

			elsif stateSeq=stateSeqIdle then -- rdySeq='1'
				if strbStart='1' then
					stateSeq <= stateSeqRun;
				end if;

			elsif stateSeq=stateSeqRun then
				TCapt <= std_logic_vector(unsigned(TCapt) + 1);

				if strbStop='1' or (stoTixVTrigger=tixVTriggerVoid and (i=0 and aSeqbuf=sizeSeqbuf/4-1)) then
					stop_lcl := true;
				end if;

				quad((i+1)*16-1) := '0';
				quad((i+1)*16-2 downto i*16) := capt;

				if i=1 then
					if quad(14 downto 0)=capt then
						if capt/=burstCapt or burstCnt=65535 then
							if not first then
								if aSeqbuf=sizeSeqbuf/4-1 then
									ptr0SeqbufTrackNotFixed <= '1';
									aSeqbuf <= 0;
								else
									aSeqbuf <= aSeqbuf + 1;
								end if;
							end if;

							burstCnt := 0;
						end if;

						burstCapt := capt;
						burstCnt := burstCnt + 1;

						dwrSeqbuf <= "1" & burstCapt & std_logic_vector(to_unsigned(burstCnt, 16));

					else
						burstCapt := (others => '0');
						burstCnt := 0;

						if not first then
							if aSeqbuf=sizeSeqbuf/4-1 then
								ptr0SeqbufTrackNotFixed <= '1';
								aSeqbuf <= 0;
							else
								aSeqbuf <= aSeqbuf + 1;
							end if;
						end if;

						dwrSeqbuf <= quad;
					end if;

					enSeqbuf <= '1';

					i := 0;
					first := false;

					stateSeq <= stateSeqRun;

				else
					enSeqbuf <= '0';

					if stop_lcl then
						stateSeq <= stateSeqDone;

					else
						i := i + 1;

						stateSeq <= stateSeqRun;
					end if;
				end if;

			elsif stateSeq=stateSeqDone then -- dneSeq='1'
				if reqOpToSeqClear='1' or reqSeqbufBToSeqClear='1' then
					aSeqbuf <= 0;
					dwrSeqbuf <= (others => '1');

					stateSeq <= stateSeqClear;
				end if;

			elsif stateSeq=stateSeqClear then
				if aSeqbuf=sizeSeqbuf/4-1 then
					if reqSeqbufBToSeqClear='1' then
						stateSeq <= stateSeqAckClear;
					else
						stateSeq <= stateSeqInit;
					end if;

				else
					aSeqbuf <= aSeqbuf + 1;
				end if;

			elsif stateSeq=stateSeqAckClear then -- ackSeqbufBToSeqClear='1'
				if reqSeqbufBToSeqClear='0' then
					stateSeq <= stateSeqInit;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: sequence buffer B/hostif-facing operation (seqbufB)
	------------------------------------------------------------------------

	ackSeqbufToHostif <= '1' when stateSeqbufB=stateSeqbufBXferA or stateSeqbufB=stateSeqbufBXferB or stateSeqbufB=stateSeqbufBDone else '0';

	avllenSeqbufToHostif <= std_logic_vector(to_unsigned(sizeSeqbuf, 32)) when dneSeq='1'
				else (others => '0');

	seqbufToHostifAXIS_tvalid <= '1' when stateSeqbufB=stateSeqbufBXferB else '0';

	seqbufToHostifAXIS_tlast <= '1' when stateSeqbufB=stateSeqbufBXferB and aSeqbufB=(sizeSeqbuf/(wD/8))-1 else '0';

	enSeqbufB <= '1' when stateSeqbufB=stateSeqbufBXferA else '0';

	aSeqbufB_vec <= std_logic_vector(to_unsigned(aSeqbufB, logSizeSeqbuf-logWD));

	reqSeqbufBToSeqClear <= '1' when stateSeqbufB=stateSeqbufBClear else '0';

	process (reset, mclk, stateSeqbufB)

	begin
		if reset='1' then
			stateSeqbufB <= stateSeqbufBInit;
			aSeqbufB <= 0;

		elsif rising_edge(mclk) then
			if stateSeqbufB=stateSeqbufBInit then
				aSeqbufB <= 0;

				stateSeqbufB <= stateSeqbufBIdle;

			elsif stateSeqbufB=stateSeqbufBIdle then
				if reqSeqbufToHostif='1' then
					stateSeqbufB <= stateSeqbufBXferA;
				end if;

			elsif stateSeqbufB=stateSeqbufBXferA then -- enSeqbufB='1'
				stateSeqbufB <= stateSeqbufBXferB;
				
			elsif stateSeqbufB=stateSeqbufBXferB then -- seqbufToHostifAXIS_tvalid='1'
				if seqbufToHostifAXIS_tready='1' then
					if aSeqbufB=(sizeSeqbuf/(wD/8))-1 then
						stateSeqbufB <= stateSeqbufBDone;

					else
						aSeqbufB <= aSeqbufB + 1;

						stateSeqbufB <= stateSeqbufBXferA;
					end if;

				elsif reqSeqbufToHostif='0' then
					stateSeqbufB <= stateSeqbufBInit;
				end if;

			elsif stateSeqbufB=stateSeqbufBDone then
				if dneSeqbufToHostif='1' then
					stateSeqbufB <= stateSeqbufBClear;

				elsif reqSeqbufToHostif='0' then
					stateSeqbufB <= stateSeqbufBInit;
				end if ;

			elsif stateSeqbufB=stateSeqbufBClear then -- reqSeqbufBToSeqClear='1'
				if reqSeqbufToHostif='0' and ackSeqbufBToSeqClear='1' then
					stateSeqbufB <= stateSeqbufBInit;
				end if;
			end if;
		end if;
	end process;

end Rtl;


-- file I2cmaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- I2cmaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06 module implementation
-- copyright: (C) 2016-2022 MPSI Technologies GmbH
-- author: Catherine Johnson (auto-generation)
-- date created: 17 Apr 2022
-- IP header --- ABOVE

-- module parameters:
-- threeNotInout (tri-state buffer configuration): true

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity I2cmaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
	generic (
		fMclk: natural := 50000;
		clkFastNotStd: std_logic := '0';
		clkFastplusNotFast: std_logic := '0'
	);
	port (
		reset: in std_logic;
		mclk: in std_logic;

		req: in std_logic;
		ack: out std_logic;
		dne: out std_logic;

		devaddr: in std_logic_vector(7 downto 0);
		r16Not8: in std_logic;
		d16Not8: in std_logic;
		readNotWrite: in std_logic;
		readAradNotArd: in std_logic;
		writeAdNotArd: in std_logic;
		regaddr: in std_logic_vector(15 downto 0);
		send: in std_logic_vector(15 downto 0);
		recv: out std_logic_vector(15 downto 0);

		scl_in: in std_logic;
		scl_out: out std_logic;
		scl_tri: out std_logic;

		sda_in: in std_logic;
		sda_out: out std_logic;
		sda_tri: out std_logic
	);
end I2cmaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of I2cmaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- transfer operation (xfer)
	type stateXfer_t is (
		stateXferInit,
		stateXferStartA, stateXferStartB,
		stateXferBitA, stateXferBitB,
		stateXferAckA, stateXferAckB,
		stateXferRestart,
		stateXferStopA, stateXferStopB, stateXferStopC,
		stateXferDone
	);
	signal stateXfer: stateXfer_t;

	signal recv_sig: std_logic_vector(15 downto 0);

	signal scl_sig: std_logic;
	signal sda_sig: std_logic;

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- implementation: transfer operation (xfer)
	------------------------------------------------------------------------

	ack <= '0' when stateXfer=stateXferInit else '1';
	dne <= '1' when stateXfer=stateXferDone else '0';

	recv <= recv_sig;

	scl_sig <= '0' when (stateXfer=stateXferBitA or stateXfer=stateXferAckA or stateXfer=stateXferRestart
				 or stateXfer=stateXferStopA) else '1';

	scl_out <= '0';
	scl_tri <= not scl_sig;

	sda_out <= '0';
	sda_tri <= not sda_sig;

	process (reset, mclk, stateXfer)
		type elem_t is (elemAddrA, elemRegMsb, elemRegLsb, elemAddrB, elemDataMsb, elemDataLsb, elemFinalize);
		variable elem: elem_t;

		variable recvraw: std_logic_vector(15 downto 0);

		variable bitcnt: natural range 0 to 8;

		variable imax: natural range 0 to (fMclk/100)/2;
		variable i: natural range 0 to (fMclk/100)/2;

	begin
		if reset='1' then
			stateXfer <= stateXferInit;
			recv_sig <= (others => '0');
			sda_sig <= '1';
			
			elem := elemAddrA;
			recvraw := (others => '0');
			bitcnt := 0;
			imax := (fMclk/100)/2;
			i := 0;

		elsif rising_edge(mclk) then
			if (stateXfer=stateXferInit or req='0') then
				recv_sig <= (others => '0');
				sda_sig <= '1';

				elem := elemAddrA;

				recvraw := (others => '0');

				bitcnt := 0;

				if clkFastNotStd='0' then
					imax := (fMclk/100)/2;
				else
					if clkFastplusNotFast='1' then
						imax := (fMclk/1000)/2;
					else
						imax := (fMclk/400)/2;
					end if;
				end if;

				i := 0;

				if req='0' then
					stateXfer <= stateXferInit;

				else
					stateXfer <= stateXferStartA;
				end if;

			elsif stateXfer=stateXferStartA then
				i := i + 1;

				if i=imax then
					i := 0;

					sda_sig <= '0';

					stateXfer <= stateXferStartB;
				end if;

			elsif stateXfer=stateXferStartB then
				i := i + 1;

				if i=imax then
					i := 0;

					bitcnt := 0;

					stateXfer <= stateXferBitA;
				end if;

			elsif stateXfer=stateXferBitA then
				if elem=elemAddrA or elem=elemAddrB then
					if bitcnt<7 then
						sda_sig <= devaddr(6-bitcnt);
					else
						if elem=elemAddrA and readNotWrite='1' and readAradNotArd='1' then
							sda_sig <= '0';
						else
							sda_sig <= readNotWrite;
						end if;
					end if;

				elsif elem=elemRegMsb then
					sda_sig <= regaddr(15-bitcnt);

				elsif elem=elemRegLsb then
					sda_sig <= regaddr(7-bitcnt);

				elsif elem=elemDataMsb and readNotWrite='0' then
					sda_sig <= send(15-bitcnt);

				elsif elem=elemDataLsb and readNotWrite='0' then
					sda_sig <= send(7-bitcnt);

				else
					sda_sig <= '1';
				end if;

				i := i + 1;

				if i=imax then
					i := 0;

					stateXfer <= stateXferBitB;
				end if;

			elsif stateXfer=stateXferBitB then
				if elem=elemDataMsb and readNotWrite='1' then
					recvraw(15-bitcnt) := sda_in;
				elsif elem=elemDataLsb and readNotWrite='1' then
					recvraw(7-bitcnt) := sda_in;
				end if;

				i := i + 1;

				if i=imax then
					i := 0;

					bitcnt := bitcnt + 1;

					if bitcnt=8 then
						stateXfer <= stateXferAckA;

					else
						stateXfer <= stateXferBitA;
					end if;
				end if;

			elsif stateXfer=stateXferAckA then
				if elem=elemDataMsb and readNotWrite='1' then
					sda_sig <= '0';
				else
					sda_sig <= '1';
				end if;

				i := i + 1;

				if i=imax then
					i := 0;

					stateXfer <= stateXferAckB;
				end if;

			elsif stateXfer=stateXferAckB then
				i := i + 1;

				if i=imax then
					i := 0;

					bitcnt := 0;

					if elem=elemAddrA then
						if readNotWrite='0' and writeAdNotArd='1' then
							if d16Not8='1' then
								elem := elemDataMsb;
							else
								elem := elemDataLsb;
							end if;

						elsif r16Not8='1' then
							elem := elemRegMsb;
						else
							elem := elemRegLsb;
						end if;

					elsif elem=elemRegMsb then
						elem := elemRegLsb;

					elsif elem=elemRegLsb then
						if readNotWrite='1' and readAradNotArd='1' then
							elem := elemAddrB;
						elsif d16Not8='1' then
							elem := elemDataMsb;
						else
							elem := elemDataLsb;
						end if;
	
					elsif elem=elemAddrB then
						if d16Not8='1' then
							elem := elemDataMsb;
						else
							elem := elemDataLsb;
						end if;

					elsif elem=elemDataMsb then
						elem := elemDataLsb;

					elsif elem=elemDataLsb then
						elem := elemFinalize;
					end if;

					if elem=elemAddrB then
						stateXfer <= stateXferRestart;

					elsif elem=elemFinalize then
						sda_sig <= '0';

						stateXfer <= stateXferStopA;

					else
						stateXfer <= stateXferBitA;
					end if;
				end if;

			elsif stateXfer=stateXferRestart then
				i := i + 1;

				if i=imax then
					i := 0;

					stateXfer <= stateXferStartA;
				end if;

			elsif stateXfer=stateXferStopA then
				i := i + 1;

				if i=imax then
					i := 0;

					stateXfer <= stateXferStopB;
				end if;

			elsif stateXfer=stateXferStopB then
				i := i + 1;

				if i=imax then
					i := 0;
					sda_sig <= '1';

					stateXfer <= stateXferStopC;
				end if;

			elsif stateXfer=stateXferStopC then
				i := i + 1;

				if i=imax then
					if readNotWrite='1' then
						recv_sig <= recvraw;
					end if;

					stateXfer <= stateXferDone;
				end if;

			elsif stateXfer=stateXferDone then
				if req='0' then
					stateXfer <= stateXferInit;
				end if;
			end if;
		end if;
	end process;

end Rtl;


-- file Ident_Easy_v1_0.vhd
-- Ident_Easy_v1_0 module implementation
-- copyright: (C) 2022 MPSI Technologies GmbH
-- author: Alexander Wirthmueller
-- date created: 15 Aug 2022
-- date modified: 26 Oct 2022
-- IP header --- ABOVE

-- module parameters:
-- hash (Git commit hash): 185b112
-- who (Git commit author): aw.mpsi
-- cfg (generics configuration): fMclk.nat.uint32;fMemclk.nat.uint32

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Ident_8c100ea18901433eb4f7c0fdbf115e06 is
	generic (
		fMclk: natural := 0;
		fMemclk: natural := 0
	);
	port (
		getUnt: out std_logic_vector(95 downto 0);
		getVer: out std_logic_vector(63 downto 0);
		getHash: out std_logic_vector(63 downto 0);
		getWho: out std_logic_vector(63 downto 0);

		getCfgFMclk: out std_logic_vector(31 downto 0);
		getCfgFMemclk: out std_logic_vector(31 downto 0)
	);
end Ident_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Ident_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant unt: string(1 to 12) := "tivsp       ";
	constant ver: string(1 to 8) := "1.2.15  ";
	constant hash: string(1 to 8) := "185b112 ";
	constant who: string(1 to 8) := "aw.mpsi ";

begin

	------------------------------------------------------------------------
	-- implementation
	------------------------------------------------------------------------

	strToSlv_unt: for i in 0 to 11 generate
		getUnt(8*(i+1)-1 downto 8*i) <= std_logic_vector(to_unsigned(character'pos(unt(i+1)), 8));
	end generate;

	strToSlv: for i in 0 to 7 generate
		getVer(8*(i+1)-1 downto 8*i) <= std_logic_vector(to_unsigned(character'pos(ver(i+1)), 8));
		getHash(8*(i+1)-1 downto 8*i) <= std_logic_vector(to_unsigned(character'pos(hash(i+1)), 8));
		getWho(8*(i+1)-1 downto 8*i) <= std_logic_vector(to_unsigned(character'pos(who(i+1)), 8));
	end generate;

	getCfgFMclk <= std_logic_vector(to_unsigned(fMclk, 32));
	getCfgFMemclk <= std_logic_vector(to_unsigned(fMemclk, 32));

end Rtl;


-- file Laser_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Laser_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Laser_8c100ea18901433eb4f7c0fdbf115e06 is
	generic (
		fMclk: natural := 50000
	);
	port (
		reset: in std_logic;
		mclk: in std_logic;

		reqInvSet: in std_logic;
		ackInvSet: out std_logic;

		setL: in std_logic_vector(15 downto 0);
		setR: in std_logic_vector(15 downto 0);

		nss: out std_logic;
		sclk: out std_logic;
		mosi: out std_logic
	);
end Laser_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Laser_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Spimaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
		generic (
			fMclk: natural := 50000;

			cpol: std_logic := '0';
			cpha: std_logic := '1';

			nssByteNotXfer: std_logic := '0';

			fSclk: natural range 100 to 50000000 := 2000000;
			Nstop: natural range 1 to 8 := 1
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;

			req: in std_logic;
			ack: out std_logic;
			dne: out std_logic;

			len: in std_logic_vector(16 downto 0);

			send: in std_logic_vector(7 downto 0);
			strbSend: out std_logic;

			recv: out std_logic_vector(7 downto 0);
			strbRecv: out std_logic;

			nss: out std_logic;
			sclk: out std_logic;
			mosi: out std_logic;
			miso: in std_logic
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpIdle,
		stateOpInv,
		stateOpSendA, stateOpSendB, stateOpSendC,
		stateOpPrepwait,
		stateOpUpdwait
	);
	signal stateOp: stateOp_t;

	signal spilen: std_logic_vector(16 downto 0);
	signal spisend: std_logic_vector(7 downto 0);

	-- IP sigs.op.cust --- INSERT

	---- mySpi
	signal strbSpisend: std_logic;

	---- handshake
	-- op to mySpi
	signal reqSpi: std_logic;
	signal ackSpi: std_logic;
	signal dneSpi: std_logic;

	---- other
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	mySpi : Spimaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06
		generic map (
			fMclk => fMclk,

			cpol => '0',
			cpha => '1',

			nssByteNotXfer => '0',

			fSclk => 2000000,
			Nstop => 1
		)
		port map (
			reset => reset,
			mclk => mclk,

			req => reqSpi,
			ack => ackSpi,
			dne => dneSpi,

			len => spilen,

			send => spisend,
			strbSend => strbSpisend,

			recv => open,
			strbRecv => open,

			nss => nss,
			sclk => sclk,
			mosi => mosi,
			miso => '0'
		);

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	ackInvSet <= '1' when stateOp=stateOpInv else '0';

	reqSpi <= '1' when (stateOp=stateOpSendA or stateOp=stateOpSendB) else '0';
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- LINE

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- BEGIN
		constant sizeTxbuf: natural := 2;
		type txbuf_t is array(0 to sizeTxbuf-1) of std_logic_vector(7 downto 0);
		variable txbuf: txbuf_t;

		variable bytecnt: natural range 0 to sizeTxbuf;
		variable updNotPrep: boolean;

		variable rNotL: boolean;
		variable r_lcl: std_logic_vector(9 downto 0);

		constant imax: natural := fMclk*8/1000; -- 8us
		variable i: natural range 0 to imax;

		constant jmax: natural := fMclk/1000; -- 1us
		variable j: natural range 0 to jmax;
		-- IP impl.op.vars --- END

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- BEGIN
			stateOp <= stateOpInit;
			spilen <= (others => '0');
			spisend <= (others => '0');

			txbuf := (x"00",x"00");
			bytecnt := 0;
			updNotPrep := false;
			rNotL := false;
			r_lcl := (others => '0');
			i := 0;
			j := 0;
			-- IP impl.op.asyncrst --- END
			-- IP impl.op.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if stateOp=stateOpInit then
				-- IP impl.op.syncrst --- RBEGIN
				spilen <= std_logic_vector(to_unsigned(sizeTxbuf, 17));

				txbuf := (x"F0",x"10"); -- DAC O/P, wake-up
				bytecnt := 0;
				updNotPrep := false;

				spisend <= txbuf(bytecnt);
				-- IP impl.op.syncrst --- REND
				-- IP impl.op.syncrst.cust --- INSERT

				stateOp <= stateOpSendA;

			elsif stateOp=stateOpIdle then
				if reqInvSet='1' then
					-- IP impl.op.idle.invSet --- IBEGIN
					txbuf(0) := "0000" & setL(9 downto 6);
					txbuf(1) := setL(5 downto 0) & "00";
					bytecnt := 0;
					updNotPrep := true;
					rNotL := false;
					r_lcl := setR(9 downto 0);

					spisend <= txbuf(bytecnt);
					-- IP impl.op.idle.invSet --- IEND

					stateOp <= stateOpInv;
				end if;

			elsif stateOp=stateOpInv then
				if reqInvSet='0' then
					stateOp <= stateOpSendA;
				end if;

			elsif stateOp=stateOpSendA then
				if dneSpi='1' then
					stateOp <= stateOpSendC;

				elsif strbSpisend='0' then
					-- IP impl.op.sendA --- IBEGIN
					bytecnt := bytecnt + 1;

					spisend <= txbuf(bytecnt);
					-- IP impl.op.sendA --- IEND

					stateOp <= stateOpSendB;
				end if;

			elsif stateOp=stateOpSendB then
				if strbSpisend='1' then
					stateOp <= stateOpSendA;
				end if;

			elsif stateOp=stateOpSendC then
				if ackSpi='0' then
					if not updNotPrep then
						i := 0; -- IP impl.op.sendC.prepdone --- ILINE

						stateOp <= stateOpPrepwait;

					else
						if not rNotL then
							-- IP impl.op.sendC.ldone --- IBEGIN
							rNotL := true;
		
							txbuf(0) := "0001" & r_lcl(9 downto 6);
							txbuf(1) := r_lcl(5 downto 0) & "00";
		
							bytecnt := 0;
		
							spisend <= txbuf(bytecnt);

							j := 0;
							-- IP impl.op.sendC.ldone --- IEND

							stateOp <= stateOpUpdwait;

						else
							stateOp <= stateOpIdle;
						end if;
					end if;
				end if;

			elsif stateOp=stateOpPrepwait then
				if i=imax then
					stateOp <= stateOpIdle;

				else
					i := i + 1; -- IP impl.op.prepwait.inc --- ILINE

					stateOp <= stateOpPrepwait;
				end if;

			elsif stateOp=stateOpUpdwait then
				if j=jmax then
					stateOp <= stateOpSendA;

				else
					j := j + 1; -- IP impl.op.updwait.inc --- ILINE

					stateOp <= stateOpUpdwait;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;


-- file Linear_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Linear_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Linear_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;
		toStepmuxNslp: out std_logic;
		toStepmuxM0: out std_logic;
		toStepmuxM0z: out std_logic;
		toStepmuxM1: out std_logic;
		toStepmuxDir: out std_logic;
		toStepmuxStep: out std_logic
	);
end Linear_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Linear_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- IBEGIN
	process (reset, mclk)
	
	begin
		if reset='1' then
			toStepmuxNslp <= '0';
			toStepmuxM0 <= '0';
			toStepmuxM0z <= '0';
			toStepmuxM1 <= '0';
			toStepmuxDir <= '0';
			toStepmuxStep <= '0';

		elsif rising_edge(mclk) then
			toStepmuxNslp <= '0';
			toStepmuxM0 <= '0';
			toStepmuxM0z <= '0';
			toStepmuxM1 <= '0';
			toStepmuxDir <= '0';
			toStepmuxStep <= '0';
		end if;
	end process;
	-- IP impl.oth.cust --- IEND

end Rtl;


-- file Memtrack_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Memtrack_8c100ea18901433eb4f7c0fdbf115e06 gptrack_Easy_v1_0 easy model debug controller implementation
-- copyright: (C) 2023 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 28 Jun 2025
-- IP header --- ABOVE

-- module parameters:
-- trkclk (clock): memclk
-- ratioTrkclk (track clock ratio wrt. master clock): 1.2
-- capts (signals to be captured): reqHdrengToDdrifRd;ackHdrengToDdrifRd;reqHdrengToDdrifWr;ackHdrengToDdrifWr;ddrAXI_rvalid;ddrAXI_rready_sig;ddrAXI_wready;ddrAXI_bvalid;ddrAXI_wvalid_sig
-- trigs (triggers): vsync.mclk;rgbVideoinToManyAXIS_tlast.mclk
-- sizeSeqbuf (sequence buffer size [kB]): 4

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Memtrack_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		resetMemclk: in std_logic;
		memclk: in std_logic;

		vsync: in std_logic;
		rgbVideoinToManyAXIS_tlast: in std_logic;

		reqInvClearMask: in std_logic;
		ackInvClearMask: out std_logic;

		getInfoTixVState: out std_logic_vector(7 downto 0);
		getInfoTCapt: out std_logic_vector(31 downto 0);
		getInfoPtr0Seqbuf: out std_logic_vector(15 downto 0);

		reqInvSelect: in std_logic;
		ackInvSelect: out std_logic;

		selectStaTixVTrigger: in std_logic_vector(7 downto 0);
		selectStaFallingNotRising: in std_logic_vector(7 downto 0);
		selectStoTixVTrigger: in std_logic_vector(7 downto 0);
		selectStoFallingNotRising: in std_logic_vector(7 downto 0);

		reqInvSet: in std_logic;
		ackInvSet: out std_logic;

		setRng: in std_logic_vector(7 downto 0);
		setTCaptMax: in std_logic_vector(31 downto 0);

		reqInvSetMask: in std_logic;
		ackInvSetMask: out std_logic;

		setMaskTixVCapture: in std_logic_vector(7 downto 0);

		reqSeqbufToHostif: in std_logic;
		ackSeqbufToHostif: out std_logic;
		dneSeqbufToHostif: in std_logic;
		avllenSeqbufToHostif: out std_logic_vector(31 downto 0);

		seqbufToHostifAXIS_tready: in std_logic;
		seqbufToHostifAXIS_tvalid: out std_logic;
		seqbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
		seqbufToHostifAXIS_tlast: out std_logic;

		reqHdrengToDdrifRd: in std_logic;
		ackHdrengToDdrifRd: in std_logic;
		reqHdrengToDdrifWr: in std_logic;
		ackHdrengToDdrifWr: in std_logic;
		ddrAXI_rvalid: in std_logic;
		ddrAXI_rready_sig: in std_logic;
		ddrAXI_wready: in std_logic;
		ddrAXI_bvalid: in std_logic;
		ddrAXI_wvalid_sig: in std_logic
	);
end Memtrack_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Memtrack_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_size4kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(9 downto 0);
			drdA: out std_logic_vector(31 downto 0);
			dwrA: in std_logic_vector(31 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(9 downto 0);
			drdB: out std_logic_vector(31 downto 0);
			dwrB: in std_logic_vector(31 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant wD: natural := 32;
	constant logWD: natural := 2;

	constant sizeSeqbuf: natural := 4096;
	constant logSizeSeqbuf: natural := 12;

	constant tixVCaptureReqHdrengToDdrifRd: std_logic_vector(7 downto 0) := x"00";
	constant tixVCaptureAckHdrengToDdrifRd: std_logic_vector(7 downto 0) := x"01";
	constant tixVCaptureReqHdrengToDdrifWr: std_logic_vector(7 downto 0) := x"02";
	constant tixVCaptureAckHdrengToDdrifWr: std_logic_vector(7 downto 0) := x"03";
	constant tixVCaptureDdrAXI_rvalid: std_logic_vector(7 downto 0) := x"04";
	constant tixVCaptureDdrAXI_rready_sig: std_logic_vector(7 downto 0) := x"05";
	constant tixVCaptureDdrAXI_wready: std_logic_vector(7 downto 0) := x"06";
	constant tixVCaptureDdrAXI_bvalid: std_logic_vector(7 downto 0) := x"07";
	constant tixVCaptureDdrAXI_wvalid_sig: std_logic_vector(7 downto 0) := x"08";

	constant tixVStateIdle: std_logic_vector(7 downto 0) := x"00";
	constant tixVStateArm: std_logic_vector(7 downto 0) := x"01";
	constant tixVStateAcq: std_logic_vector(7 downto 0) := x"02";
	constant tixVStateDone: std_logic_vector(7 downto 0) := x"03";

	constant tixVTriggerVoid: std_logic_vector(7 downto 0) := x"00";
	constant tixVTriggerVsync: std_logic_vector(7 downto 0) := x"01";
	constant tixVTriggerRgbVideoinToManyAXIS_tlast: std_logic_vector(7 downto 0) := x"02";

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv,
		stateOpIdle,
		stateOpStart,
		stateOpRun,
		stateOpStop,
		stateOpClear
	);
	signal stateOp: stateOp_t;

	signal ackInvClearMask_sig: std_logic;
	signal ackInvSelect_sig: std_logic;
	signal ackInvSet_sig: std_logic;
	signal ackInvSetMask_sig: std_logic;

	signal staTixVTrigger: std_logic_vector(7 downto 0);
	signal staFallingNotRising: boolean;

	signal stoTixVTrigger: std_logic_vector(7 downto 0);
	signal stoFallingNotRising: boolean;

	signal mask: std_logic_vector(14 downto 0);

	signal strbStart: std_logic;
	signal strbStop: std_logic;

	---- sequence operation (seq)
	type stateSeq_t is (
		stateSeqInit,
		stateSeqIdle,
		stateSeqRun,
		stateSeqDone,
		stateSeqClear,
		stateSeqAckClear
	);
	signal stateSeq: stateSeq_t;

	signal rdySeq: std_logic;
	signal dneSeq: std_logic;

	signal TCapt: std_logic_vector(31 downto 0);

	signal ptr0SeqbufTrackNotFixed: std_logic;
	signal ptr0Seqbuf: natural range 0 to sizeSeqbuf/4-1;

	signal enSeqbuf: std_logic;

	signal aSeqbuf: natural range 0 to sizeSeqbuf/4-1;
	signal aSeqbuf_vec: std_logic_vector(logSizeSeqbuf-2-1 downto 0);

	signal dwrSeqbuf: std_logic_vector(31 downto 0);

	---- sequence buffer B/hostif-facing operation (seqbufB)
	type stateSeqbufB_t is (
		stateSeqbufBInit,
		stateSeqbufBIdle,
		stateSeqbufBXferA, stateSeqbufBXferB,
		stateSeqbufBDone,
		stateSeqbufBClear
	);
	signal stateSeqbufB: stateSeqbufB_t;

	signal enSeqbufB: std_logic;

	signal aSeqbufB: natural range 0 to sizeSeqbuf/(wD/8)-1;
	signal aSeqbufB_vec: std_logic_vector(logSizeSeqbuf-logWD-1 downto 0);

	---- sampling operation (sample)
	signal capt: std_logic_vector(14 downto 0);

	signal start: std_logic;
	signal stop: std_logic;

	---- mclk to memclk CDC sampling (mclkToMemclkSample)

	signal capt_memclk: std_logic_vector(14 downto 0);
	signal capt_to_memclkm1: std_logic_vector(14 downto 0);
	signal capt_to_memclkm2: std_logic_vector(14 downto 0);
	signal staTixVTrigger_memclk: std_logic_vector(7 downto 0);
	signal staTixVTrigger_to_memclkm1: std_logic_vector(7 downto 0);
	signal staTixVTrigger_to_memclkm2: std_logic_vector(7 downto 0);
	signal stoTixVTrigger_memclk: std_logic_vector(7 downto 0);
	signal stoTixVTrigger_to_memclkm1: std_logic_vector(7 downto 0);
	signal stoTixVTrigger_to_memclkm2: std_logic_vector(7 downto 0);
	signal strbStart_memclk: std_logic;
	signal strbStart_to_memclkm1: std_logic;
	signal strbStart_to_memclkm2: std_logic;
	signal strbStop_memclk: std_logic;
	signal strbStop_to_memclkm1: std_logic;
	signal strbStop_to_memclkm2: std_logic;
	signal reqOpToSeqClear_memclk: std_logic;
	signal reqOpToSeqClear_to_memclkm1: std_logic;
	signal reqOpToSeqClear_to_memclkm2: std_logic;
	signal reqSeqbufBToSeqClear_memclk: std_logic;
	signal reqSeqbufBToSeqClear_to_memclkm1: std_logic;
	signal reqSeqbufBToSeqClear_to_memclkm2: std_logic;

	---- mclk to memclk CDC stretching (mclkToMemclkStretch)

	signal capt_to_memclk: std_logic_vector(14 downto 0);
	signal staTixVTrigger_to_memclk: std_logic_vector(7 downto 0);
	signal stoTixVTrigger_to_memclk: std_logic_vector(7 downto 0);
	signal strbStart_to_memclk: std_logic;
	signal strbStop_to_memclk: std_logic;
	signal reqOpToSeqClear_to_memclk: std_logic;
	signal reqSeqbufBToSeqClear_to_memclk: std_logic;

	---- memclk to mclk CDC sampling (memclkToMclkSample)

	signal rdySeq_mclk: std_logic;
	signal rdySeq_to_mclkm1: std_logic;
	signal rdySeq_to_mclkm2: std_logic;
	signal dneSeq_mclk: std_logic;
	signal dneSeq_to_mclkm1: std_logic;
	signal dneSeq_to_mclkm2: std_logic;
	signal TCapt_mclk: std_logic_vector(31 downto 0);
	signal TCapt_to_mclkm1: std_logic_vector(31 downto 0);
	signal TCapt_to_mclkm2: std_logic_vector(31 downto 0);
	signal ptr0Seqbuf_mclk: natural range 0 to sizeSeqbuf/4-1;
	signal ptr0Seqbuf_to_mclkm1: natural range 0 to sizeSeqbuf/4-1;
	signal ptr0Seqbuf_to_mclkm2: natural range 0 to sizeSeqbuf/4-1;
	signal start_mclk: std_logic;
	signal start_to_mclkm1: std_logic;
	signal start_to_mclkm2: std_logic;
	signal stop_mclk: std_logic;
	signal stop_to_mclkm1: std_logic;
	signal stop_to_mclkm2: std_logic;
	signal ackSeqbufBToSeqClear_mclk: std_logic;
	signal ackSeqbufBToSeqClear_to_mclkm1: std_logic;
	signal ackSeqbufBToSeqClear_to_mclkm2: std_logic;

	---- memclk to mclk CDC stretching (memclkToMclkStretch)

	signal rdySeq_to_mclk: std_logic;
	signal dneSeq_to_mclk: std_logic;
	signal TCapt_to_mclk: std_logic_vector(31 downto 0);
	signal ptr0Seqbuf_to_mclk: natural range 0 to sizeSeqbuf/4-1;
	signal start_to_mclk: std_logic;
	signal stop_to_mclk: std_logic;
	signal ackSeqbufBToSeqClear_to_mclk: std_logic;

	---- handshake

	-- op to seq
	signal reqOpToSeqClear: std_logic;

	-- seqbufB to seq
	signal reqSeqbufBToSeqClear: std_logic;
	signal ackSeqbufBToSeqClear: std_logic;

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	mySeqbuf : Dpbram_size4kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => resetMemclk,
			clkA => memclk,

			enA => enSeqbuf,
			weA => '1',

			aA => aSeqbuf_vec,
			drdA => open,
			dwrA => dwrSeqbuf,

			rstB => reset,
			clkB => mclk,

			enB => enSeqbufB,
			weB => '0',

			aB => aSeqbufB_vec,
			drdB => seqbufToHostifAXIS_tdata,
			dwrB => (others => '0')
		);

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	ackInvClearMask <= ackInvClearMask_sig;
	ackInvSelect <= ackInvSelect_sig;
	ackInvSet <= ackInvSet_sig;
	ackInvSetMask <= ackInvSetMask_sig;

	getInfoTixVState <= tixVStateArm when stateOp=stateOpIdle
				else tixVStateAcq when stateOp=stateOpRun
				else tixVStateDone when stateOp=stateOpStop
				else tixVStateIdle;
	getInfoTCapt <= TCapt_mclk;
	getInfoPtr0Seqbuf <= std_logic_vector(to_unsigned(ptr0Seqbuf_mclk, 16));

	strbStart <= '1' when stateOp=stateOpStart else '0';

	reqOpToSeqClear <= '1' when stateOp=stateOpClear else '0';

	process (reset, mclk, stateOp)
		variable rng: boolean;
		variable restart: boolean;

		variable TCaptMax: std_logic_vector(31 downto 0);

		variable ixMask: natural range 0 to 14;

		variable strb_last: std_logic;

	begin
		if reset='1' then
			stateOp <= stateOpInit;
			ackInvClearMask_sig <= '0';
			ackInvSelect_sig <= '0';
			ackInvSet_sig <= '0';
			ackInvSetMask_sig <= '0';
			staTixVTrigger <= tixVTriggerVoid;
			staFallingNotRising <= false;
			stoTixVTrigger <= tixVTriggerVoid;
			stoFallingNotRising <= false;
			mask <= (others => '0');
			strbStop <= '0';

			rng := false;
			restart := false;
			TCaptMax := (others => '0');
			strb_last := '0';

		elsif rising_edge(mclk) then
			if stateOp=stateOpInit or (stateOp/=stateOpInv and (reqInvClearMask='1' or reqInvSelect='1' or reqInvSet='1' or reqInvSetMask='1'))  then
				strbStop <= '0';

				if reqInvClearMask='1' then
					mask <= (others => '0');

					ackInvClearMask_sig <= '1';
					stateOp <= stateOpInv;

				elsif reqInvSelect='1' then
					staTixVTrigger <= selectStaTixVTrigger;
					staFallingNotRising <= (selectStaFallingNotRising=tru8);
					stoTixVTrigger <= selectStoTixVTrigger;
					stoFallingNotRising <= (selectStoFallingNotRising=tru8);

					ackInvSelect_sig <= '1';
					stateOp <= stateOpInv;

				elsif reqInvSet='1' then
					if setRng=tru8 then
						rng := true;
					else
						rng := false;
					end if;
					TCaptMax := setTCaptMax;

					ackInvSet_sig <= '1';
					stateOp <= stateOpInv;

				elsif reqInvSetMask='1' then
					ixMask := to_integer(unsigned(setMaskTixVCapture));
					mask(ixMask) <= '1';

					ackInvSetMask_sig <= '1';
					stateOp <= stateOpInv;

				else
					restart := false;

					if rng then
						strb_last := start_mclk;

						stateOp <= stateOpIdle;

					else
						stateOp <= stateOpInit;
					end if;
				end if;

			elsif stateOp=stateOpInv then
				if (reqInvClearMask='0' and ackInvClearMask_sig='1') or (reqInvSet='0' and ackInvSet_sig='1') or (reqInvSelect='0' and ackInvSelect_sig='1') or (reqInvSetMask='0' and ackInvSetMask_sig='1') then
					ackInvClearMask_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvSelect_sig <= '0';
					ackInvSetMask_sig <= '0';

					strbStop <= '1';

					restart := true;

					stateOp <= stateOpStop;
				end if;

			elsif stateOp=stateOpIdle then
				if staTixVTrigger=tixVTriggerVoid or (not staFallingNotRising and strb_last='0' and start_mclk='1') or (staFallingNotRising and strb_last='1' and start_mclk='0') then
					stateOp <= stateOpStart;
				else
					strb_last := start_mclk;
				end if;

			elsif stateOp=stateOpStart then -- strbStart='1'
				strb_last := stop_mclk;

				stateOp <= stateOpRun;

			elsif stateOp=stateOpRun then
				if (stoTixVTrigger=tixVTriggerVoid and unsigned(TCaptMax)/=0 and (unsigned(TCapt_mclk)>=unsigned(TCaptMax) or dneSeq_mclk='1')) or unsigned(TCapt_mclk)>=x"FFFFFF00" or (not stoFallingNotRising and strb_last='0' and stop_mclk='1') or (stoFallingNotRising and strb_last='1' and stop_mclk='0') then
					strbStop <= '1';

					stateOp <= stateOpStop;

				else
					strb_last := stop_mclk;
				end if;

			elsif stateOp=stateOpStop then
				strbStop <= '0';

				if restart then
					stateOp <= stateOpClear;

				else
					if rdySeq_mclk='1' then
						stateOp <= stateOpInit;
					end if;
				end if;

			elsif stateOp=stateOpClear then -- reqOpToSeqClear='1'
				if rdySeq_mclk='1' then
					stateOp <= stateOpInit;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: sampling operation (sample)
	------------------------------------------------------------------------

	process (resetMemclk, memclk)

	begin
		if resetMemclk='1' then
			capt <= (others => '0');
			start <= '0';
			stop <= '0';

		elsif rising_edge(memclk) then
			capt <= ("000000" & ddrAXI_wvalid_sig & ddrAXI_bvalid & ddrAXI_wready & ddrAXI_rready_sig & ddrAXI_rvalid & ackHdrengToDdrifWr & reqHdrengToDdrifWr & ackHdrengToDdrifRd & reqHdrengToDdrifRd) and not mask;

			case staTixVTrigger_memclk is
				when tixVTriggerVsync =>
					start <= vsync;
				when tixVTriggerRgbVideoinToManyAXIS_tlast =>
					start <= rgbVideoinToManyAXIS_tlast;
				when others =>
					start <= '0';
			end case;

			case stoTixVTrigger_memclk is
				when tixVTriggerVsync =>
					stop <= vsync;
				when tixVTriggerRgbVideoinToManyAXIS_tlast =>
					stop <= rgbVideoinToManyAXIS_tlast;
				when others =>
					stop <= '0';
			end case;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: sequence operation (seq)
	------------------------------------------------------------------------

	rdySeq <= '1' when stateSeq=stateSeqIdle else '0';
	dneSeq <= '1' when stateSeq=stateSeqDone else '0';

	ptr0Seqbuf <= aSeqbuf when ptr0SeqbufTrackNotFixed='1' else 0;

	aSeqbuf_vec <= std_logic_vector(to_unsigned(aSeqbuf, logSizeSeqbuf-2));

	ackSeqbufBToSeqClear <= '1' when stateSeq=stateSeqAckClear else '0';

	process (resetMemclk, memclk, stateSeq)
		variable quad: std_logic_vector(31 downto 0);

		variable i: natural range 0 to 3;

		variable first: boolean;
		variable stop_lcl: boolean;

		variable burstCapt: std_logic_vector(14 downto 0);
		variable burstCnt: natural range 0 to 65535;

	begin
		if resetMemclk='1' then
			stateSeq <= stateSeqInit;
			TCapt <= (others => '0');
			ptr0SeqbufTrackNotFixed <= '0';
			enSeqbuf <= '0';
			aSeqbuf <= 0;
			dwrSeqbuf <= (others => '0');

			quad := (others => '0');
			i := 0;
			first := true;
			stop_lcl := false;
			burstCapt := (others => '0');
			burstCnt := 0;

		elsif rising_edge(memclk) then
			if stateSeq=stateSeqInit then
				TCapt <= (others => '0');
				ptr0SeqbufTrackNotFixed <= '0';
				enSeqbuf <= '0';
				aSeqbuf <= 0;
				dwrSeqbuf <= (others => '0');

				quad := (others => '0');
				i := 0;
				first := true;
				stop_lcl := false;
				burstCapt := (others => '0');
				burstCnt := 0;

				stateSeq <= stateSeqIdle;

			elsif stateSeq=stateSeqIdle then -- rdySeq='1'
				if strbStart_memclk='1' then
					stateSeq <= stateSeqRun;
				end if;

			elsif stateSeq=stateSeqRun then
				TCapt <= std_logic_vector(unsigned(TCapt) + 1);

				if strbStop_memclk='1' or (stoTixVTrigger=tixVTriggerVoid and (i=0 and aSeqbuf=sizeSeqbuf/4-1)) then
					stop_lcl := true;
				end if;

				quad((i+1)*16-1) := '0';
				quad((i+1)*16-2 downto i*16) := capt;

				if i=1 then
					if quad(14 downto 0)=capt then
						if capt/=burstCapt or burstCnt=65535 then
							if not first then
								if aSeqbuf=sizeSeqbuf/4-1 then
									ptr0SeqbufTrackNotFixed <= '1';
									aSeqbuf <= 0;
								else
									aSeqbuf <= aSeqbuf + 1;
								end if;
							end if;

							burstCnt := 0;
						end if;

						burstCapt := capt;
						burstCnt := burstCnt + 1;

						dwrSeqbuf <= "1" & burstCapt & std_logic_vector(to_unsigned(burstCnt, 16));

					else
						burstCapt := (others => '0');
						burstCnt := 0;

						if not first then
							if aSeqbuf=sizeSeqbuf/4-1 then
								ptr0SeqbufTrackNotFixed <= '1';
								aSeqbuf <= 0;
							else
								aSeqbuf <= aSeqbuf + 1;
							end if;
						end if;

						dwrSeqbuf <= quad;
					end if;

					enSeqbuf <= '1';

					i := 0;
					first := false;

					stateSeq <= stateSeqRun;

				else
					enSeqbuf <= '0';

					if stop_lcl then
						stateSeq <= stateSeqDone;

					else
						i := i + 1;

						stateSeq <= stateSeqRun;
					end if;
				end if;

			elsif stateSeq=stateSeqDone then -- dneSeq='1'
				if reqOpToSeqClear_memclk='1' or reqSeqbufBToSeqClear_memclk='1' then
					aSeqbuf <= 0;
					dwrSeqbuf <= (others => '1');

					stateSeq <= stateSeqClear;
				end if;

			elsif stateSeq=stateSeqClear then
				if aSeqbuf=sizeSeqbuf/4-1 then
					if reqSeqbufBToSeqClear_memclk='1' then
						stateSeq <= stateSeqAckClear;
					else
						stateSeq <= stateSeqInit;
					end if;

				else
					aSeqbuf <= aSeqbuf + 1;
				end if;

			elsif stateSeq=stateSeqAckClear then -- ackSeqbufBToSeqClear='1'
				if reqSeqbufBToSeqClear_memclk='0' then
					stateSeq <= stateSeqInit;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: sequence buffer B/hostif-facing operation (seqbufB)
	------------------------------------------------------------------------

	ackSeqbufToHostif <= '1' when stateSeqbufB=stateSeqbufBXferA or stateSeqbufB=stateSeqbufBXferB or stateSeqbufB=stateSeqbufBDone else '0';

	avllenSeqbufToHostif <= std_logic_vector(to_unsigned(sizeSeqbuf, 32)) when dneSeq_mclk='1'
				else (others => '0');

	seqbufToHostifAXIS_tvalid <= '1' when stateSeqbufB=stateSeqbufBXferB else '0';

	seqbufToHostifAXIS_tlast <= '1' when stateSeqbufB=stateSeqbufBXferB and aSeqbufB=(sizeSeqbuf/(wD/8))-1 else '0';

	enSeqbufB <= '1' when stateSeqbufB=stateSeqbufBXferA else '0';

	aSeqbufB_vec <= std_logic_vector(to_unsigned(aSeqbufB, logSizeSeqbuf-logWD));

	reqSeqbufBToSeqClear <= '1' when stateSeqbufB=stateSeqbufBClear else '0';

	process (reset, mclk, stateSeqbufB)

	begin
		if reset='1' then
			stateSeqbufB <= stateSeqbufBInit;
			aSeqbufB <= 0;

		elsif rising_edge(mclk) then
			if stateSeqbufB=stateSeqbufBInit then
				aSeqbufB <= 0;

				stateSeqbufB <= stateSeqbufBIdle;

			elsif stateSeqbufB=stateSeqbufBIdle then
				if reqSeqbufToHostif='1' then
					stateSeqbufB <= stateSeqbufBXferA;
				end if;

			elsif stateSeqbufB=stateSeqbufBXferA then -- enSeqbufB='1'
				stateSeqbufB <= stateSeqbufBXferB;
				
			elsif stateSeqbufB=stateSeqbufBXferB then -- seqbufToHostifAXIS_tvalid='1'
				if seqbufToHostifAXIS_tready='1' then
					if aSeqbufB=(sizeSeqbuf/(wD/8))-1 then
						stateSeqbufB <= stateSeqbufBDone;

					else
						aSeqbufB <= aSeqbufB + 1;

						stateSeqbufB <= stateSeqbufBXferA;
					end if;

				elsif reqSeqbufToHostif='0' then
					stateSeqbufB <= stateSeqbufBInit;
				end if;

			elsif stateSeqbufB=stateSeqbufBDone then
				if dneSeqbufToHostif='1' then
					stateSeqbufB <= stateSeqbufBClear;

				elsif reqSeqbufToHostif='0' then
					stateSeqbufB <= stateSeqbufBInit;
				end if ;

			elsif stateSeqbufB=stateSeqbufBClear then -- reqSeqbufBToSeqClear='1'
				if reqSeqbufToHostif='0' and ackSeqbufBToSeqClear='1' then
					stateSeqbufB <= stateSeqbufBInit;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: mclk to memclk CDC sampling (mclkToMemclkSample)
	------------------------------------------------------------------------

	-- IP impl.mclkToMemclkSample.wiring --- BEGIN
	-- IP impl.mclkToMemclkSample.wiring --- END

	-- IP impl.mclkToMemclkSample.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.mclkToMemclkSample.vars --- BEGIN
		variable strbStart_wait: boolean;
		variable strbStop_wait: boolean;
		-- IP impl.mclkToMemclkSample.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.mclkToMemclkSample.asyncrst --- BEGIN
			capt_memclk <= (others => '0');
			capt_to_memclkm1 <= (others => '0');
			capt_to_memclkm2 <= (others => '0');
			staTixVTrigger_memclk <= (others => '0');
			staTixVTrigger_to_memclkm1 <= (others => '0');
			staTixVTrigger_to_memclkm2 <= (others => '0');
			stoTixVTrigger_memclk <= (others => '0');
			stoTixVTrigger_to_memclkm1 <= (others => '0');
			stoTixVTrigger_to_memclkm2 <= (others => '0');
			strbStart_memclk <= '0';
			strbStart_to_memclkm1 <= '0';
			strbStart_to_memclkm2 <= '0';
			strbStop_memclk <= '0';
			strbStop_to_memclkm1 <= '0';
			strbStop_to_memclkm2 <= '0';
			reqOpToSeqClear_memclk <= '0';
			reqOpToSeqClear_to_memclkm1 <= '0';
			reqOpToSeqClear_to_memclkm2 <= '0';
			reqSeqbufBToSeqClear_memclk <= '0';
			reqSeqbufBToSeqClear_to_memclkm1 <= '0';
			reqSeqbufBToSeqClear_to_memclkm2 <= '0';

			strbStart_wait := false;
			strbStop_wait := false;
			-- IP impl.mclkToMemclkSample.asyncrst --- END
			-- IP impl.mclkToMemclkSample.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if capt_to_memclkm1=capt_to_memclkm2 then
				capt_memclk <= capt_to_memclkm2;
			end if;
			capt_to_memclkm1 <= capt_to_memclk;
			capt_to_memclkm2 <= capt_to_memclkm1;

			if staTixVTrigger_to_memclkm1=staTixVTrigger_to_memclkm2 then
				staTixVTrigger_memclk <= staTixVTrigger_to_memclkm2;
			end if;
			staTixVTrigger_to_memclkm1 <= staTixVTrigger_to_memclk;
			staTixVTrigger_to_memclkm2 <= staTixVTrigger_to_memclkm1;

			if stoTixVTrigger_to_memclkm1=stoTixVTrigger_to_memclkm2 then
				stoTixVTrigger_memclk <= stoTixVTrigger_to_memclkm2;
			end if;
			stoTixVTrigger_to_memclkm1 <= stoTixVTrigger_to_memclk;
			stoTixVTrigger_to_memclkm2 <= stoTixVTrigger_to_memclkm1;

			if strbStart_memclk='1' then
				strbStart_memclk <= '0';
			elsif strbStart_to_memclkm1='1' and strbStart_to_memclkm2='1' and not strbStart_wait then
				strbStart_memclk <= '1';
				strbStart_wait := true;
			end if;
			if strbStart_to_memclkm1='0' and strbStart_to_memclkm2='0' and strbStart_wait then
				strbStart_wait := false;
			end if;
			strbStart_to_memclkm1 <= strbStart_to_memclk;
			strbStart_to_memclkm2 <= strbStart_to_memclkm1;

			if strbStop_memclk='1' then
				strbStop_memclk <= '0';
			elsif strbStop_to_memclkm1='1' and strbStop_to_memclkm2='1' and not strbStop_wait then
				strbStop_memclk <= '1';
				strbStop_wait := true;
			end if;
			if strbStop_to_memclkm1='0' and strbStop_to_memclkm2='0' and strbStop_wait then
				strbStop_wait := false;
			end if;
			strbStop_to_memclkm1 <= strbStop_to_memclk;
			strbStop_to_memclkm2 <= strbStop_to_memclkm1;

			if reqOpToSeqClear_to_memclkm1=reqOpToSeqClear_to_memclkm2 then
				reqOpToSeqClear_memclk <= reqOpToSeqClear_to_memclkm2;
			end if;
			reqOpToSeqClear_to_memclkm1 <= reqOpToSeqClear_to_memclk;
			reqOpToSeqClear_to_memclkm2 <= reqOpToSeqClear_to_memclkm1;

			if reqSeqbufBToSeqClear_to_memclkm1=reqSeqbufBToSeqClear_to_memclkm2 then
				reqSeqbufBToSeqClear_memclk <= reqSeqbufBToSeqClear_to_memclkm2;
			end if;
			reqSeqbufBToSeqClear_to_memclkm1 <= reqSeqbufBToSeqClear_to_memclk;
			reqSeqbufBToSeqClear_to_memclkm2 <= reqSeqbufBToSeqClear_to_memclkm1;

		end if;
	end process;
	-- IP impl.mclkToMemclkSample.rising --- END

	------------------------------------------------------------------------
	-- implementation: mclk to memclk CDC stretching (mclkToMemclkStretch)
	------------------------------------------------------------------------

	-- IP impl.mclkToMemclkStretch.wiring --- BEGIN
	-- IP impl.mclkToMemclkStretch.wiring --- END

	-- IP impl.mclkToMemclkStretch.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.mclkToMemclkStretch.vars --- BEGIN
		constant imax: natural := 1;

		variable capt_i: natural range 0 to imax;
		variable staTixVTrigger_i: natural range 0 to imax;
		variable stoTixVTrigger_i: natural range 0 to imax;
		variable strbStart_i: natural range 0 to imax;
		variable strbStop_i: natural range 0 to imax;
		variable reqOpToSeqClear_i: natural range 0 to imax;
		variable reqSeqbufBToSeqClear_i: natural range 0 to imax;
		-- IP impl.mclkToMemclkStretch.vars --- END

	begin
		if reset='1' then
			-- IP impl.mclkToMemclkStretch.asyncrst --- BEGIN
			capt_to_memclk <= (others => '0');
			staTixVTrigger_to_memclk <= (others => '0');
			stoTixVTrigger_to_memclk <= (others => '0');
			strbStart_to_memclk <= '0';
			strbStop_to_memclk <= '0';
			reqOpToSeqClear_to_memclk <= '0';
			reqSeqbufBToSeqClear_to_memclk <= '0';

			capt_i := 0;
			staTixVTrigger_i := 0;
			stoTixVTrigger_i := 0;
			strbStart_i := 0;
			strbStop_i := 0;
			reqOpToSeqClear_i := 0;
			reqSeqbufBToSeqClear_i := 0;
			-- IP impl.mclkToMemclkStretch.asyncrst --- END
			-- IP impl.mclkToMemclkStretch.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if capt_i=imax then
				if capt/=capt_to_memclk then
					capt_to_memclk <= capt;
					capt_i := 0;
				end if;
			else
				capt_i := capt_i + 1;
			end if;

			if staTixVTrigger_i=imax then
				if staTixVTrigger/=staTixVTrigger_to_memclk then
					staTixVTrigger_to_memclk <= staTixVTrigger;
					staTixVTrigger_i := 0;
				end if;
			else
				staTixVTrigger_i := staTixVTrigger_i + 1;
			end if;

			if stoTixVTrigger_i=imax then
				if stoTixVTrigger/=stoTixVTrigger_to_memclk then
					stoTixVTrigger_to_memclk <= stoTixVTrigger;
					stoTixVTrigger_i := 0;
				end if;
			else
				stoTixVTrigger_i := stoTixVTrigger_i + 1;
			end if;

			if strbStart='1' then
				strbStart_to_memclk <= '1';
				strbStart_i := 0;
			elsif strbStart_i=imax then
				strbStart_to_memclk <= '0';
			else
				strbStart_i := strbStart_i + 1;
			end if;

			if strbStop='1' then
				strbStop_to_memclk <= '1';
				strbStop_i := 0;
			elsif strbStop_i=imax then
				strbStop_to_memclk <= '0';
			else
				strbStop_i := strbStop_i + 1;
			end if;

			if reqOpToSeqClear_i=imax then
				if reqOpToSeqClear/=reqOpToSeqClear_to_memclk then
					reqOpToSeqClear_to_memclk <= reqOpToSeqClear;
					reqOpToSeqClear_i := 0;
				end if;
			else
				reqOpToSeqClear_i := reqOpToSeqClear_i + 1;
			end if;

			if reqSeqbufBToSeqClear_i=imax then
				if reqSeqbufBToSeqClear/=reqSeqbufBToSeqClear_to_memclk then
					reqSeqbufBToSeqClear_to_memclk <= reqSeqbufBToSeqClear;
					reqSeqbufBToSeqClear_i := 0;
				end if;
			else
				reqSeqbufBToSeqClear_i := reqSeqbufBToSeqClear_i + 1;
			end if;

		end if;
	end process;
	-- IP impl.mclkToMemclkStretch.rising --- END

	------------------------------------------------------------------------
	-- implementation: memclk to mclk CDC sampling (memclkToMclkSample)
	------------------------------------------------------------------------

	-- IP impl.memclkToMclkSample.wiring --- BEGIN
	-- IP impl.memclkToMclkSample.wiring --- END

	-- IP impl.memclkToMclkSample.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.memclkToMclkSample.vars --- BEGIN
		-- IP impl.memclkToMclkSample.vars --- END

	begin
		if reset='1' then
			-- IP impl.memclkToMclkSample.asyncrst --- BEGIN
			rdySeq_mclk <= '0';
			rdySeq_to_mclkm1 <= '0';
			rdySeq_to_mclkm2 <= '0';
			dneSeq_mclk <= '0';
			dneSeq_to_mclkm1 <= '0';
			dneSeq_to_mclkm2 <= '0';
			TCapt_mclk <= (others => '0');
			TCapt_to_mclkm1 <= (others => '0');
			TCapt_to_mclkm2 <= (others => '0');
			ptr0Seqbuf_mclk <= 0;
			ptr0Seqbuf_to_mclkm1 <= 0;
			ptr0Seqbuf_to_mclkm2 <= 0;
			start_mclk <= '0';
			start_to_mclkm1 <= '0';
			start_to_mclkm2 <= '0';
			stop_mclk <= '0';
			stop_to_mclkm1 <= '0';
			stop_to_mclkm2 <= '0';
			ackSeqbufBToSeqClear_mclk <= '0';
			ackSeqbufBToSeqClear_to_mclkm1 <= '0';
			ackSeqbufBToSeqClear_to_mclkm2 <= '0';

			-- IP impl.memclkToMclkSample.asyncrst --- END
			-- IP impl.memclkToMclkSample.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if rdySeq_to_mclkm1=rdySeq_to_mclkm2 then
				rdySeq_mclk <= rdySeq_to_mclkm2;
			end if;
			rdySeq_to_mclkm1 <= rdySeq_to_mclk;
			rdySeq_to_mclkm2 <= rdySeq_to_mclkm1;

			if dneSeq_to_mclkm1=dneSeq_to_mclkm2 then
				dneSeq_mclk <= dneSeq_to_mclkm2;
			end if;
			dneSeq_to_mclkm1 <= dneSeq_to_mclk;
			dneSeq_to_mclkm2 <= dneSeq_to_mclkm1;

			if TCapt_to_mclkm1=TCapt_to_mclkm2 then
				TCapt_mclk <= TCapt_to_mclkm2;
			end if;
			TCapt_to_mclkm1 <= TCapt_to_mclk;
			TCapt_to_mclkm2 <= TCapt_to_mclkm1;

			if ptr0Seqbuf_to_mclkm1=ptr0Seqbuf_to_mclkm2 then
				ptr0Seqbuf_mclk <= ptr0Seqbuf_to_mclkm2;
			end if;
			ptr0Seqbuf_to_mclkm1 <= ptr0Seqbuf_to_mclk;
			ptr0Seqbuf_to_mclkm2 <= ptr0Seqbuf_to_mclkm1;

			if start_to_mclkm1=start_to_mclkm2 then
				start_mclk <= start_to_mclkm2;
			end if;
			start_to_mclkm1 <= start_to_mclk;
			start_to_mclkm2 <= start_to_mclkm1;

			if stop_to_mclkm1=stop_to_mclkm2 then
				stop_mclk <= stop_to_mclkm2;
			end if;
			stop_to_mclkm1 <= stop_to_mclk;
			stop_to_mclkm2 <= stop_to_mclkm1;

			if ackSeqbufBToSeqClear_to_mclkm1=ackSeqbufBToSeqClear_to_mclkm2 then
				ackSeqbufBToSeqClear_mclk <= ackSeqbufBToSeqClear_to_mclkm2;
			end if;
			ackSeqbufBToSeqClear_to_mclkm1 <= ackSeqbufBToSeqClear_to_mclk;
			ackSeqbufBToSeqClear_to_mclkm2 <= ackSeqbufBToSeqClear_to_mclkm1;

		end if;
	end process;
	-- IP impl.memclkToMclkSample.rising --- END

	------------------------------------------------------------------------
	-- implementation: memclk to mclk CDC stretching (memclkToMclkStretch)
	------------------------------------------------------------------------

	-- IP impl.memclkToMclkStretch.wiring --- BEGIN
	-- IP impl.memclkToMclkStretch.wiring --- END

	-- IP impl.memclkToMclkStretch.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.memclkToMclkStretch.vars --- BEGIN
		constant imax: natural := 2;

		variable rdySeq_i: natural range 0 to imax;
		variable dneSeq_i: natural range 0 to imax;
		variable TCapt_i: natural range 0 to imax;
		variable ptr0Seqbuf_i: natural range 0 to imax;
		variable start_i: natural range 0 to imax;
		variable stop_i: natural range 0 to imax;
		variable ackSeqbufBToSeqClear_i: natural range 0 to imax;
		-- IP impl.memclkToMclkStretch.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.memclkToMclkStretch.asyncrst --- BEGIN
			rdySeq_to_mclk <= '0';
			dneSeq_to_mclk <= '0';
			TCapt_to_mclk <= (others => '0');
			ptr0Seqbuf_to_mclk <= 0;
			start_to_mclk <= '0';
			stop_to_mclk <= '0';
			ackSeqbufBToSeqClear_to_mclk <= '0';

			rdySeq_i := 0;
			dneSeq_i := 0;
			TCapt_i := 0;
			ptr0Seqbuf_i := 0;
			start_i := 0;
			stop_i := 0;
			ackSeqbufBToSeqClear_i := 0;
			-- IP impl.memclkToMclkStretch.asyncrst --- END
			-- IP impl.memclkToMclkStretch.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if rdySeq_i=imax then
				if rdySeq/=rdySeq_to_mclk then
					rdySeq_to_mclk <= rdySeq;
					rdySeq_i := 0;
				end if;
			else
				rdySeq_i := rdySeq_i + 1;
			end if;

			if dneSeq_i=imax then
				if dneSeq/=dneSeq_to_mclk then
					dneSeq_to_mclk <= dneSeq;
					dneSeq_i := 0;
				end if;
			else
				dneSeq_i := dneSeq_i + 1;
			end if;

			if TCapt_i=imax then
				if TCapt/=TCapt_to_mclk then
					TCapt_to_mclk <= TCapt;
					TCapt_i := 0;
				end if;
			else
				TCapt_i := TCapt_i + 1;
			end if;

			if ptr0Seqbuf_i=imax then
				if ptr0Seqbuf/=ptr0Seqbuf_to_mclk then
					ptr0Seqbuf_to_mclk <= ptr0Seqbuf;
					ptr0Seqbuf_i := 0;
				end if;
			else
				ptr0Seqbuf_i := ptr0Seqbuf_i + 1;
			end if;

			if start_i=imax then
				if start/=start_to_mclk then
					start_to_mclk <= start;
					start_i := 0;
				end if;
			else
				start_i := start_i + 1;
			end if;

			if stop_i=imax then
				if stop/=stop_to_mclk then
					stop_to_mclk <= stop;
					stop_i := 0;
				end if;
			else
				stop_i := stop_i + 1;
			end if;

			if ackSeqbufBToSeqClear_i=imax then
				if ackSeqbufBToSeqClear/=ackSeqbufBToSeqClear_to_mclk then
					ackSeqbufBToSeqClear_to_mclk <= ackSeqbufBToSeqClear;
					ackSeqbufBToSeqClear_i := 0;
				end if;
			else
				ackSeqbufBToSeqClear_i := ackSeqbufBToSeqClear_i + 1;
			end if;

		end if;
	end process;
	-- IP impl.memclkToMclkStretch.rising --- END

end Rtl;


-- file Render_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Render_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Render_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		resetMemclk: in std_logic;
		memclk: in std_logic;

		rndmemAXI_awaddr: out std_logic_vector(17 downto 0);
		rndmemAXI_awready: in std_logic;
		rndmemAXI_awvalid: out std_logic;
		rndmemAXI_wdata: out std_logic_vector(127 downto 0);
		rndmemAXI_wlast: out std_logic;
		rndmemAXI_wready: in std_logic;
		rndmemAXI_wvalid: out std_logic;

		reqToDdrifWr: out std_logic;
		ackToDdrifWr: in std_logic;

		rndmemAXI_araddr: out std_logic_vector(17 downto 0);
		rndmemAXI_arready: in std_logic;
		rndmemAXI_arvalid: out std_logic;
		rndmemAXI_rdata: in std_logic_vector(127 downto 0);
		rndmemAXI_rlast: in std_logic;
		rndmemAXI_rready: out std_logic;
		rndmemAXI_rresp: in std_logic_vector(1 downto 0);
		rndmemAXI_rvalid: in std_logic;

		reqToDdrifRd: out std_logic;
		ackToDdrifRd: in std_logic
	);
end Render_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Render_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_size16kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(11 downto 0);
			drdA: out std_logic_vector(31 downto 0);
			dwrA: in std_logic_vector(31 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(9 downto 0);
			drdB: out std_logic_vector(127 downto 0);
			dwrB: in std_logic_vector(127 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- DDR memory egress (egr)
	type stateEgr_t is (
		stateEgrInit,
		stateEgrCopyA, stateEgrCopyB, stateEgrCopyC
	);
	signal stateEgr: stateEgr_t;

	signal rndmemAXI_awaddr_sig: std_logic_vector(17 downto 0);

	-- IP sigs.egr.cust --- INSERT

	---- DDR memory ingress (igr)
	type stateIgr_t is (
		stateIgrInit,
		stateIgrCopyA, stateIgrCopyB
	);
	signal stateIgr: stateIgr_t;

	signal rndmemAXI_araddr_sig: std_logic_vector(17 downto 0);

	-- IP sigs.igr.cust --- INSERT

	---- main operation (op)
	type stateOp_t is (
		stateOpInit
	);
	signal stateOp: stateOp_t;

	signal enRowAbuf: std_logic;
	signal enRowBbuf: std_logic;
	signal weRowbuf: std_logic;
	signal aRowbuf: natural;
	signal aRowbuf_vec: std_logic_vector(11 downto 0);
	signal dwrRowbuf: std_logic_vector(31 downto 0);

	signal enRowAbufB: std_logic;
	signal enRowBbufB: std_logic;
	signal weRowbufB: std_logic;
	signal aRowbufB: natural;
	signal aRowbufB_vec: std_logic_vector(9 downto 0);
	signal dwrRowbufB: std_logic_vector(127 downto 0);

	-- IP sigs.op.cust --- INSERT

	---- myRowAbuf
	signal drdRowAbuf: std_logic_vector(31 downto 0);

	signal drdRowAbufB: std_logic_vector(127 downto 0);

	---- myRowBbuf
	signal drdRowBbuf: std_logic_vector(31 downto 0);

	signal drdRowBbufB: std_logic_vector(127 downto 0);

	---- other
	-- IP sigs.oth.cust --- IBEGIN
	signal egrAXIS_tdata: std_logic_vector(127 downto 0);
	signal egrAXIS_tvalid: std_logic;

	signal reqEgrToEgrstr: std_logic;
	signal ackEgrToEgrstr: std_logic;
	-- IP sigs.oth.cust --- IEND

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myRowAbuf : Dpbram_size16kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enRowAbuf,
			weA => weRowbuf,

			aA => aRowbuf_vec,
			drdA => drdRowAbuf,
			dwrA => dwrRowbuf,

			rstB => resetMemclk,
			clkB => memclk,

			enB => enRowAbufB,
			weB => weRowbufB,

			aB => aRowbufB_vec,
			drdB => drdRowAbufB,
			dwrB => dwrRowbufB
		);

	myRowBbuf : Dpbram_size16kB_a32b128_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enRowBbuf,
			weA => weRowbuf,

			aA => aRowbuf_vec,
			drdA => drdRowBbuf,
			dwrA => dwrRowbuf,

			rstB => resetMemclk,
			clkB => memclk,

			enB => enRowBbufB,
			weB => weRowbufB,

			aB => aRowbufB_vec,
			drdB => drdRowBbufB,
			dwrB => dwrRowbufB
		);

	------------------------------------------------------------------------
	-- implementation: DDR memory egress (egr)
	------------------------------------------------------------------------

	-- IP impl.egr.wiring --- BEGIN
	rndmemAXI_awaddr <= rndmemAXI_awaddr_sig;
	rndmemAXI_awvalid <= '1' when stateEgr=stateEgrCopyB else '0';

	rndmemAXI_wdata <= egrAXIS_tdata;
	rndmemAXI_wlast <= '0' when ((reqEgrToEgrstr='1' and ackEgrToEgrstr='0') or stateEgr=stateEgrCopyC) else '1';
	rndmemAXI_wvalid <= egrAXIS_tvalid;

	reqToDdrifWr <= '1' when stateEgr=stateEgrCopyB else '0';
	-- IP impl.egr.wiring --- END

	-- IP impl.egr.wiring.cust --- LINE

	-- IP impl.egr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.egr.vars --- BEGIN
		-- IP impl.egr.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.egr.asyncrst --- BEGIN
			stateEgr <= stateEgrInit;
			rndmemAXI_awaddr_sig <= (others => '0');

			-- IP impl.egr.asyncrst --- END
			-- IP impl.egr.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if stateEgr=stateEgrInit then
				-- IP impl.egr.syncrst --- BEGIN
				rndmemAXI_awaddr_sig <= (others => '0');

				stateEgr <= stateEgrCopyA;
				-- IP impl.egr.syncrst --- END
				-- IP impl.egr.syncrst.cust --- INSERT

			elsif stateEgr=stateEgrCopyA then
				-- IP impl.egr.copyA --- INSERT

			elsif stateEgr=stateEgrCopyB then
				-- IP impl.egr.copyB --- INSERT

			elsif stateEgr=stateEgrCopyC then
				-- IP impl.egr.copyC --- INSERT
			end if;
		end if;
	end process;
	-- IP impl.egr.rising --- END

	------------------------------------------------------------------------
	-- implementation: DDR memory ingress (igr)
	------------------------------------------------------------------------

	-- IP impl.igr.wiring --- BEGIN
	rndmemAXI_araddr <= rndmemAXI_araddr_sig;
	rndmemAXI_arvalid <= '1' when stateIgr=stateIgrCopyB else '0';

	reqToDdrifRd <= '1' when stateIgr=stateIgrCopyB else '0';
	-- IP impl.igr.wiring --- END

	-- IP impl.igr.wiring.cust --- LINE

	-- IP impl.igr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.igr.vars --- BEGIN
		-- IP impl.igr.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.igr.asyncrst --- BEGIN
			stateIgr <= stateIgrInit;
			rndmemAXI_araddr_sig <= (others => '0');

			-- IP impl.igr.asyncrst --- END
			-- IP impl.igr.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if stateIgr=stateIgrInit then
				-- IP impl.igr.syncrst --- BEGIN
				rndmemAXI_araddr_sig <= (others => '0');

				stateIgr <= stateIgrCopyA;
				-- IP impl.igr.syncrst --- END
				-- IP impl.igr.syncrst.cust --- INSERT

			elsif stateIgr=stateIgrCopyA then
				-- IP impl.igr.copyA --- INSERT

			elsif stateIgr=stateIgrCopyB then
				-- IP impl.igr.copyB --- INSERT
			end if;
		end if;
	end process;
	-- IP impl.igr.rising --- END

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- LINE

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- BEGIN
		-- IP impl.op.vars --- END

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- BEGIN
			stateOp <= stateOpInit;
			enRowAbuf <= '0';
			enRowBbuf <= '0';
			weRowbuf <= '0';
			aRowbuf <= 0;
			aRowbuf_vec <= (others => '0');
			dwrRowbuf <= (others => '0');
			enRowAbufB <= '0';
			enRowBbufB <= '0';
			weRowbufB <= '0';
			aRowbufB <= 0;
			aRowbufB_vec <= (others => '0');
			dwrRowbufB <= (others => '0');

			-- IP impl.op.asyncrst --- END
			-- IP impl.op.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if stateOp=stateOpInit then
				-- IP impl.op.syncrst --- BEGIN
				enRowAbuf <= '0';
				enRowBbuf <= '0';
				weRowbuf <= '0';
				aRowbuf <= 0;
				aRowbuf_vec <= (others => '0');
				dwrRowbuf <= (others => '0');
				enRowAbufB <= '0';
				enRowBbufB <= '0';
				weRowbufB <= '0';
				aRowbufB <= 0;
				aRowbufB_vec <= (others => '0');
				dwrRowbufB <= (others => '0');

				-- IP impl.op.syncrst --- END
				-- IP impl.op.syncrst.cust --- INSERT

			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;


-- file Rgbled_v1_0_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Rgbled_v1_0_8c100ea18901433eb4f7c0fdbf115e06 module implementation
-- copyright: (C) 2022 MPSI Technologies GmbH
-- author: Alexander Wirthmueller
-- date created: 25 Dec 2022
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Rgbled_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
	generic (
		fMclk: natural := 50000 -- in kHz
	);
	port (
		reset: in std_logic;

		mclk: in std_logic;

		rgb: in std_logic_vector(23 downto 0);

		r: out std_logic;
		g: out std_logic;
		b: out std_logic
	);
end Rgbled_v1_0_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Rgbled_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- blue LED PWM (blue)
	type stateBlue_t is (
		stateBlueOff,
		stateBlueOn
	);
	signal stateBlue: stateBlue_t;

	---- green LED PWM (green)
	type stateGreen_t is (
		stateGreenOff,
		stateGreenOn
	);
	signal stateGreen: stateGreen_t;

	---- red LED PWM (red)
	type stateRed_t is (
		stateRedOff,
		stateRedOn
	);
	signal stateRed: stateRed_t;

begin

	------------------------------------------------------------------------
	-- implementation: blue LED PWM (blue)
	------------------------------------------------------------------------

	b <= '1' when stateBlue=stateBlueOn else '0';

	process (reset, mclk, stateBlue)
		variable i: natural range 0 to 256;
		
		constant jmax: natural := fMclk/50; -- 50kHz base clock resulting in 195Hz PWM clock
		variable j: natural range 0 to jmax;

	begin
		if reset='1' then
			stateBlue <= stateBlueOff;
			
			i := 0;
			j := 0;

		elsif rising_edge(mclk) then
			j := j + 1;
			
			if j=jmax then
				j := 0;
				i := i + 1;
			end if;

			if stateBlue=stateBlueOff then
				if j=0 then
					if i=256 then
						i := 0;

						if rgb(7 downto 0)/=x"00" then
							stateBlue <= stateBlueOn;
						end if;
					end if;
				end if;

			elsif stateBlue=stateBlueOn then
				if j=0 then
					if i=256 then
						i := 0;
					elsif i >= to_integer(unsigned(rgb(7 downto 0))) then
						stateBlue <= stateBlueOff;
					end if;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: green LED PWM (green)
	------------------------------------------------------------------------

	g <= '1' when stateGreen=stateGreenOn else '0';

	process (reset, mclk, stateGreen)
		variable i: natural range 0 to 256;
		
		constant jmax: natural := fMclk/50;
		variable j: natural range 0 to jmax;

	begin
		if reset='1' then
			stateGreen <= stateGreenOff;
			
			i := 0;
			j := 0;

		elsif rising_edge(mclk) then
			j := j + 1;
			
			if j=jmax then
				j := 0;
				i := i + 1;
			end if;

			if stateGreen=stateGreenOff then
				if j=0 then
					if i=256 then
						i := 0;

						if rgb(15 downto 8)/=x"00" then
							stateGreen <= stateGreenOn;
						end if;
					end if;
				end if;

			elsif stateGreen=stateGreenOn then
				if j=0 then
					if i=256 then
						i := 0;
					elsif i >= to_integer(unsigned(rgb(15 downto 8))) then
						stateGreen <= stateGreenOff;
					end if;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: red LED PWM (red)
	------------------------------------------------------------------------

	r <= '1' when stateRed=stateRedOn else '0';

	process (reset, mclk, stateRed)
		variable i: natural range 0 to 256;
		
		constant jmax: natural := fMclk/50;
		variable j: natural range 0 to jmax;

	begin
		if reset='1' then
			stateRed <= stateRedOff;
			
			i := 0;
			j := 0;

		elsif rising_edge(mclk) then
			j := j + 1;
			
			if j=jmax then
				j := 0;
				i := i + 1;
			end if;

			if stateRed=stateRedOff then
				if j=0 then
					if i=256 then
						i := 0;

						if rgb(23 downto 16)/=x"00" then
							stateRed <= stateRedOn;
						end if;
					end if;
				end if;

			elsif stateRed=stateRedOn then
				if j=0 then
					if i=256 then
						i := 0;
					elsif i >= to_integer(unsigned(rgb(23 downto 16))) then
						stateRed <= stateRedOff;
					end if;
				end if;
			end if;
		end if;
	end process;

end Rtl;


-- file Rotary_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Rotary_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Rotary_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;
		tkclk: in std_logic;

		toStepmuxNslp: out std_logic;
		toStepmuxM0: out std_logic;
		toStepmuxM0z: out std_logic;
		toStepmuxM1: out std_logic;
		toStepmuxDir: out std_logic;
		toStepmuxStep: out std_logic;

		reqInvConfig: in std_logic;
		ackInvConfig: out std_logic;

		configTixVStepmode: in std_logic_vector(7 downto 0);
		configTStep: in std_logic_vector(7 downto 0);

		getInfoTixVState: out std_logic_vector(7 downto 0);
		getInfoAngle: out std_logic_vector(15 downto 0);

		reqInvMoveto: in std_logic;
		ackInvMoveto: out std_logic;

		movetoAngle: in std_logic_vector(15 downto 0);

		reqInvSet: in std_logic;
		ackInvSet: out std_logic;

		setRng: in std_logic_vector(7 downto 0);
		setCcwNotCw: in std_logic_vector(7 downto 0);

		reqInvZero: in std_logic;
		ackInvZero: out std_logic
	);
end Rotary_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Rotary_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant tixVStateIdle: std_logic_vector(7 downto 0) := x"00";
	constant tixVStateMove: std_logic_vector(7 downto 0) := x"01";

	constant tixVStepmodeFull: std_logic_vector(7 downto 0) := x"00";
	constant tixVStepmodeHalf: std_logic_vector(7 downto 0) := x"01";
	constant tixVStepmodeQuarter: std_logic_vector(7 downto 0) := x"02";

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv,
		stateOpRunA, stateOpRunB
	);
	signal stateOp: stateOp_t;

	signal ackInvConfig_sig: std_logic;
	signal ackInvMoveto_sig: std_logic;
	signal ackInvSet_sig: std_logic;
	signal ackInvZero_sig: std_logic;
	signal tixVStepmode: std_logic_vector(7 downto 0);
	signal TStep: natural range 0 to 255; -- should be > 15 ms full cycle or 75
	signal rng: std_logic;
	signal angle: unsigned(13 downto 0);
	signal ccwNotCw: std_logic;
	signal step: std_logic;

	signal m0: std_logic;
	signal m0z: std_logic;
	signal m1: std_logic;

	-- IP sigs.op.cust --- INSERT

	---- other
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	ackInvConfig <= ackInvConfig_sig;
	ackInvMoveto <= ackInvMoveto_sig;
	ackInvSet <= ackInvSet_sig;
	ackInvZero <= ackInvZero_sig;
	toStepmuxNslp <= '1';
	toStepmuxDir <= ccwNotCw;
	toStepmuxStep <= step;

	m0 <= '1' when tixVStepmode=tixVStepmodeHalf else '0';
	toStepmuxM0 <= m0;
	m0z <= '1' when tixVStepmode=tixVStepmodeQuarter else '0';
	toStepmuxM0z <= m0z;
	m1 <= '0';
	toStepmuxM1 <= m1;
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- RBEGIN
	getInfoTixVState <= tixVStateMove when stateOp=stateOpRunA or stateOp=StateOpRunB else tixVStateIdle;
	getInfoAngle <= "00" & std_logic_vector(angle);
	-- IP impl.op.wiring.cust --- REND

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- RBEGIN
		constant anglemax: natural := 15999;
		constant anglemax_vec: unsigned(13 downto 0) := "11111001111111";

		variable lsb: natural range 0 to 2;

		variable target: unsigned(13 downto 0);
		variable dAngle: integer range -anglemax to anglemax;

		variable targetNotSteady: boolean;
		variable atTarget: boolean;

		variable i: natural range 0 to 255;
		-- IP impl.op.vars --- REND

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- BEGIN
			stateOp <= stateOpInit;
			ackInvConfig_sig <= '0';
			ackInvMoveto_sig <= '0';
			ackInvSet_sig <= '0';
			ackInvZero_sig <= '0';
			tixVStepmode <= tixVStepmodeFull;
			TStep <= 75;
			rng <= '0';
			angle <= (others => '0');
			ccwNotCw <= '0';
			step <= '0';

			-- IP impl.op.asyncrst --- END
			-- IP impl.op.asyncrst.cust --- IBEGIN
			lsb := 2;
			target := (others => '0');
			dAngle := 0;
			targetNotSteady := false;
			atTarget := false;
			i := 0;
			-- IP impl.op.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			if (stateOp=stateOpInit or (stateOp/=stateOpInv and (reqInvConfig='1' or reqInvMoveto='1' or reqInvSet='1' or reqInvZero='1'))) then
				-- IP impl.op.syncrst --- RBEGIN
				step <= '0';
				-- IP impl.op.syncrst --- REND
				-- IP impl.op.syncrst.cust --- IBEGIN
				i := 0;
				-- IP impl.op.syncrst.cust --- IEND

				if reqInvConfig='1' then
					-- IP impl.op.init.invConfig --- IBEGIN
					tixVStepmode <= configTixVStepmode;
					case configTixVStepmode is
						when tixVStepmodeFull =>
							lsb := 2;
						when tixVStepmodeHalf =>
							lsb := 1;
						when others =>
							lsb := 0;
					end case;

					TStep <= to_integer(unsigned(configTStep));

					ackInvConfig_sig <= '1';
					ackInvMoveto_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvZero_sig <= '0';
					-- IP impl.op.init.invConfig --- IEND

					stateOp <= stateOpInv;

				elsif reqInvMoveto='1' then
					-- IP impl.op.init.invMoveto --- IBEGIN
					targetNotSteady := true;

					-- determine shortest path
					target := unsigned(movetoAngle(13 downto 0));
					dAngle := to_integer(target) - to_integer(angle);

					if dAngle > anglemax/2 then
						-- dAngle := dAngle - anglemax - 1; -- will become negative
						ccwNotCw <= '1';
					elsif dAngle < -anglemax/2 then
						--dAngle := dAngle + anglemax + 1; -- will become positive
						ccwNotCw <= '0';
					elsif dAngle > 0 then
						ccwNotCw <= '0';
					else
						ccwNotCw <= '1';
					end if;

					ackInvConfig_sig <= '0';
					ackInvMoveto_sig <= '1';
					ackInvSet_sig <= '0';
					ackInvZero_sig <= '0';
					-- IP impl.op.init.invMoveto --- IEND

					stateOp <= stateOpInv;

				elsif reqInvSet='1' then
					-- IP impl.op.init.invSet --- IBEGIN
					targetNotSteady := false;

					if setRng=tru8 then
						rng <= '1';
					else
						rng <= '0';
					end if;
					if setCcwNotCw=tru8 then
						ccwNotCw <= '1';
					else
						ccwNotCw <= '0';
					end if;

					ackInvConfig_sig <= '0';
					ackInvMoveto_sig <= '0';
					ackInvSet_sig <= '1';
					ackInvZero_sig <= '0';
					-- IP impl.op.init.invSet --- IEND

					stateOp <= stateOpInv;

				elsif reqInvZero='1' then
					-- IP impl.op.init.invZero --- IBEGIN
					angle <= (others => '0');

					ackInvConfig_sig <= '0';
					ackInvMoveto_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvZero_sig <= '1';
					-- IP impl.op.init.invZero --- IEND

					stateOp <= stateOpInv;

				else
					-- IP impl.op.init.start --- IBEGIN
					ackInvConfig_sig <= '0';
					ackInvMoveto_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvZero_sig <= '0';

					atTarget := (angle(13 downto lsb) = target(13 downto lsb));
					-- IP impl.op.init.start --- IEND

					if TStep/=0 and ((not targetNotSteady and rng='1') or (targetNotSteady and not atTarget)) then
						stateOp <= stateOpRunB;

					else
						stateOp <= stateOpInit;
					end if;
				end if;

			elsif stateOp=stateOpInv then
				if ((reqInvConfig='0' and ackInvConfig_sig='1') or (reqInvMoveto='0' and ackInvMoveto_sig='1') or (reqInvSet='0' and ackInvSet_sig='1') or (reqInvZero='0' and ackInvZero_sig='1')) then
					-- IP impl.op.inv.reset --- IBEGIN
					ackInvConfig_sig <= '0';
					ackInvMoveto_sig <= '0';
					ackInvSet_sig <= '0';
					ackInvZero_sig <= '0';
					-- IP impl.op.inv.reset --- IEND

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpRunA then
				if tkclk='1' then
					-- IP impl.op.runA --- IBEGIN
					if i=TStep then
						i := 0;

						if ccwNotCw='0' then
							if angle(13 downto lsb)=anglemax_vec(13 downto lsb) then
								angle(13 downto lsb) <= (others => '0');
							else
								angle(13 downto lsb) <= angle(13 downto lsb) + 1;
							end if;
						else
							if angle(13 downto lsb)=0 then
								angle(13 downto lsb) <= anglemax_vec(13 downto lsb);
							else
								angle(13 downto lsb) <= angle(13 downto lsb) - 1;
							end if;
						end if;
						
						step <= not step;
					end if;
					-- IP impl.op.runA --- IEND

					stateOp <= stateOpRunB;
				end if;

			elsif stateOp=stateOpRunB then
				if tkclk='0' then
					-- IP impl.op.runB --- IBEGIN
					i := i + 1;

					atTarget := (angle(13 downto lsb) = target(13 downto lsb));
					-- IP impl.op.runB --- IEND

					if targetNotSteady and atTarget then
						stateOp <= stateOpInit;

					else
						stateOp <= stateOpRunA;
					end if;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;


-- file Spimaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Spimaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06 module implementation
-- copyright: (C) 2016-2017 MPSI Technologies GmbH
-- author: Alexander Wirthmueller
-- date created: 17 May 2016
-- date modified: 28 Jan 2017
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Spimaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
	generic (
		fMclk: natural := 50000; -- in kHz
	
		cpol: std_logic := '0';
		cpha: std_logic := '0';

		nssByteNotXfer: std_logic := '0';

		fSclk: natural range 100 to 50000000 := 2000000;
		NStop: natural range 1 to 8 := 1
	);
	port (
		reset: in std_logic;

		mclk: in std_logic;

		req: in std_logic;
		ack: out std_logic;
		dne: out std_logic;

		len: in std_logic_vector(16 downto 0);

		send: in std_logic_vector(7 downto 0);
		strbSend: out std_logic;

		recv: out std_logic_vector(7 downto 0);
		strbRecv: out std_logic;

		nss: out std_logic;
		sclk: out std_logic;
		mosi: out std_logic;
		miso: in std_logic
	);
end Spimaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Spimaster_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	-- transfer operation (xfer)
	type stateXfer_t is (
		stateXferInit,
		stateXferIdle,
		stateXferLoad,
		stateXferDataA, stateXferDataB,
		stateXferStore,
		stateXferStop,
		stateXferDone
	);
	signal stateXfer: stateXfer_t;

	signal sclk_sig: std_logic;
	signal mosi_sig: std_logic;
	
	signal recv_sig: std_logic_vector(7 downto 0);

begin

	------------------------------------------------------------------------
	-- implementation: transfer operation (xfer)
	------------------------------------------------------------------------

	sclk_sig <= '1' when stateXfer=stateXferDataB else '0';

	nss <= '0' when (stateXfer=stateXferLoad or stateXfer=stateXferDataA or stateXfer=stateXferDataB or stateXfer=stateXferStore or (nssByteNotXfer='0' and stateXfer=stateXferStop)) else '1';

	sclk <= sclk_sig when cpol='0' else not sclk_sig;

	mosi <= mosi_sig;
	
	ack <= '1' when (stateXfer=stateXferLoad or stateXfer=stateXferDataA or stateXfer=stateXferDataB or stateXfer=stateXferStore or stateXfer=stateXferStop
				or stateXfer=stateXferDone) else '0';

	dne <= '1' when stateXfer=stateXferDone else '0';

	strbSend <= '0' when (stateXfer=stateXferDataA or stateXfer=stateXferDataB or stateXfer=stateXferStore or stateXfer=stateXferStop) else '1';

	recv <= recv_sig;
	
	strbRecv <= '0' when (stateXfer=stateXferLoad or stateXfer=stateXferDataA or stateXfer=stateXferDataB or stateXfer=stateXferStore) else '1';

	process (reset, mclk, stateXfer)
		variable send_var: std_logic_vector(7 downto 0);

		variable recvraw: std_logic_vector(7 downto 0);
		
		variable bitcnt: natural range 0 to 7;
		variable bytecnt: natural range 0 to 65536;

		variable i: natural range 0 to (1000*fMclk)/fSclk;
		variable j: natural range 0 to NStop;

	begin
		if reset='1' then
			stateXfer <= stateXferInit;
			mosi_sig <= '0';
			recv_sig <= x"00";

		elsif rising_edge(mclk) then
			if stateXfer=stateXferInit then
				mosi_sig <= '0';
				recv_sig <= x"00";
				
				bytecnt := 0;

				stateXfer <= stateXferIdle;

			elsif stateXfer=stateXferIdle then
				if req='1' then
					if to_integer(unsigned(len))=0 then
						stateXfer <= stateXferDone;
					else
						stateXfer <= stateXferLoad;
					end if;
				end if;

			elsif stateXfer=stateXferLoad then
				if req='0' then
					stateXfer <= stateXferInit;

				else
					send_var := send;
						
					recvraw := x"00";

					bitcnt := 0;
					bytecnt := bytecnt + 1; -- byte count put out for send

					if cpha='0' then
						mosi_sig <= send_var(7-bitcnt);
					end if;

					i := 0;

					stateXfer <= stateXferDataA;
				end if;

			elsif stateXfer=stateXferDataA then -- sclk='0'
				i := i + 1;

				if i=((1000*fMclk)/fSclk)/2 then
					if cpha='0' then
						recvraw(7-bitcnt) := miso;
					elsif cpha='1' then
						mosi_sig <= send_var(7-bitcnt);
					end if;

					i := 0;

					stateXfer <= stateXferDataB;
				end if;

			elsif stateXfer=stateXferDataB then -- sclk='1'
				i := i + 1;

				if i=((1000*fMclk)/fSclk)/2 then
					i := 0;

					if cpha='1' then
						recvraw(7-bitcnt) := miso;
					end if;
					
					if bitcnt=7 then
						recv_sig <= recvraw;

						j := 0;
						
						stateXfer <= stateXferStore;

					else	
						bitcnt := bitcnt + 1;

						if cpha='0' then
							mosi_sig <= send_var(7-bitcnt);
						end if;
						
						stateXfer <= stateXferDataA;
					end if;
				end if;

			elsif stateXfer=stateXferStore then
				i := i + 1;
				stateXfer <= stateXferStop;
				
			elsif stateXfer=stateXferStop then
				i := i + 1;
				if i=(1000*fMclk)/fSclk then
					i := 0;

					j := j + 1;

					if j=NStop then
						if bytecnt=to_integer(unsigned(len)) then
							stateXfer <= stateXferDone;
						else
							stateXfer <= stateXferLoad;
						end if;
					end if;
				end if;

			elsif stateXfer=stateXferDone then
				if req='0' then
					stateXfer <= stateXferInit;
				end if;
			end if;
		end if;
	end process;

end Rtl;


-- file Spram_v1_0_size2kB_w8_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Spram_v1_0_size2kB_w8_8c100ea18901433eb4f7c0fdbf115e06 spram_efnx_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 31 Aug 2025
-- IP header --- ABOVE

-- module parameters:
-- size (size [kB]): 2
-- w (width [bit]): 8

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library efxphysicallib;
use efxphysicallib.efxcomponents.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Spram_v1_0_size2kB_w8_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		clk: in std_logic;

		en: in std_logic;
		we: in std_logic;

		a: in std_logic_vector(10 downto 0);
		drd: out std_logic_vector(7 downto 0);
		dwr: in std_logic_vector(7 downto 0)
	);
end Spram_v1_0_size2kB_w8_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Spram_v1_0_size2kB_w8_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- multiplexing (mux)

	signal enm1: std_logic;
	signal am1: std_logic_vector(10 downto 0);

	signal en_i0: std_logic;
	signal RE_i0: std_logic;
	signal WE_i0: std_logic_vector(1 downto 0);
	signal en_i0m1: std_logic;

	signal en_i1: std_logic;
	signal RE_i1: std_logic;
	signal WE_i1: std_logic_vector(1 downto 0);
	signal en_i1m1: std_logic;

	-- IP sigs.mux.cust --- INSERT

	---- myRam_i0j0
	signal drd_i0j0: std_logic_vector(7 downto 0);

	---- myRam_i1j0
	signal drd_i1j0: std_logic_vector(7 downto 0);

	---- other
	signal drd_i0: std_logic_vector(7 downto 0);
	signal drd_i1: std_logic_vector(7 downto 0);
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myRam_i0j0 : EFX_RAM10
		generic map (
			READ_WIDTH => 8,
			WRITE_WIDTH => 8,

			RST_POLARITY => 1,
			RCLK_POLARITY => 1,
			RE_POLARITY => 1,
			RADDREN_POLARITY => 1,
			WCLK_POLARITY => 1,
			WCLKE_POLARITY => 1,
			WE_POLARITY => "11",
			WADDREN_POLARITY => 1,

			WRITE_MODE => "READ_FIRST",
			RESET_RAM => "ASYNC",
			RESET_OUTREG => "ASYNC",

			INIT_0 => x"000114010009EB300005EB3000FF0B3000FF0A30000CEB300005EB3000000001",
			INIT_1 => x"0001640100786301000D6201005961010004600100002B0100182A0100002801",
			INIT_2 => x"00076C0100906B0100086A01000F69010001680100776701000B660100586501",
			INIT_3 => x"000A8C010000750100007401000171010001700100386F0100046E0100806D01",
			INIT_4 => x"000A0903006007030000060300030503000304030001030300050103000A8D01",
			INIT_5 => x"0040570100720D0300000C0300010B03000A090300720D0300000C0300010B03",
			INIT_6 => x"00545B0100045A0100786301000D620100E36101000660010000590100025801",
			INIT_7 => x"00F09A0100F09901000098010000950100009401000193010000910100019001",
			INIT_8 => x"000CA2010000A1010008A00100009F0100089E0100009D01000A9C0100009B01",
			INIT_9 => x"0000000000000000000000000000000000000000000000000000000000000000",
			INIT_A => (others => '0'),
			INIT_B => (others => '0'),
			INIT_C => (others => '0'),
			INIT_D => (others => '0'),
			INIT_E => (others => '0'),
			INIT_F => (others => '0'),
			INIT_10 => (others => '0'),
			INIT_11 => (others => '0'),
			INIT_12 => (others => '0'),
			INIT_13 => (others => '0'),
			INIT_14 => (others => '0'),
			INIT_15 => (others => '0'),
			INIT_16 => (others => '0'),
			INIT_17 => (others => '0'),
			INIT_18 => (others => '0'),
			INIT_19 => (others => '0'),
			INIT_1A => (others => '0'),
			INIT_1B => (others => '0'),
			INIT_1C => (others => '0'),
			INIT_1D => (others => '0'),
			INIT_1E => (others => '0'),
			INIT_1F => (others => '0'),
			INIT_20 => (others => '0'),
			INIT_21 => (others => '0'),
			INIT_22 => (others => '0'),
			INIT_23 => (others => '0'),
			INIT_24 => (others => '0'),
			INIT_25 => (others => '0'),
			INIT_26 => (others => '0'),
			INIT_27 => (others => '0')
		)
		port map (
			RST => reset,
			RCLK => clk,
			RE => RE_i0,

			RADDR => a(9 downto 0),
			RADDREN => '1',

			RDATA => drd_i0j0,

			WCLK => clk,
			WCLKE => '1',

			WE => WE_i0,

			WADDR => a(9 downto 0),
			WADDREN => '1',

			WDATA => dwr(7 downto 0)
		);

	myRam_i1j0 : EFX_RAM10
		generic map (
			READ_WIDTH => 8,
			WRITE_WIDTH => 8,

			RST_POLARITY => 1,
			RCLK_POLARITY => 1,
			RE_POLARITY => 1,
			RADDREN_POLARITY => 1,
			WCLK_POLARITY => 1,
			WCLKE_POLARITY => 1,
			WE_POLARITY => "11",
			WADDREN_POLARITY => 1,

			WRITE_MODE => "READ_FIRST",
			RESET_RAM => "ASYNC",
			RESET_OUTREG => "ASYNC",

			INIT_0 => x"008F183A0003013A00019D3100001D3400471C34000150300001023000010030",
			INIT_1 => x"007F263A004F243A0087223A004F203A00011F3A00371E3A00471C3A004F1A3A",
			INIT_2 => x"00302C30000235300026343000003230001131300094303000001830003F283A",
			INIT_3 => x"005876300000753000B074300097573000AC5630000A2F3000382E3000002D30",
			INIT_4 => x"00840C300010D930004CD8300000CF300000CE300000C7300000C630000F7730",
			INIT_5 => x"002188320000A13100019E31007F6A31008F683100035A3100B04C31005D0D30",
			INIT_6 => x"00317C360001783600044C3600044A3600014836001816340005143400028A32",
			INIT_7 => x"003D1C3700031737000116370002153700021437000308370010063700317E36",
			INIT_8 => x"00083237000031370089303700002F3700462E3700002D3700002C37003F1D37",
			INIT_9 => x"0001603700115F3700005E3700005D37000240370005353700FE343700013337",
			INIT_A => x"00007637000F6E3700176D37001A6C37001B6B37001B6A37001B6937001B6837",
			INIT_B => x"00237E3700017D3700087C3700007B3700897A37000079370046783700007737",
			INIT_C => x"00D98A37000F883700A584370006833700F582370003813700D9803700027F37",
			INIT_D => x"007A94370043923700F5903700068F3700878E3700058D3700EB8C3700038B37",
			INIT_E => x"00000000000000000000000000000000000000300001003A0036B03700A19637",
			INIT_F => (others => '0'),
			INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000230",
			INIT_11 => (others => '0'),
			INIT_12 => (others => '0'),
			INIT_13 => (others => '0'),
			INIT_14 => (others => '0'),
			INIT_15 => (others => '0'),
			INIT_16 => (others => '0'),
			INIT_17 => (others => '0'),
			INIT_18 => (others => '0'),
			INIT_19 => (others => '0'),
			INIT_1A => (others => '0'),
			INIT_1B => (others => '0'),
			INIT_1C => (others => '0'),
			INIT_1D => (others => '0'),
			INIT_1E => (others => '0'),
			INIT_1F => (others => '0'),
			INIT_20 => (others => '0'),
			INIT_21 => (others => '0'),
			INIT_22 => (others => '0'),
			INIT_23 => (others => '0'),
			INIT_24 => (others => '0'),
			INIT_25 => (others => '0'),
			INIT_26 => (others => '0'),
			INIT_27 => (others => '0')
		)
		port map (
			RST => reset,
			RCLK => clk,
			RE => RE_i1,

			RADDR => a(9 downto 0),
			RADDREN => '1',

			RDATA => drd_i1j0,

			WCLK => clk,
			WCLKE => '1',

			WE => WE_i1,

			WADDR => a(9 downto 0),
			WADDREN => '1',

			WDATA => dwr(7 downto 0)
		);

	------------------------------------------------------------------------
	-- implementation: multiplexing (mux)
	------------------------------------------------------------------------

	-- IP impl.mux.wiring --- BEGIN
	en_i0 <= '1' when (en='1' and a(10 downto 10)="0") else '0';
	RE_i0 <= '1' when (en_i0='1' and we='0') else '0';
	WE_i0 <= "11" when (en_i0='1' and we='1') else "00";
	en_i0m1 <= '1' when (enm1='1' and am1(10 downto 10)="0") else '0';

	en_i1 <= '1' when (en='1' and a(10 downto 10)="1") else '0';
	RE_i1 <= '1' when (en_i1='1' and we='0') else '0';
	WE_i1 <= "11" when (en_i1='1' and we='1') else "00";
	en_i1m1 <= '1' when (enm1='1' and am1(10 downto 10)="1") else '0';
	-- IP impl.mux.wiring --- END

	-- IP impl.mux.wiring.cust --- LINE

	-- IP impl.mux.rising --- BEGIN
	process (reset, clk)
		-- IP impl.mux.vars --- BEGIN
		-- IP impl.mux.vars --- END

	begin
		if reset='1' then
			-- IP impl.mux.asyncrst --- BEGIN
			enm1 <= '0';
			am1 <= (others => '0');

			-- IP impl.mux.asyncrst --- END
			-- IP impl.mux.asyncrst.cust --- INSERT

		elsif rising_edge(clk) then
			enm1 <= en;
			am1 <= a;
		end if;
	end process;
	-- IP impl.mux.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	drd_i0 <= drd_i0j0;
	drd_i1 <= drd_i1j0;

	drd <= drd_i0 when en_i0m1='1'
				else drd_i1 when en_i1m1='1'
				else (others => '0');

end Rtl;


-- file State_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- State_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity State_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;
		tkclk: in std_logic;
		commok: in std_logic;
		rng: in std_logic;
		rgb: out std_logic_vector(23 downto 0)
	);
end State_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of State_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant rgbWhite: std_logic_vector(23 downto 0) := x"555555";
	constant rgbRed: std_logic_vector(23 downto 0) := x"FF0000";
	constant rgbOrange: std_logic_vector(23 downto 0) := x"7F7F00";

	constant rgbGreen: std_logic_vector(23 downto 0) := x"00FF00";
	constant rgbGreenD1: std_logic_vector(23 downto 0) := x"00D000";
	constant rgbGreenD2: std_logic_vector(23 downto 0) := x"00A000";
	constant rgbGreenD3: std_logic_vector(23 downto 0) := x"007000";
	constant rgbGreenD4: std_logic_vector(23 downto 0) := x"004000";

	constant rgbBluegreen: std_logic_vector(23 downto 0) := x"007F7F";
	constant rgbBlue: std_logic_vector(23 downto 0) := x"0000FF";
	constant rgbPink: std_logic_vector(23 downto 0) := x"7F007F";

	---- RGB LED control (led)
	type stateLed_t is (
		stateLedRunA, stateLedRunB
	);
	signal stateLed: stateLed_t;

	constant sizeSeq: natural := 5;
	type seq_t is array (0 to sizeSeq-1) of std_logic_vector(23 downto 0);
	signal seq: seq_t;
	signal ixSeq: natural range 0 to sizeSeq-1;

	-- IP sigs.led.cust --- INSERT

	---- other
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- implementation: RGB LED control (led)
	------------------------------------------------------------------------

	-- IP impl.led.wiring --- BEGIN
	-- IP impl.led.wiring --- END

	-- IP impl.led.wiring.cust --- RBEGIN
	rgb <= seq(ixSeq);
	-- IP impl.led.wiring.cust --- REND

	-- IP impl.led.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.led.vars --- RBEGIN
		variable rgb_lcl: std_logic_vector(23 downto 0);

		constant imax: natural := 2000; -- 200ms slice time
		variable i: natural range 0 to imax;
		-- IP impl.led.vars --- REND

	begin
		if reset='1' then
			-- IP impl.led.asyncrst --- BEGIN
			stateLed <= stateLedRunA;
			ixSeq <= 0;

			-- IP impl.led.asyncrst --- END
			-- IP impl.led.asyncrst.cust --- IBEGIN
			seq <= (others => (others => '0'));

			rgb_lcl := (others => '0');
			i := 0;
			-- IP impl.led.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			if stateLed=stateLedRunA then
				if tkclk='1' then
					-- IP impl.led.runA --- IBEGIN
					if i=imax then
						i := 0;

						if ixSeq=sizeSeq-1 then
							ixSeq <= 0;

							if commok='0' then
								seq <= (rgbRed, x"000000", x"000000", x"000000", x"000000");

							elsif rng='1' then
								rgb_lcl := rgbBlue;
	
								for j in 0 to sizeSeq-1 loop
									seq(j) <= rgb_lcl;
								end loop;

							else
								seq(0) <= rgbGreenD4;
								seq(1) <= rgbGreenD3;
								seq(2) <= rgbGreenD2;
								seq(3) <= rgbGreenD1;
								seq(4) <= rgbGreen;
							end if;

						else
							ixSeq <= ixSeq + 1;
						end if;
					end if;
					-- IP impl.led.runA --- IEND

					stateLed <= stateLedRunB;
				end if;

			elsif stateLed=stateLedRunB then
				if tkclk='0' then
					i := i + 1; -- IP impl.led.runB --- ILINE

					stateLed <= stateLedRunA;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.led.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;


-- file Stepmux_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Stepmux_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Stepmux_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		fromLinearNslp: in std_logic;
		fromLinearM0: in std_logic;
		fromLinearM0z: in std_logic;
		fromLinearM1: in std_logic;
		fromLinearDir: in std_logic;
		fromLinearStep: in std_logic;

		fromRotaryNslp: in std_logic;
		fromRotaryM0: in std_logic;
		fromRotaryM0z: in std_logic;
		fromRotaryM1: in std_logic;
		fromRotaryDir: in std_logic;
		fromRotaryStep: in std_logic;

		reqInvSet: in std_logic;
		ackInvSet: out std_logic;

		setLinNotRot: in std_logic_vector(7 downto 0);

		nslp: out std_logic;
		dir: out std_logic;
		step: out std_logic;

		m0: out std_logic;
		m0z: out std_logic;

		m1: out std_logic;
		m1z: out std_logic
	);
end Stepmux_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Stepmux_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv
	);
	signal stateOp: stateOp_t;

	signal linNotRot: std_logic;

	-- IP sigs.op.cust --- INSERT

	---- other
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	ackInvSet <= '1' when stateOp=stateOpInv else '0';
	nslp <= fromLinearNslp when linNotRot='1' else fromRotaryNslp;

	m0 <= fromLinearM0 when linNotRot='1' else fromRotaryM0;
	m0z <= fromLinearM0z when linNotRot='1' else fromRotaryM0z;

	m1 <= fromLinearM1 when linNotRot='1' else fromRotaryM1;
	m1z <= '0';

	dir <= fromLinearDir when linNotRot='1' else fromRotaryDir;
	step <= fromLinearStep when linNotRot='1' else fromRotaryStep;
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- LINE

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- BEGIN
		-- IP impl.op.vars --- END

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- BEGIN
			stateOp <= stateOpInit;
			linNotRot <= '0';

			-- IP impl.op.asyncrst --- END
			-- IP impl.op.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateOp=stateOpInit or (stateOp/=stateOpInv and reqInvSet='1')) then
				-- IP impl.op.syncrst --- RBEGIN
				-- IP impl.op.syncrst --- REND
				-- IP impl.op.syncrst.cust --- INSERT

				if reqInvSet='1' then
					-- IP impl.op.init.invSet --- IBEGIN
					if setLinNotRot=tru8 then
						linNotRot <= '1';
					else
						linNotRot <= '0';
					end if;
					-- IP impl.op.init.invSet --- IEND

					stateOp <= stateOpInv;

				else
					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpInv then
				if reqInvSet='0' then
					stateOp <= stateOpInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;


-- file Timeout_v1_0_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Timeout_v1_0_8c100ea18901433eb4f7c0fdbf115e06 module implementation
-- copyright: (C) 2017 MPSI Technologies GmbH
-- author: Alexander Wirthmueller
-- date created: 16 Jan 2017
-- date modified: 6 Apr 2017
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Timeout_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
	generic (
		twait: natural range 1 to 10000 -- in tkclk clocks
	);
	port (
		reset: in std_logic;

		mclk: in std_logic;

		tkclk: in std_logic;

		restart: in std_logic;
		timeout: out std_logic
	);
end Timeout_v1_0_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Timeout_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	-- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpWaitA, stateOpWaitB,
		stateOpDone
	);
	signal stateOp: stateOp_t;

begin

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	timeout <= '1' when (stateOp=stateOpDone and restart='0') else '0';

	process (reset, mclk, stateOp)
		variable i: natural range 0 to twait;

	begin
		if reset='1' then
			stateOp <= stateOpInit;

		elsif rising_edge(mclk) then
			if (restart='1' or stateOp=stateOpInit) then
				i := 0;

				if restart='1' then
					stateOp <= stateOpInit;
				else
					stateOp <= stateOpWaitA;
				end if;

			elsif stateOp=stateOpWaitA then
				if i=twait then
					stateOp <= stateOpDone;

				elsif tkclk='1' then
					stateOp <= stateOpWaitB;
				end if;
		
			elsif stateOp=stateOpWaitB then
				if tkclk='0' then
					i := i + 1;
					stateOp <= stateOpWaitA;
				end if;

			elsif stateOp=stateOpDone then
				-- if restart='1' then
				-- 	stateOp <= stateOpInit;
				-- end if;
			end if;
		end if;
	end process;

end Rtl;


-- file Tkclksrc_Easy_v1_0_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Tkclksrc_Easy_v1_0_8c100ea18901433eb4f7c0fdbf115e06 module implementation
-- copyright: (C) 2017-2024 MPSI Technologies GmbH
-- author: Alexander Wirthmueller
-- date created: 15 Dec 2017
-- date modified: 1 Jul 2024
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Tkclksrc_Easy_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
	generic (
		fMclk: natural := 50000
	);
	port (
		reset: in std_logic;
		mclk: in std_logic;
		tkclk: out std_logic;

		getTkstTkst: out std_logic_vector(31 downto 0);

		reqInvSetTkst: in std_logic;
		ackInvSetTkst: out std_logic;

		setTkstTkst: in std_logic_vector(31 downto 0);

		stateOp_dbg: out std_logic_vector(7 downto 0)
	);
end Tkclksrc_Easy_v1_0_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Tkclksrc_Easy_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv,
		stateOpRun
	);
	signal stateOp: stateOp_t;

	signal tkclk_sig: std_logic;
	signal tkst: std_logic_vector(31 downto 0);

begin

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	tkclk <= tkclk_sig;

	getTkstTkst <= tkst;

	ackInvSetTkst <= '1' when stateOp=stateOpInv else '0';

	-- IP cust --- BEGIN
	-- stateOp_dbg <= x"00" when stateOp=stateOpInit
	-- 			else x"10" when stateOp=stateOpInv
	-- 			else x"20" when stateOp=stateOpRun
	-- 			else (others => '1');
	-- IP cust --- END

	process (reset, mclk, stateOp)
		variable i: natural range 0 to (fMclk/10)/2;

	begin
		if reset='1' then
			stateOp <= stateOpInit;
			tkclk_sig <= '0';
			tkst <= (others => '0');

			i := 0;

		elsif rising_edge(mclk) then
			if (stateOp=stateOpInit or (stateOp/=stateOpInv and reqInvSetTkst='1')) then
				tkclk_sig <= '0';

				i := 0;

				if reqInvSetTkst='1' then
					tkst <= setTkstTkst;
					stateOp <= stateOpInv;
				else
					stateOp <= stateOpRun;
				end if;

			elsif stateOp=stateOpInv then
				if reqInvSetTkst='0' then
					stateOp <= stateOpRun;
				end if;

			elsif stateOp=stateOpRun then
				i := i + 1;
				if i=(fMclk/10)/2 then
					i := 0;
					if tkclk_sig='1' then
						tkst <= std_logic_vector(unsigned(tkst) + 1);
					end if;
					tkclk_sig <= not tkclk_sig;
				end if;
			end if;
		end if;
	end process;

end Rtl;


-- file Trace_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Trace_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Trace_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		vsync: in std_logic;
		ixTExp: in std_logic_vector(3 downto 0);

		NRow: in std_logic_vector(10 downto 0);
		NCol: in std_logic_vector(10 downto 0);

		rgbFromVideoinAXIS_tready: out std_logic;
		rgbFromVideoinAXIS_tvalid: in std_logic;
		rgbFromVideoinAXIS_tdata: in std_logic_vector(35 downto 0);
		rgbFromVideoinAXIS_tlast: in std_logic;

		tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0);

		reqInvAcquire: in std_logic;
		ackInvAcquire: out std_logic;

		reqInvConfig: in std_logic;
		ackInvConfig: out std_logic;

		configTixVOrient: in std_logic_vector(7 downto 0);
		configRow0: in std_logic_vector(15 downto 0);
		configCol0: in std_logic_vector(15 downto 0);

		getInfoTixVState: out std_logic_vector(7 downto 0);
		getInfoTkst: out std_logic_vector(31 downto 0);

		reqInvUnlock: in std_logic;
		ackInvUnlock: out std_logic;

		reqFlgbufToHostif: in std_logic;
		ackFlgbufToHostif: out std_logic;
		dneFlgbufToHostif: in std_logic;
		avllenFlgbufToHostif: out std_logic_vector(31 downto 0);

		flgbufToHostifAXIS_tready: in std_logic;
		flgbufToHostifAXIS_tvalid: out std_logic;
		flgbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
		flgbufToHostifAXIS_tlast: out std_logic
	);
end Trace_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Trace_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(13 downto 0);
			drdA: out std_logic_vector(7 downto 0);
			dwrA: in std_logic_vector(7 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(13 downto 0);
			drdB: out std_logic_vector(7 downto 0);
			dwrB: in std_logic_vector(7 downto 0)
		);
	end component;

	component Dpbram_size32kB_a32b8_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(12 downto 0);
			drdA: out std_logic_vector(31 downto 0);
			dwrA: in std_logic_vector(31 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(14 downto 0);
			drdB: out std_logic_vector(7 downto 0);
			dwrB: in std_logic_vector(7 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant tixVOrientSqr: std_logic_vector(7 downto 0) := x"00";
	constant tixVOrientLand: std_logic_vector(7 downto 0) := x"01";
	constant tixVOrientPort: std_logic_vector(7 downto 0) := x"02";

	constant tixVStateIdle: std_logic_vector(7 downto 0) := x"00";
	constant tixVStateAcq: std_logic_vector(7 downto 0) := x"01";
	constant tixVStateLock: std_logic_vector(7 downto 0) := x"02";

	---- flag buffer B/hostif-facing operation (flgbufB)
	type stateFlgbufB_t is (
		stateFlgbufBInit,
		stateFlgbufBIdle,
		stateFlgbufBXferA, stateFlgbufBXferB,
		stateFlgbufBDone
	);
	signal stateFlgbufB: stateFlgbufB_t;

	signal enFlgbufB: std_logic;
	signal aFlgbufB: natural range 0 to 32*1024/4-1;
	signal aFlgbufB_vec: std_logic_vector(12 downto 0);

	-- IP sigs.flgbufB.cust --- INSERT

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv
	);
	signal stateOp: stateOp_t;

	signal ackInvAcquire_sig: std_logic;
	signal ackInvConfig_sig: std_logic;
	signal ackInvUnlock_sig: std_logic;

	signal tixVState: std_logic_vector(7 downto 0);
	signal tkst: std_logic_vector(31 downto 0);

	signal tixVOrient: std_logic_vector(7 downto 0);

	signal row0: natural range 0 to 3000/2-1;
	signal col0: natural range 0 to 4000/2-1;

	signal enAccbuf: std_logic;
	signal aAccbuf: natural;
	signal aAccbuf_vec: std_logic_vector(17 downto 0);
	signal dwrAccbuf: std_logic_vector(7 downto 0);

	signal enAccbufB: std_logic;
	signal aAccbufB: natural;
	signal aAccbufB_vec: std_logic_vector(17 downto 0);

	signal enFlgbuf: std_logic;
	signal aFlgbuf: natural;
	signal aFlgbuf_vec: std_logic_vector(14 downto 0);
	signal dwrFlgbuf: std_logic_vector(7 downto 0);

	-- IP sigs.op.cust --- INSERT

	---- myAccbuf0
	signal drdAccbuf0B: std_logic_vector(7 downto 0);

	---- myAccbuf1
	signal drdAccbuf1B: std_logic_vector(7 downto 0);

	---- myAccbuf10
	signal drdAccbuf10B: std_logic_vector(7 downto 0);

	---- myAccbuf11
	signal drdAccbuf11B: std_logic_vector(7 downto 0);

	---- myAccbuf2
	signal drdAccbuf2B: std_logic_vector(7 downto 0);

	---- myAccbuf3
	signal drdAccbuf3B: std_logic_vector(7 downto 0);

	---- myAccbuf4
	signal drdAccbuf4B: std_logic_vector(7 downto 0);

	---- myAccbuf5
	signal drdAccbuf5B: std_logic_vector(7 downto 0);

	---- myAccbuf6
	signal drdAccbuf6B: std_logic_vector(7 downto 0);

	---- myAccbuf7
	signal drdAccbuf7B: std_logic_vector(7 downto 0);

	---- myAccbuf8
	signal drdAccbuf8B: std_logic_vector(7 downto 0);

	---- myAccbuf9
	signal drdAccbuf9B: std_logic_vector(7 downto 0);

	---- other
	-- IP sigs.oth.cust --- IBEGIN

	------------------------------------------------------------------------
	-- functional description
	------------------------------------------------------------------------

	-- perform log2 5-bit red-only HDR of "on" image first, then flag if log2 of "off" image is -2 or more
	-- accbuf is sufficient for 640x480 pixels, allow arbitrary row0/col0, 640x480/480x640/554x554 (up to 307200 pixels)

--	if abc=0 then
--		val <= drdAccbufB(4 downto 0);
--	elsif abc=1 then
--		val <= drdAccbufB(1 downto 0) & drdAccbufBm1(7 downto 5);
--	elsif abc=2 then
--		val <= drdAccbufB(6 downto 2);
--	elsif abc=3 then
--		val <= drdAccbufB(3 downto 0) & drdAccbufBm1(7 downto 7);
--	elsif abc=4 then
--		val <= drdAccbufB(0 downto 0) & drdAccbufBm1(7 downto 4);
--	elsif abc=5 then
--		val <= drdAccbufB(5 downto 1);
--	elsif abc=6 then
--		val <= drdAccbufB(2 downto 0) & drdAccbufBm1(7 downto 6);
--	elsif abc=7 then
--		val <= drdAccbufB(7 downto 3);
--	end if;

	-- IP sigs.oth.cust --- IEND

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myAccbuf0 : Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enAccbuf,
			weA => '1',

			aA => aAccbuf_vec(13 downto 0),
			drdA => open,
			dwrA => dwrAccbuf,

			rstB => reset,
			clkB => mclk,

			enB => enAccbufB,
			weB => '0',

			aB => aAccbufB_vec(13 downto 0),
			drdB => drdAccbuf0B,
			dwrB => (others => '0')
		);

	myAccbuf1 : Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enAccbuf,
			weA => '1',

			aA => aAccbuf_vec(13 downto 0),
			drdA => open,
			dwrA => dwrAccbuf,

			rstB => reset,
			clkB => mclk,

			enB => enAccbufB,
			weB => '0',

			aB => aAccbufB_vec(13 downto 0),
			drdB => drdAccbuf1B,
			dwrB => (others => '0')
		);

	myAccbuf10 : Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enAccbuf,
			weA => '1',

			aA => aAccbuf_vec(13 downto 0),
			drdA => open,
			dwrA => dwrAccbuf,

			rstB => reset,
			clkB => mclk,

			enB => enAccbufB,
			weB => '0',

			aB => aAccbufB_vec(13 downto 0),
			drdB => drdAccbuf10B,
			dwrB => (others => '0')
		);

	myAccbuf11 : Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enAccbuf,
			weA => '1',

			aA => aAccbuf_vec(13 downto 0),
			drdA => open,
			dwrA => dwrAccbuf,

			rstB => reset,
			clkB => mclk,

			enB => enAccbufB,
			weB => '0',

			aB => aAccbufB_vec(13 downto 0),
			drdB => drdAccbuf11B,
			dwrB => (others => '0')
		);

	myAccbuf2 : Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enAccbuf,
			weA => '1',

			aA => aAccbuf_vec(13 downto 0),
			drdA => open,
			dwrA => dwrAccbuf,

			rstB => reset,
			clkB => mclk,

			enB => enAccbufB,
			weB => '0',

			aB => aAccbufB_vec(13 downto 0),
			drdB => drdAccbuf2B,
			dwrB => (others => '0')
		);

	myAccbuf3 : Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enAccbuf,
			weA => '1',

			aA => aAccbuf_vec(13 downto 0),
			drdA => open,
			dwrA => dwrAccbuf,

			rstB => reset,
			clkB => mclk,

			enB => enAccbufB,
			weB => '0',

			aB => aAccbufB_vec(13 downto 0),
			drdB => drdAccbuf3B,
			dwrB => (others => '0')
		);

	myAccbuf4 : Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enAccbuf,
			weA => '1',

			aA => aAccbuf_vec(13 downto 0),
			drdA => open,
			dwrA => dwrAccbuf,

			rstB => reset,
			clkB => mclk,

			enB => enAccbufB,
			weB => '0',

			aB => aAccbufB_vec(13 downto 0),
			drdB => drdAccbuf4B,
			dwrB => (others => '0')
		);

	myAccbuf5 : Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enAccbuf,
			weA => '1',

			aA => aAccbuf_vec(13 downto 0),
			drdA => open,
			dwrA => dwrAccbuf,

			rstB => reset,
			clkB => mclk,

			enB => enAccbufB,
			weB => '0',

			aB => aAccbufB_vec(13 downto 0),
			drdB => drdAccbuf5B,
			dwrB => (others => '0')
		);

	myAccbuf6 : Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enAccbuf,
			weA => '1',

			aA => aAccbuf_vec(13 downto 0),
			drdA => open,
			dwrA => dwrAccbuf,

			rstB => reset,
			clkB => mclk,

			enB => enAccbufB,
			weB => '0',

			aB => aAccbufB_vec(13 downto 0),
			drdB => drdAccbuf6B,
			dwrB => (others => '0')
		);

	myAccbuf7 : Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enAccbuf,
			weA => '1',

			aA => aAccbuf_vec(13 downto 0),
			drdA => open,
			dwrA => dwrAccbuf,

			rstB => reset,
			clkB => mclk,

			enB => enAccbufB,
			weB => '0',

			aB => aAccbufB_vec(13 downto 0),
			drdB => drdAccbuf7B,
			dwrB => (others => '0')
		);

	myAccbuf8 : Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enAccbuf,
			weA => '1',

			aA => aAccbuf_vec(13 downto 0),
			drdA => open,
			dwrA => dwrAccbuf,

			rstB => reset,
			clkB => mclk,

			enB => enAccbufB,
			weB => '0',

			aB => aAccbufB_vec(13 downto 0),
			drdB => drdAccbuf8B,
			dwrB => (others => '0')
		);

	myAccbuf9 : Dpbram_size16kB_a8b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enAccbuf,
			weA => '1',

			aA => aAccbuf_vec(13 downto 0),
			drdA => open,
			dwrA => dwrAccbuf,

			rstB => reset,
			clkB => mclk,

			enB => enAccbufB,
			weB => '0',

			aB => aAccbufB_vec(13 downto 0),
			drdB => drdAccbuf9B,
			dwrB => (others => '0')
		);

	myFlgbuf : Dpbram_size32kB_a32b8_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enFlgbufB,
			weA => '0',

			aA => aFlgbufB_vec,
			drdA => flgbufToHostifAXIS_tdata,
			dwrA => (others => '0'),

			rstB => reset,
			clkB => mclk,

			enB => enFlgbuf,
			weB => '1',

			aB => aFlgbuf_vec,
			drdB => open,
			dwrB => dwrFlgbuf
		);

	------------------------------------------------------------------------
	-- implementation: flag buffer B/hostif-facing operation (flgbufB)
	------------------------------------------------------------------------

	-- IP impl.flgbufB.wiring --- BEGIN
	ackFlgbufToHostif <= '1' when (stateFlgbufB=stateFlgbufBXferA or stateFlgbufB=stateFlgbufBXferB or stateFlgbufB=stateFlgbufBDone) else '0';

	flgbufToHostifAXIS_tvalid <= '1' when stateFlgbufB=stateFlgbufBXferB else '0';
	flgbufToHostifAXIS_tlast <= '0' when (stateFlgbufB=stateFlgbufBXferA or (stateFlgbufB=stateFlgbufBXferB and aFlgbufB/=32*1024/4-1)) else '1';

	enFlgbufB <= '1' when stateFlgbufB=stateFlgbufBXferA else '0';
	aFlgbufB_vec <= std_logic_vector(to_unsigned(aFlgbufB, 13));
	-- IP impl.flgbufB.wiring --- END

	-- IP impl.flgbufB.wiring.cust --- RBEGIN
	avllenFlgbufToHostif <= std_logic_vector(to_unsigned(38*1024, 32)) when stateFlgbufB=stateFlgbufBIdle else (others => '0');
	-- IP impl.flgbufB.wiring.cust --- REND

	-- IP impl.flgbufB.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.flgbufB.vars --- BEGIN
		-- IP impl.flgbufB.vars --- END

	begin
		if reset='1' then
			-- IP impl.flgbufB.asyncrst --- BEGIN
			stateFlgbufB <= stateFlgbufBInit;
			aFlgbufB <= 0;

			-- IP impl.flgbufB.asyncrst --- END
			-- IP impl.flgbufB.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if stateFlgbufB=stateFlgbufBInit then
				-- IP impl.flgbufB.syncrst --- BEGIN
				aFlgbufB <= 0;

				-- IP impl.flgbufB.syncrst --- END
				-- IP impl.flgbufB.syncrst.cust --- INSERT

				if reqFlgbufToHostif='0' then
					stateFlgbufB <= stateFlgbufBIdle;
				end if;

			elsif stateFlgbufB=stateFlgbufBIdle then
				if reqFlgbufToHostif='1' then
					stateFlgbufB <= stateFlgbufBXferA;
				end if;

			elsif stateFlgbufB=stateFlgbufBXferA then
				stateFlgbufB <= stateFlgbufBXferB;

			elsif stateFlgbufB=stateFlgbufBXferB then
				if flgbufToHostifAXIS_tready='1' then
					if aFlgbufB=32*1024/4-1 then
						stateFlgbufB <= stateFlgbufBDone;

					else
						aFlgbufB <= aFlgbufB + 1; -- IP impl.flgbufB.xferB.inc --- ILINE

						stateFlgbufB <= stateFlgbufBXferA;
					end if;

				elsif reqFlgbufToHostif='0' then
					stateFlgbufB <= stateFlgbufBInit;
				end if;

			elsif stateFlgbufB=stateFlgbufBDone then
				if dneFlgbufToHostif='1' then
					stateFlgbufB <= stateFlgbufBInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.flgbufB.rising --- END

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	ackInvAcquire <= ackInvAcquire_sig;
	ackInvConfig <= ackInvConfig_sig;
	ackInvUnlock <= ackInvUnlock_sig;

	getInfoTixVState <= tixVState;
	getInfoTkst <= tkst;
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- LINE

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- BEGIN
		-- IP impl.op.vars --- END

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- BEGIN
			stateOp <= stateOpInit;
			ackInvAcquire_sig <= '0';
			ackInvConfig_sig <= '0';
			ackInvUnlock_sig <= '0';
			tixVState <= (others => '0');
			tkst <= (others => '0');
			tixVOrient <= (others => '0');
			row0 <= 0;
			col0 <= 0;
			enAccbuf <= '0';
			aAccbuf <= 0;
			aAccbuf_vec <= (others => '0');
			dwrAccbuf <= (others => '0');
			enAccbufB <= '0';
			aAccbufB <= 0;
			aAccbufB_vec <= (others => '0');
			enFlgbuf <= '0';
			aFlgbuf <= 0;
			aFlgbuf_vec <= (others => '0');
			dwrFlgbuf <= (others => '0');

			-- IP impl.op.asyncrst --- END
			-- IP impl.op.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateOp=stateOpInit or (stateOp/=stateOpInv and (reqInvAcquire='1' or reqInvConfig='1' or reqInvUnlock='1'))) then
				if reqInvAcquire='1' then
					-- IP impl.op.init.invAcquire --- IBEGIN
					if tixVState=tixVStateIdle then
						tixVState <= tixVStateAcq;
					end if;

					ackInvAcquire_sig <= '1';
					ackInvConfig_sig <= '0';
					ackInvUnlock_sig <= '0';
					-- IP impl.op.init.invAcquire --- IEND

					stateOp <= stateOpInv;

				elsif reqInvConfig='1' then
					-- IP impl.op.init.invConfig --- IBEGIN
					tixVOrient <= configTixVOrient;
					row0 <= to_integer(unsigned(configRow0));
					col0 <= to_integer(unsigned(configCol0));

					ackInvAcquire_sig <= '0';
					ackInvConfig_sig <= '1';
					ackInvUnlock_sig <= '0';
					-- IP impl.op.init.invConfig --- IEND

					stateOp <= stateOpInv;

				elsif reqInvUnlock='1' then
					-- IP impl.op.init.invUnlock --- IBEGIN
					if tixVState=tixVStateLock then
						tixVState <= tixVStateIdle;
					end if;

					ackInvAcquire_sig <= '1';
					ackInvConfig_sig <= '0';
					ackInvUnlock_sig <= '0';
					-- IP impl.op.init.invUnlock --- IEND

					stateOp <= stateOpInv;

				else
					-- IP impl.op.syncrst --- RBEGIN
					ackInvAcquire_sig <= '0';
					ackInvConfig_sig <= '0';
					ackInvUnlock_sig <= '0';
					enAccbuf <= '0';
					aAccbuf <= 0;
					aAccbuf_vec <= (others => '0');
					dwrAccbuf <= (others => '0');
					enAccbufB <= '0';
					aAccbufB <= 0;
					aAccbufB_vec <= (others => '0');
					enFlgbuf <= '0';
					aFlgbuf <= 0;
					aFlgbuf_vec <= (others => '0');
					dwrFlgbuf <= (others => '0');

					-- IP impl.op.syncrst --- REND
					-- IP impl.op.syncrst.cust --- INSERT

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpInv then
				if ((reqInvAcquire='0' and ackInvAcquire_sig='1') or (reqInvConfig='0' and ackInvConfig_sig='1') or (reqInvUnlock='0' and ackInvUnlock_sig='1')) then
					-- IP impl.op.inv.reset --- IBEGIN
					ackInvAcquire_sig <= '0';
					ackInvConfig_sig <= '0';
					ackInvUnlock_sig <= '0';
					-- IP impl.op.inv.reset --- IEND

					stateOp <= stateOpInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;


-- file Vecrend_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Vecrend_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Vecrend_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic
	);
end Vecrend_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Vecrend_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;


-- file Videoin_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Videoin_8c100ea18901433eb4f7c0fdbf115e06 easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Videoin_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		fromCamifAXIS_tready: out std_logic;
		fromCamifAXIS_tvalid: in std_logic;
		fromCamifAXIS_tdata: in std_logic_vector(23 downto 0);
		fromCamifAXIS_tlast: in std_logic;

		vsync: in std_logic;
		NCol: in std_logic_vector(10 downto 0);

		grayToManyAXIS_tready: in std_logic;
		grayToManyAXIS_tvalid: out std_logic;
		grayToManyAXIS_tdata: out std_logic_vector(71 downto 0);
		grayToManyAXIS_tlast: out std_logic;

		rgbToManyAXIS_tready: in std_logic;
		rgbToManyAXIS_tvalid: out std_logic;
		rgbToManyAXIS_tdata: out std_logic_vector(35 downto 0);
		rgbToManyAXIS_tlast: out std_logic;

		stateIgr_dbg: out std_logic_vector(7 downto 0);
		stateRgbegr_dbg: out std_logic_vector(7 downto 0)
	);
end Videoin_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Videoin_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_size8kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(9 downto 0);
			drdA: out std_logic_vector(63 downto 0);
			dwrA: in std_logic_vector(63 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(9 downto 0);
			drdB: out std_logic_vector(63 downto 0);
			dwrB: in std_logic_vector(63 downto 0)
		);
	end component;

	component Dpbram_size4kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(8 downto 0);
			drdA: out std_logic_vector(63 downto 0);
			dwrA: in std_logic_vector(63 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(8 downto 0);
			drdB: out std_logic_vector(63 downto 0);
			dwrB: in std_logic_vector(63 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- gray egress from buffers operation (grayegr)
	type stateGrayegr_t is (
		stateGrayegrInit,
		stateGrayegrIdle,
		stateGrayegrLoad,
		stateGrayegrRun,
		stateGrayegrEol
	);
	signal stateGrayegr: stateGrayegr_t;

	signal abcde: natural range 0 to 4; -- used jointly between graypack and grayegr
	signal nop: natural range 0 to 15;
	signal enRowbufB: std_logic;

	signal aRowbufB: natural range 0 to 511;
	signal aRowbufB_vec: std_logic_vector(8 downto 0);

	signal drdRow0bufBm1: std_logic_vector(63 downto 0);
	signal drdRow1bufBm1: std_logic_vector(63 downto 0);
	signal drdRow2bufBm1: std_logic_vector(63 downto 0);
	signal drdRow3bufBm1: std_logic_vector(63 downto 0);
	signal drdRow4bufBm1: std_logic_vector(63 downto 0);

	signal grayToManyAXIS_tvalid_sig: std_logic;
	signal grayToManyAXIS_tlast_sig: std_logic;

	signal gr0: std_logic_vector(11 downto 0);
	signal gr1: std_logic_vector(11 downto 0);
	signal gr2: std_logic_vector(11 downto 0);
	signal gr3: std_logic_vector(11 downto 0);
	signal gr4: std_logic_vector(11 downto 0);

	-- IP sigs.grayegr.cust --- INSERT

	---- RGB-to-gray packing operation (graypack)
	type stateGraypack_t is (
		stateGraypackInit,
		stateGraypackIdle,
		stateGraypackRun,
		stateGraypackEol
	);
	signal stateGraypack: stateGraypack_t;

	signal tuv: natural range 0 to 15;

	signal enRowbuf: std_logic;
	signal enRow0buf: std_logic;
	signal enRow1buf: std_logic;
	signal enRow2buf: std_logic;
	signal enRow3buf: std_logic;
	signal enRow4buf: std_logic;

	signal aRowbuf: natural range 0 to 511;
	signal aRowbuf_vec: std_logic_vector(8 downto 0);

	signal dwrRowbuf: std_logic_vector(63 downto 0);
	signal dwrRowbufp1: std_logic_vector(63 downto 0);

	-- IP sigs.graypack.cust --- INSERT

	---- ingress and even/odd buffer packing operation (igr)
	type stateIgr_t is (
		stateIgrInit,
		stateIgrRun,
		stateIgrEolA, stateIgrEolB
	);
	signal stateIgr: stateIgr_t;

	signal klm: natural range 0 to 7;

	signal fillBNotA: std_logic;
	signal oddNotEven: std_logic;

	signal enEobuf: std_logic;

	signal enEvenAbuf: std_logic;
	signal enEvenBbuf: std_logic;

	signal enOddbuf: std_logic;

	signal aEobuf: natural range 0 to 767;
	signal aEobuf_vec: std_logic_vector(9 downto 0);

	signal dwrEobuf: std_logic_vector(63 downto 0);
	signal dwrEobufp1: std_logic_vector(63 downto 0);

	signal rawcolEgrstart: natural range 0 to 3999;
	signal strbEgrstart: std_logic;

	-- IP sigs.igr.cust --- INSERT

	---- RGB and internal egress from buffers operation (rgbegr)
	type stateRgbegr_t is (
		stateRgbegrInit,
		stateRgbegrIdle,
		stateRgbegrLoad,
		stateRgbegrRun,
		stateRgbegrHold,
		stateRgbegrEol
	);
	signal stateRgbegr: stateRgbegr_t;

	signal qrs: natural range 0 to 7;
	signal enEobufB: std_logic;

	signal enEvenAbufB: std_logic;
	signal enEvenBbufB: std_logic;

	signal aEobufB: natural range 0 to 767;
	signal aEobufB_vec: std_logic_vector(9 downto 0);

	signal drdEvenbufB: std_logic_vector(63 downto 0);
	signal drdEvenbufBm1: std_logic_vector(63 downto 0);

	signal drdOddbufBm1: std_logic_vector(63 downto 0);

	signal rgbToManyAXIS_tvalid_sig: std_logic;
	signal rgbToManyAXIS_tdata_sig: std_logic_vector(35 downto 0);
	signal rgbToManyAXIS_tlast_sig: std_logic;

	signal gr: std_logic_vector(11 downto 0);

	-- IP sigs.rgbegr.cust --- INSERT

	---- myEvenAbuf
	signal drdEvenAbufB: std_logic_vector(63 downto 0);

	---- myEvenBbuf
	signal drdEvenBbufB: std_logic_vector(63 downto 0);

	---- myOddbuf
	signal drdOddbufB: std_logic_vector(63 downto 0);

	---- myRow0buf
	signal drdRow0bufB: std_logic_vector(63 downto 0);

	---- myRow1buf
	signal drdRow1bufB: std_logic_vector(63 downto 0);

	---- myRow2buf
	signal drdRow2bufB: std_logic_vector(63 downto 0);

	---- myRow3buf
	signal drdRow3bufB: std_logic_vector(63 downto 0);

	---- myRow4buf
	signal drdRow4bufB: std_logic_vector(63 downto 0);

	---- other
	signal sprsNotFull: std_logic := '1';
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myEvenAbuf : Dpbram_size8kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enEvenAbuf,
			weA => '1',

			aA => aEobuf_vec,
			drdA => open,
			dwrA => dwrEobuf,

			rstB => reset,
			clkB => mclk,

			enB => enEvenAbufB,
			weB => '0',

			aB => aEobufB_vec,
			drdB => drdEvenAbufB,
			dwrB => (others => '0')
		);

	myEvenBbuf : Dpbram_size8kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enEvenBbuf,
			weA => '1',

			aA => aEobuf_vec,
			drdA => open,
			dwrA => dwrEobuf,

			rstB => reset,
			clkB => mclk,

			enB => enEvenBbufB,
			weB => '0',

			aB => aEobufB_vec,
			drdB => drdEvenBbufB,
			dwrB => (others => '0')
		);

	myOddbuf : Dpbram_size8kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enOddbuf,
			weA => '1',

			aA => aEobuf_vec,
			drdA => open,
			dwrA => dwrEobuf,

			rstB => '0',
			clkB => mclk,

			enB => enEobufB,
			weB => '0',

			aB => aEobufB_vec,
			drdB => drdOddbufB,
			dwrB => (others => '0')
		);

	myRow0buf : Dpbram_size4kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enRow0buf,
			weA => '1',

			aA => aRowbuf_vec,
			drdA => open,
			dwrA => dwrRowbuf,

			rstB => reset,
			clkB => mclk,

			enB => enRowbufB,
			weB => '0',

			aB => aRowbufB_vec,
			drdB => drdRow0bufB,
			dwrB => (others => '0')
		);

	myRow1buf : Dpbram_size4kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enRow1buf,
			weA => '1',

			aA => aRowbuf_vec,
			drdA => open,
			dwrA => dwrRowbuf,

			rstB => reset,
			clkB => mclk,

			enB => enRowbufB,
			weB => '0',

			aB => aRowbufB_vec,
			drdB => drdRow1bufB,
			dwrB => (others => '0')
		);

	myRow2buf : Dpbram_size4kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enRow2buf,
			weA => '1',

			aA => aRowbuf_vec,
			drdA => open,
			dwrA => dwrRowbuf,

			rstB => reset,
			clkB => mclk,

			enB => enRowbufB,
			weB => '0',

			aB => aRowbufB_vec,
			drdB => drdRow2bufB,
			dwrB => (others => '0')
		);

	myRow3buf : Dpbram_size4kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enRow3buf,
			weA => '1',

			aA => aRowbuf_vec,
			drdA => open,
			dwrA => dwrRowbuf,

			rstB => reset,
			clkB => mclk,

			enB => enRowbufB,
			weB => '0',

			aB => aRowbufB_vec,
			drdB => drdRow3bufB,
			dwrB => (others => '0')
		);

	myRow4buf : Dpbram_size4kB_a64b64_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enRow4buf,
			weA => '1',

			aA => aRowbuf_vec,
			drdA => open,
			dwrA => dwrRowbuf,

			rstB => reset,
			clkB => mclk,

			enB => enRowbufB,
			weB => '0',

			aB => aRowbufB_vec,
			drdB => drdRow4bufB,
			dwrB => (others => '0')
		);

	------------------------------------------------------------------------
	-- implementation: gray egress from buffers operation (grayegr)
	------------------------------------------------------------------------

	-- IP impl.grayegr.wiring --- BEGIN
	aRowbufB_vec <= std_logic_vector(to_unsigned(aRowbufB, 9));

	grayToManyAXIS_tvalid <= grayToManyAXIS_tvalid_sig;
	grayToManyAXIS_tlast <= grayToManyAXIS_tlast_sig;
	-- IP impl.grayegr.wiring --- END

	-- IP impl.grayegr.wiring.cust --- RBEGIN
	grayToManyAXIS_tdata <= gr0 & gr1 & gr2 & gr3 & gr4 & gr when abcde=0
				else gr1 & gr2 & gr3 & gr4 & gr0 & gr when abcde=1
				else gr2 & gr3 & gr4 & gr0 & gr1 & gr when abcde=2
				else gr3 & gr4 & gr0 & gr1 & gr2 & gr when abcde=3
				else gr4 & gr0 & gr1 & gr2 & gr3 & gr when abcde=4
				else (others => '0');
	-- IP impl.grayegr.wiring.cust --- REND

	-- IP impl.grayegr.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.grayegr.vars --- RBEGIN
		variable col_lcl: natural range 0 to 2000;

		variable enRowbufB_lcl: std_logic;
		-- IP impl.grayegr.vars --- REND

	begin
		if reset='1' then
			-- IP impl.grayegr.asyncrst --- BEGIN
			stateGrayegr <= stateGrayegrInit;
			abcde <= 0;
			nop <= 0;
			enRowbufB <= '0';
			aRowbufB <= 0;
			drdRow0bufBm1 <= (others => '0');
			drdRow1bufBm1 <= (others => '0');
			drdRow2bufBm1 <= (others => '0');
			drdRow3bufBm1 <= (others => '0');
			drdRow4bufBm1 <= (others => '0');
			grayToManyAXIS_tvalid_sig <= '0';
			grayToManyAXIS_tlast_sig <= '1';
			gr0 <= (others => '0');
			gr1 <= (others => '0');
			gr2 <= (others => '0');
			gr3 <= (others => '0');
			gr4 <= (others => '0');

			-- IP impl.grayegr.asyncrst --- END
			-- IP impl.grayegr.asyncrst.cust --- IBEGIN
			col_lcl := 0;
			enRowbufB_lcl := '0';
			-- IP impl.grayegr.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			if stateGrayegr=stateGrayegrInit then
				-- IP impl.grayegr.syncrst --- BEGIN
				abcde <= 0;
				nop <= 0;
				enRowbufB <= '0';
				aRowbufB <= 0;
				drdRow0bufBm1 <= (others => '0');
				drdRow1bufBm1 <= (others => '0');
				drdRow2bufBm1 <= (others => '0');
				drdRow3bufBm1 <= (others => '0');
				drdRow4bufBm1 <= (others => '0');
				grayToManyAXIS_tvalid_sig <= '0';
				grayToManyAXIS_tlast_sig <= '1';
				gr0 <= (others => '0');
				gr1 <= (others => '0');
				gr2 <= (others => '0');
				gr3 <= (others => '0');
				gr4 <= (others => '0');

				-- IP impl.grayegr.syncrst --- END
				-- IP impl.grayegr.syncrst.cust --- IBEGIN
				col_lcl := 0;
				enRowbufB_lcl := '0';
				-- IP impl.grayegr.syncrst.cust --- IEND

				if vsync='1' then
					stateGrayegr <= stateGrayegrInit;

				else
					stateGrayegr <= stateGrayegrIdle;
				end if;

			elsif stateGrayegr=stateGrayegrIdle then
				if strbEgrstart='1' then
					enRowbufB <= '1'; -- IP impl.grayegr.idle.start --- ILINE

					stateGrayegr <= stateGrayegrLoad;
				end if;

			elsif stateGrayegr=stateGrayegrLoad then
				-- IP impl.grayegr.load --- IBEGIN
				grayToManyAXIS_tlast_sig <= '0';

				enRowbufB <= '0';
				aRowbufB <= aRowbufB + 1;

				enRowbufB_lcl := '0';
				-- IP impl.grayegr.load --- IEND

				stateGrayegr <= stateGrayegrRun;

			elsif stateGrayegr=stateGrayegrRun then
				if rgbToManyAXIS_tvalid_sig='1' then
					-- IP impl.grayegr.run --- IBEGIN
					if nop=0 then -- en at nop 14
						gr0 <= drdRow0bufB(11 downto 0);
						gr1 <= drdRow1bufB(11 downto 0);
						gr2 <= drdRow2bufB(11 downto 0);
						gr3 <= drdRow3bufB(11 downto 0);
						gr4 <= drdRow4bufB(11 downto 0);
					elsif nop=1 then
						gr0 <= drdRow0bufB(23 downto 12);
						gr1 <= drdRow1bufB(23 downto 12);
						gr2 <= drdRow2bufB(23 downto 12);
						gr3 <= drdRow3bufB(23 downto 12);
						gr4 <= drdRow4bufB(23 downto 12);
					elsif nop=2 then
						gr0 <= drdRow0bufB(35 downto 24);
						gr1 <= drdRow1bufB(35 downto 24);
						gr2 <= drdRow2bufB(35 downto 24);
						gr3 <= drdRow3bufB(35 downto 24);
						gr4 <= drdRow4bufB(35 downto 24);
					elsif nop=3 then
						gr0 <= drdRow0bufB(47 downto 36);
						gr1 <= drdRow1bufB(47 downto 36);
						gr2 <= drdRow2bufB(47 downto 36);
						gr3 <= drdRow3bufB(47 downto 36);
						gr4 <= drdRow4bufB(47 downto 36);
					elsif nop=4 then
						gr0 <= drdRow0bufB(59 downto 48);
						gr1 <= drdRow1bufB(59 downto 48);
						gr2 <= drdRow2bufB(59 downto 48);
						gr3 <= drdRow3bufB(59 downto 48);
						gr4 <= drdRow4bufB(59 downto 48);
					elsif nop=5 then -- en at nop 3
						gr0 <= drdRow0bufB(7 downto 0) & drdRow0bufBm1(63 downto 60);
						gr1 <= drdRow1bufB(7 downto 0) & drdRow1bufBm1(63 downto 60);
						gr2 <= drdRow2bufB(7 downto 0) & drdRow2bufBm1(63 downto 60);
						gr3 <= drdRow3bufB(7 downto 0) & drdRow3bufBm1(63 downto 60);
						gr4 <= drdRow4bufB(7 downto 0) & drdRow4bufBm1(63 downto 60);
					elsif nop=6 then
						gr0 <= drdRow0bufB(19 downto 8);
						gr1 <= drdRow1bufB(19 downto 8);
						gr2 <= drdRow2bufB(19 downto 8);
						gr3 <= drdRow3bufB(19 downto 8);
						gr4 <= drdRow4bufB(19 downto 8);
					elsif nop=7 then
						gr0 <= drdRow0bufB(31 downto 20);
						gr1 <= drdRow1bufB(31 downto 20);
						gr2 <= drdRow2bufB(31 downto 20);
						gr3 <= drdRow3bufB(31 downto 20);
						gr4 <= drdRow4bufB(31 downto 20);
					elsif nop=8 then
						gr0 <= drdRow0bufB(43 downto 32);
						gr1 <= drdRow1bufB(43 downto 32);
						gr2 <= drdRow2bufB(43 downto 32);
						gr3 <= drdRow3bufB(43 downto 32);
						gr4 <= drdRow4bufB(43 downto 32);
					elsif nop=9 then
						gr0 <= drdRow0bufB(55 downto 44);
						gr1 <= drdRow1bufB(55 downto 44);
						gr2 <= drdRow2bufB(55 downto 44);
						gr3 <= drdRow3bufB(55 downto 44);
						gr4 <= drdRow4bufB(55 downto 44);
					elsif nop=10 then -- en at nop 8
						gr0 <= drdRow0bufB(3 downto 0) & drdRow0bufBm1(63 downto 56);
						gr1 <= drdRow1bufB(3 downto 0) & drdRow1bufBm1(63 downto 56);
						gr2 <= drdRow2bufB(3 downto 0) & drdRow2bufBm1(63 downto 56);
						gr3 <= drdRow3bufB(3 downto 0) & drdRow3bufBm1(63 downto 56);
						gr4 <= drdRow4bufB(3 downto 0) & drdRow4bufBm1(63 downto 56);
					elsif nop=11 then
						gr0 <= drdRow0bufB(15 downto 4);
						gr1 <= drdRow1bufB(15 downto 4);
						gr2 <= drdRow2bufB(15 downto 4);
						gr3 <= drdRow3bufB(15 downto 4);
						gr4 <= drdRow4bufB(15 downto 4);
					elsif nop=12 then
						gr0 <= drdRow0bufB(27 downto 16);
						gr1 <= drdRow1bufB(27 downto 16);
						gr2 <= drdRow2bufB(27 downto 16);
						gr3 <= drdRow3bufB(27 downto 16);
						gr4 <= drdRow4bufB(27 downto 16);
					elsif nop=13 then
						gr0 <= drdRow0bufB(39 downto 28);
						gr1 <= drdRow1bufB(39 downto 28);
						gr2 <= drdRow2bufB(39 downto 28);
						gr3 <= drdRow3bufB(39 downto 28);
						gr4 <= drdRow4bufB(39 downto 28);
					elsif nop=14 then
						gr0 <= drdRow0bufB(51 downto 40);
						gr1 <= drdRow1bufB(51 downto 40);
						gr2 <= drdRow2bufB(51 downto 40);
						gr3 <= drdRow3bufB(51 downto 40);
						gr4 <= drdRow4bufB(51 downto 40);
					elsif nop=15 then
						gr0 <= drdRow0bufB(63 downto 52);
						gr1 <= drdRow1bufB(63 downto 52);
						gr2 <= drdRow2bufB(63 downto 52);
						gr3 <= drdRow3bufB(63 downto 52);
						gr4 <= drdRow4bufB(63 downto 52);
					end if;

					if nop=14 or nop=3 or nop=8 then
						enRowbufB_lcl := '1';

						drdRow0bufBm1 <= drdRow0bufB;
						drdRow1bufBm1 <= drdRow1bufB;
						drdRow2bufBm1 <= drdRow2bufB;
						drdRow3bufBm1 <= drdRow3bufB;
						drdRow4bufBm1 <= drdRow4bufB;

					else
						enRowbufB_lcl := '0';
					end if;

					if (nop=15 or nop=4 or nop=9) then
						aRowbufB <= aRowbufB + 1;
					end if;

					if nop=15 then
						nop <= 0;
					else
						nop <= nop + 1;
					end if;

					grayToManyAXIS_tvalid_sig <= '1';

					col_lcl := col_lcl + 1; -- in next clock cycle
					-- IP impl.grayegr.run --- IEND

					if col_lcl=unsigned(NCol) then
						grayToManyAXIS_tlast_sig <= '1'; -- IP impl.grayegr.run.rowDone --- ILINE

						stateGrayegr <= stateGrayegrEol;

					else
						-- IP impl.grayegr.run.nextCol --- IBEGIN
						if sprsNotFull='0' then
							enRowbufB <= enRowbufB_lcl;
						else
							enRowbufB <= '0';
						end if;
						-- IP impl.grayegr.run.nextCol --- IEND

						stateGrayegr <= stateGrayegrRun;
					end if;

				else
					-- IP impl.grayegr.run.reset --- IBEGIN
					if sprsNotFull='1' then
						enRowbufB <= enRowbufB_lcl;
					else
						enRowbufB <= '0';
					end if;

					grayToManyAXIS_tvalid_sig <= '0';
					-- IP impl.grayegr.run.reset --- IEND

					stateGrayegr <= stateGrayegrRun;
				end if;

			elsif stateGrayegr=stateGrayegrEol then
				grayToManyAXIS_tvalid_sig <= '0'; -- IP impl.grayegr.eol.pre --- ILINE

				if vsync='1' then
					stateGrayegr <= stateGrayegrInit;

				else
					-- IP impl.grayegr.eol.nextRow --- IBEGIN
					if abcde=4 then
						abcde <= 0;
					else
						abcde <= abcde + 1;
					end if;

					nop <= 0;

					enRowbufB <= '0';
					aRowbufB <= 0;

					col_lcl := 0;
					-- IP impl.grayegr.eol.nextRow --- IEND

					stateGrayegr <= stateGrayegrIdle;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.grayegr.rising --- END

	------------------------------------------------------------------------
	-- implementation: RGB-to-gray packing operation (graypack)
	------------------------------------------------------------------------

	-- IP impl.graypack.wiring --- BEGIN
	enRow0buf <= '1' when (enRowbuf='1' and abcde=0) else '0';
	enRow1buf <= '1' when (enRowbuf='1' and abcde=1) else '0';
	enRow2buf <= '1' when (enRowbuf='1' and abcde=2) else '0';
	enRow3buf <= '1' when (enRowbuf='1' and abcde=3) else '0';
	enRow4buf <= '1' when (enRowbuf='1' and abcde=4) else '0';

	aRowbuf_vec <= std_logic_vector(to_unsigned(aRowbuf, 9));
	-- IP impl.graypack.wiring --- END

	-- IP impl.graypack.wiring.cust --- RBEGIN

	-- row*buf write side

	-- 12 = (2^2)*3, 64 = (2^2)*2^4 => 16 entries in three words
	-- 0: Gr5/4 Gr4/12 Gr3/12 Gr2/12 Gr1/12 Gr0/12
	-- 1: Gr10/8 Gr9/12 Gr8/12 Gr7/12 Gr6/12 /8
	-- 2: Gr15/12 Gr14/12 Gr13/12 Gr12/12 Gr11/12 /4

	-- population sequence: rowbuf0-1-2-3-4-0-1-2-3-4

	-- IP impl.graypack.wiring.cust --- REND

	-- IP impl.graypack.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.graypack.vars --- RBEGIN
		variable col_lcl: natural range 0 to 2000;
		-- IP impl.graypack.vars --- REND

	begin
		if reset='1' then
			-- IP impl.graypack.asyncrst --- BEGIN
			stateGraypack <= stateGraypackInit;
			tuv <= 0;
			enRowbuf <= '0';
			aRowbuf <= 0;
			dwrRowbuf <= (others => '0');
			dwrRowbufp1 <= (others => '0');

			-- IP impl.graypack.asyncrst --- END
			-- IP impl.graypack.asyncrst.cust --- IBEGIN
			col_lcl := 0;
			-- IP impl.graypack.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			if stateGraypack=stateGraypackInit then
				-- IP impl.graypack.syncrst --- BEGIN
				tuv <= 0;
				enRowbuf <= '0';
				aRowbuf <= 0;
				dwrRowbuf <= (others => '0');
				dwrRowbufp1 <= (others => '0');

				-- IP impl.graypack.syncrst --- END
				-- IP impl.graypack.syncrst.cust --- IBEGIN
				col_lcl := 0;
				-- IP impl.graypack.syncrst.cust --- IEND

				if vsync='1' then
					stateGraypack <= stateGraypackInit;

				else
					stateGraypack <= stateGraypackIdle;
				end if;

			elsif stateGraypack=stateGraypackIdle then
				if strbEgrstart='1' then
					stateGraypack <= stateGraypackRun;
				end if;

			elsif stateGraypack=stateGraypackRun then
				if rgbToManyAXIS_tvalid_sig='1' then
					-- IP impl.graypack.run --- IBEGIN
					if tuv=0 then
						dwrRowbuf(11 downto 0) <= gr;
					elsif tuv=1 then
						dwrRowbuf(23 downto 12) <= gr;
					elsif tuv=2 then
						dwrRowbuf(35 downto 24) <= gr;
					elsif tuv=3 then
						dwrRowbuf(47 downto 36) <= gr;
					elsif tuv=4 then
						dwrRowbuf(59 downto 48) <= gr;
					elsif tuv=5 then
						dwrRowbuf(63 downto 60) <= gr(3 downto 0);
						dwrRowbufp1(7 downto 0) <= gr(11 downto 4);
					elsif tuv=6 then
						dwrRowbuf(7 downto 0) <= dwrRowbufp1(7 downto 0);
						dwrRowbuf(19 downto 8) <= gr;
					elsif tuv=7 then
						dwrRowbuf(31 downto 20) <= gr;
					elsif tuv=8 then
						dwrRowbuf(43 downto 32) <= gr;
					elsif tuv=9 then
						dwrRowbuf(55 downto 44) <= gr;
					elsif tuv=10 then
						dwrRowbuf(63 downto 56) <= gr(7 downto 0);
						dwrRowbufp1(3 downto 0) <= gr(11 downto 8);
					elsif tuv=11 then
						dwrRowbuf(3 downto 0) <= dwrRowbufp1(3 downto 0);
						dwrRowbuf(15 downto 4) <= gr;
					elsif tuv=12 then
						dwrRowbuf(27 downto 16) <= gr;
					elsif tuv=13 then
						dwrRowbuf(39 downto 28) <= gr;
					elsif tuv=14 then
						dwrRowbuf(51 downto 40) <= gr;
					elsif tuv=15 then
						dwrRowbuf(63 downto 52) <= gr;
					end if;

					col_lcl := col_lcl + 1; -- in next clock cycle

					if (tuv=5 or tuv=10 or tuv=15) or col_lcl=unsigned(NCol) then
						enRowbuf <= '1';
					else
						enRowbuf <= '0';
					end if;

					if tuv=6 or tuv=11 or (tuv=0 and col_lcl/=1) then
						aRowbuf <= aRowbuf + 1;
					end if;

					if tuv=15 then
						tuv <= 0;
					else
						tuv <= tuv + 1;
					end if;
					-- IP impl.graypack.run --- IEND

					if col_lcl=unsigned(NCol) then
						stateGraypack <= stateGraypackEol;

					else
						stateGraypack <= stateGraypackRun;
					end if;
				end if;

			elsif stateGraypack=stateGraypackEol then
				if vsync='1' then
					stateGraypack <= stateGraypackInit;

				else
					-- IP impl.graypack.eol.nextRow --- IBEGIN
					tuv <= 0;

					enRowbuf <= '0';
					aRowbuf <= 0;
					
					col_lcl := 0;
					-- IP impl.graypack.eol.nextRow --- IEND

					stateGraypack <= stateGraypackIdle;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.graypack.rising --- END

	------------------------------------------------------------------------
	-- implementation: ingress and even/odd buffer packing operation (igr)
	------------------------------------------------------------------------

	-- IP impl.igr.wiring --- BEGIN
	enEvenAbuf <= '1' when (enEobuf='1' and fillBNotA='0' and oddNotEven='0') else '0';
	enEvenBbuf <= '1' when (enEobuf='1' and fillBNotA='1' and oddNotEven='0') else '0';

	enOddbuf <= '1' when (enEobuf='1' and oddNotEven='1') else '0';

	aEobuf_vec <= std_logic_vector(to_unsigned(aEobuf, 10));
	-- IP impl.igr.wiring --- END

	-- IP impl.igr.wiring.cust --- RBEGIN

	-- input: r/12 & g/12 or g/12 & b/12 (up to each clock)
	-- output: 64 bit (sparse)

	-- 24 = (2^3)*3, 64 = (2^3)*2^3 => 8 entries in three words
	-- 0: (R2G2)/16 (R1/12,G1/12)/24 (R0/12,G0/12)/24
	-- 1: (R5G5)/8 (R4G4)/24 (R3G3)/24 /8
	-- 2: (R7G7)/24 (R6G6)/24 /16

	-- IP impl.igr.wiring.cust --- REND

	stateIgr_dbg <= x"00" when stateIgr=stateIgrInit
				else x"10" when stateIgr=stateIgrRun
				else x"20" when stateIgr=stateIgrEolA
				else x"21" when stateIgr=stateIgrEolB
				else (others => '1');

	-- IP impl.igr.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.igr.vars --- RBEGIN
		variable rawcol_lcl: natural range 0 to 4000;
		-- IP impl.igr.vars --- REND

	begin
		if reset='1' then
			-- IP impl.igr.asyncrst --- BEGIN
			stateIgr <= stateIgrInit;
			klm <= 0;
			fillBNotA <= '0';
			oddNotEven <= '0';
			enEobuf <= '0';
			aEobuf <= 0;
			dwrEobuf <= (others => '0');
			dwrEobufp1 <= (others => '0');
			rawcolEgrstart <= 256;
			strbEgrstart <= '0';

			-- IP impl.igr.asyncrst --- END
			-- IP impl.igr.asyncrst.cust --- IBEGIN
			rawcol_lcl := 0;
			-- IP impl.igr.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			if stateIgr=stateIgrInit then
				-- IP impl.igr.syncrst --- BEGIN
				klm <= 0;
				fillBNotA <= '0';
				oddNotEven <= '0';
				enEobuf <= '0';
				aEobuf <= 0;
				dwrEobuf <= (others => '0');
				dwrEobufp1 <= (others => '0');
				rawcolEgrstart <= 256;
				strbEgrstart <= '0';

				-- IP impl.igr.syncrst --- END
				-- IP impl.igr.syncrst.cust --- IBEGIN
				rawcol_lcl := 0;
				-- IP impl.igr.syncrst.cust --- IEND

				if vsync='1' then
					stateIgr <= stateIgrRun;

				else
					stateIgr <= stateIgrInit;
				end if;

			elsif stateIgr=stateIgrRun then
				-- IP impl.igr.run.pre --- IBEGIN
				if strbEgrstart='1' then
					strbEgrstart <= '0';
				elsif oddNotEven='1' and rawcol_lcl=rawcolEgrstart then
					strbEgrstart <= '1';
				end if;
				-- IP impl.igr.run.pre --- IEND

				if (vsync='0' and fromCamifAXIS_tvalid='1') then
					-- IP impl.igr.run --- IBEGIN
					if klm=0 then
						dwrEobuf(23 downto 0) <= fromCamifAXIS_tdata;
					elsif klm=1 then
						dwrEobuf(47 downto 24) <= fromCamifAXIS_tdata;
					elsif klm=2 then
						dwrEobuf(63 downto 48) <= fromCamifAXIS_tdata(15 downto 0);
						dwrEobufp1(7 downto 0) <= fromCamifAXIS_tdata(23 downto 16);
					elsif klm=3 then
						dwrEobuf(7 downto 0) <= dwrEobufp1(7 downto 0);
						dwrEobuf(31 downto 8) <= fromCamifAXIS_tdata;
					elsif klm=4 then
						dwrEobuf(55 downto 32) <= fromCamifAXIS_tdata;
					elsif klm=5 then
						dwrEobuf(63 downto 56) <= fromCamifAXIS_tdata(7 downto 0);
						dwrEobufp1(15 downto 0) <= fromCamifAXIS_tdata(23 downto 8);
					elsif klm=6 then
						dwrEobuf(15 downto 0) <= dwrEobufp1(15 downto 0);
						dwrEobuf(39 downto 16) <= fromCamifAXIS_tdata;
					elsif klm=7 then
						dwrEobuf(63 downto 40) <= fromCamifAXIS_tdata;
					end if;

					if klm=2 or klm=5 or klm=7 then
						enEobuf <= '1';
					else
						enEobuf <= '0';
					end if;

					if klm=3 or klm=6 or (klm=0 and rawcol_lcl/=0) then
						aEobuf <= aEobuf + 1;
					end if;

					if klm=7 then
						klm <= 0;
					else
						klm <= klm + 1;
					end if;

					rawcol_lcl := rawcol_lcl + 1;
					-- IP impl.igr.run --- IEND

					if fromCamifAXIS_tlast='1' then
						if (klm=2 or klm=5 or klm=7) then
							stateIgr <= stateIgrEolB;

						else
							stateIgr <= stateIgrEolA;
						end if;

					else
						stateIgr <= stateIgrRun;
					end if;
				end if;

			elsif stateIgr=stateIgrEolA then
				-- IP impl.igr.eolA --- IBEGIN
				enEobuf <= '1';
				
				if klm=3 or klm=6 or klm=0 then
					aEobuf <= aEobuf + 1;
				end if;
				-- IP impl.igr.eolA --- IEND

				stateIgr <= stateIgrEolB;

			elsif stateIgr=stateIgrEolB then
				if vsync='1' then
					stateIgr <= stateIgrInit;

				else
					-- IP impl.igr.eolB.nextRow --- IBEGIN
					klm <= 0;

					if oddNotEven='0' then
						fillBNotA <= not fillBNotA;
					end if;

					oddNotEven <= not oddNotEven;

					enEobuf <= '0';
					aEobuf <= 0;

					rawcol_lcl := 0;
					-- IP impl.igr.eolB.nextRow --- IEND

					stateIgr <= stateIgrRun;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.igr.rising --- END

	------------------------------------------------------------------------
	-- implementation: RGB and internal egress from buffers operation (rgbegr)
	------------------------------------------------------------------------

	-- IP impl.rgbegr.wiring --- BEGIN
	enEvenAbufB <= '1' when (enEobufB='1' and fillBNotA='1') else '0';
	enEvenBbufB <= '1' when (enEobufB='1' and fillBNotA='0') else '0';

	aEobufB_vec <= std_logic_vector(to_unsigned(aEobufB, 10));

	drdEvenbufB <= drdEvenAbufB when fillBNotA='1' else drdEvenBbufB;

	rgbToManyAXIS_tvalid <= rgbToManyAXIS_tvalid_sig;
	rgbToManyAXIS_tdata <= rgbToManyAXIS_tdata_sig;
	rgbToManyAXIS_tlast <= rgbToManyAXIS_tlast_sig;
	-- IP impl.rgbegr.wiring --- END

	-- IP impl.rgbegr.wiring.cust --- RBEGIN

	-- even/odd buf B/read side

	-- sparse:
	-- enEobufB  100010000010000
	-- drdEobufB  000011111122222
	-- _tvalid     1010101010101010 1010
	-- qrs         0011223344556677

	-- full:
	-- enEobufB  10100100
	-- drdEobufB  00111222
	-- _tvalid     11111111 1111
	-- qrs       6701234567

	-- IP impl.rgbegr.wiring.cust --- REND

	stateRgbegr_dbg <= x"00" when stateRgbegr=stateRgbegrInit
				else x"10" when stateRgbegr=stateRgbegrIdle
				else x"20" when stateRgbegr=stateRgbegrLoad
				else x"30" when stateRgbegr=stateRgbegrRun
				else x"40" when stateRgbegr=stateRgbegrHold
				else x"50" when stateRgbegr=stateRgbegrEol
				else (others => '1');

	-- IP impl.rgbegr.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.rgbegr.vars --- RBEGIN
		variable col_lcl: natural range 0 to 2000;

		variable r_lcl: std_logic_vector(11 downto 0);
		variable g0_lcl: std_logic_vector(11 downto 0);
		variable g1_lcl: std_logic_vector(11 downto 0);
		variable g01_lcl: unsigned(12 downto 0);
		variable b_lcl: std_logic_vector(11 downto 0);
		variable gr_lcl: unsigned(13 downto 0);

		variable enEobufB_lcl: std_logic;
		-- IP impl.rgbegr.vars --- REND

	begin
		if reset='1' then
			-- IP impl.rgbegr.asyncrst --- BEGIN
			stateRgbegr <= stateRgbegrInit;
			qrs <= 0;
			enEobufB <= '0';
			aEobufB <= 0;
			drdEvenbufBm1 <= (others => '0');
			drdOddbufBm1 <= (others => '0');
			rgbToManyAXIS_tvalid_sig <= '0';
			rgbToManyAXIS_tdata_sig <= (others => '0');
			rgbToManyAXIS_tlast_sig <= '1';
			gr <= (others => '0');

			-- IP impl.rgbegr.asyncrst --- END
			-- IP impl.rgbegr.asyncrst.cust --- IBEGIN
			col_lcl := 0;
			r_lcl := (others => '0');
			g0_lcl := (others => '0');
			g1_lcl := (others => '0');
			g01_lcl := (others => '0');
			b_lcl := (others => '0');
			gr_lcl := (others => '0');
			enEobufB_lcl := '0';
			-- IP impl.rgbegr.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			if stateRgbegr=stateRgbegrInit then
				-- IP impl.rgbegr.syncrst --- BEGIN
				qrs <= 0;
				enEobufB <= '0';
				aEobufB <= 0;
				drdEvenbufBm1 <= (others => '0');
				drdOddbufBm1 <= (others => '0');
				rgbToManyAXIS_tvalid_sig <= '0';
				rgbToManyAXIS_tdata_sig <= (others => '0');
				rgbToManyAXIS_tlast_sig <= '1';
				gr <= (others => '0');

				-- IP impl.rgbegr.syncrst --- END
				-- IP impl.rgbegr.syncrst.cust --- IBEGIN
				col_lcl := 0;
				r_lcl := (others => '0');
				g0_lcl := (others => '0');
				g1_lcl := (others => '0');
				g01_lcl := (others => '0');
				b_lcl := (others => '0');
				gr_lcl := (others => '0');
				enEobufB_lcl := '0';
				-- IP impl.rgbegr.syncrst.cust --- IEND

				if vsync='1' then
					stateRgbegr <= stateRgbegrInit;

				else
					stateRgbegr <= stateRgbegrIdle;
				end if;

			elsif stateRgbegr=stateRgbegrIdle then
				if strbEgrstart='1' then
					enEobufB <= '1'; -- IP impl.rgbegr.idle.start --- ILINE

					stateRgbegr <= stateRgbegrLoad;
				end if;

			elsif stateRgbegr=stateRgbegrLoad then
				-- IP impl.rgbegr.load --- IBEGIN
				rgbToManyAXIS_tlast_sig <= '0';

				enEobufB <= '0';
				aEobufB <= aEobufB + 1;
				-- IP impl.rgbegr.load --- IEND

				stateRgbegr <= stateRgbegrRun;

			elsif stateRgbegr=stateRgbegrRun then
				-- IP impl.rgbegr.run.pre --- IBEGIN
				if qrs=0 then -- en at qrs 6
					r_lcl := drdEvenbufB(23 downto 12);
					g0_lcl := drdEvenbufB(11 downto 0);
					g1_lcl := drdOddbufB(23 downto 12);
					b_lcl := drdOddbufB(11 downto 0);
				elsif qrs=1 then
					r_lcl := drdEvenbufB(47 downto 36);
					g0_lcl := drdEvenbufB(35 downto 24);
					g1_lcl := drdOddbufB(47 downto 36);
					b_lcl := drdOddbufB(35 downto 24);
				elsif qrs=2 then -- en at qrs 0
					r_lcl := drdEvenbufB(7 downto 0) & drdEvenbufBm1(63 downto 60);
					g0_lcl := drdEvenbufBm1(59 downto 48);
					g1_lcl := drdOddbufB(7 downto 0) & drdOddbufBm1(63 downto 60);
					b_lcl := drdOddbufBm1(59 downto 48);
				elsif qrs=3 then
					r_lcl := drdEvenbufB(31 downto 20);
					g0_lcl := drdEvenbufB(19 downto 8);
					g1_lcl := drdOddbufB(31 downto 20);
					b_lcl := drdOddbufB(19 downto 8);
				elsif qrs=4 then
					r_lcl := drdEvenbufB(55 downto 44);
					g0_lcl := drdEvenbufB(43 downto 32);
					g1_lcl := drdOddbufB(55 downto 44);
					b_lcl := drdOddbufB(43 downto 32);
				elsif qrs=5 then -- en at qrs 3
					r_lcl := drdEvenbufB(15 downto 4);
					g0_lcl := drdEvenbufB(3 downto 0) & drdEvenbufBm1(63 downto 56);
					g1_lcl := drdOddbufB(15 downto 4);
					b_lcl := drdOddbufB(3 downto 0) & drdOddbufBm1(63 downto 56);
				elsif qrs=6 then
					r_lcl := drdEvenbufB(39 downto 28);
					g0_lcl := drdEvenbufB(27 downto 16);
					g1_lcl := drdOddbufB(39 downto 28);
					b_lcl := drdOddbufB(27 downto 16);
				elsif qrs=7 then
					r_lcl := drdEvenbufB(63 downto 52);
					g0_lcl := drdEvenbufB(51 downto 40);
					g1_lcl := drdOddbufB(63 downto 52);
					b_lcl := drdOddbufB(51 downto 40);
				end if;

				g01_lcl := resize(unsigned(g0_lcl), 13) + resize(unsigned(g1_lcl), 13);
				rgbToManyAXIS_tdata_sig <= r_lcl & std_logic_vector(g01_lcl(12 downto 1)) & b_lcl;

				gr_lcl := resize(unsigned(r_lcl), 14) + resize(unsigned(g0_lcl), 14) + resize(unsigned(g1_lcl), 14) + resize(unsigned(b_lcl), 14);
				gr <= std_logic_vector(gr_lcl(13 downto 2));

				if qrs=6 or qrs=0 or qrs=3 then
					enEobufB_lcl := '1';

					drdEvenbufBm1 <= drdEvenbufB;
					drdOddbufBm1 <= drdOddbufB;

				else
					enEobufB_lcl := '0';
				end if;

				if qrs=7 or qrs=1 or qrs=4 then
					aEobufB <= aEobufB + 1;
				end if;

				if qrs=7 then
					qrs <= 0;
				else
					qrs <= qrs + 1;
				end if;

				rgbToManyAXIS_tvalid_sig <= '1';

				col_lcl := col_lcl + 1; -- in next clock cycle
				-- IP impl.rgbegr.run.pre --- IEND

				if col_lcl=unsigned(NCol) then
					rgbToManyAXIS_tlast_sig <= '1'; -- IP impl.rgbegr.run.rowDone --- ILINE

					stateRgbegr <= stateRgbegrEol;

				else
					if sprsNotFull='0' then
						enEobufB <= enEobufB_lcl; -- IP impl.rgbegr.run.nextCol --- ILINE

						stateRgbegr <= stateRgbegrRun;

					else
						enEobufB <= '0'; -- IP impl.rgbegr.run.wait --- ILINE

						stateRgbegr <= stateRgbegrHold;
					end if;
				end if;

			elsif stateRgbegr=stateRgbegrHold then
				-- IP impl.rgbegr.hold --- IBEGIN
				enEobufB <= enEobufB_lcl;
				rgbToManyAXIS_tvalid_sig <= '0';
				-- IP impl.rgbegr.hold --- IEND

				stateRgbegr <= stateRgbegrRun;

			elsif stateRgbegr=stateRgbegrEol then
				rgbToManyAXIS_tvalid_sig <= '0'; -- IP impl.rgbegr.eol.pre --- ILINE

				if vsync='1' then
					stateRgbegr <= stateRgbegrInit;

				else
					-- IP impl.rgbegr.eol.nextRow --- IBEGIN
					qrs <= 0;

					enEobufB <= '0';
					aEobufB <= 0;

					col_lcl := 0;
					-- IP impl.rgbegr.eol.nextRow --- IEND

					stateRgbegr <= stateRgbegrIdle;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.rgbegr.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;


-- file Freqprobe_v1_0_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Freqprobe_v1_0_8c100ea18901433eb4f7c0fdbf115e06 module implementation
-- author: Alexander Wirthmueller
-- copyright: (C) 2020 MPSI Technologies GmbH
-- date created: 6 Jan 2020
-- date modified: 4 Feb 2020
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Freqprobe_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
	generic (
		fMclk: natural := 50000 -- in kHz
	);
	port (
		reset: in std_logic;
		mclk: in std_logic;

		bcdNotHex: in std_logic;

		capt: in std_logic_vector(15 downto 0);
		
		freq: out std_logic
	);
end Freqprobe_v1_0_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Freqprobe_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpLoad,
		stateOpStep,
		stateOpRun
	);
	signal stateOp: stateOp_t;

	signal freq_sig: std_logic;

begin

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	freq <= freq_sig;

	process (reset, mclk, stateOp)
		-- assume abcd (four nibbles, least significant / fastest: d)
		variable abcd: natural range 0 to 4; -- 4 invalid

		constant amax: natural := fMclk/2; -- 500us wait for thousands
		constant bmax: natural := fMclk/10/2; -- 50us wait for hundreds
		constant cmax: natural := fMclk/100/2; -- 5us wait for tens
		constant dmax: natural := fMclk/1000/2; -- 500ns wait for ones

		variable bcdNotHex_lcl: boolean;
		variable capt_lcl_init: std_logic_vector(15 downto 0);
		variable capt_lcl: std_logic_vector(15 downto 0);

		variable cnt: natural range 0 to 65535; -- compatibility with hex and with (wrong) BCD values A..F
		variable i: natural range 0 to amax;

	begin
		if reset='1' then
			stateOp <= stateOpInit;

			freq_sig <= '0';
			
			abcd := 0;
			bcdNotHex_lcl := false;
			capt_lcl_init := (others => '0');
			capt_lcl := (others => '0');
			cnt := 0;
			i := 0;

		elsif rising_edge(mclk) then
			if stateOp=stateOpInit then
				freq_sig <= '0';
				
				abcd := 0;
				bcdNotHex_lcl := false;
				capt_lcl_init := (others => '0');
				capt_lcl := (others => '0');
				cnt := 0;
				i := 0;

				stateOp <= stateOpLoad;

			elsif stateOp=stateOpLoad then
				freq_sig <= '0';
				
				bcdNotHex_lcl := (bcdNotHex='1');

				capt_lcl_init := capt;
				capt_lcl := capt_lcl_init;

				if capt_lcl_init/=x"0000" then
					stateOp <= stateOpStep;
				end if;

			elsif stateOp=stateOpStep then
				if not bcdNotHex_lcl and capt_lcl/=x"0000" then
					abcd := 3;
				elsif capt_lcl(15 downto 12)/="0000" then
					abcd := 0;
				elsif capt_lcl(11 downto 8)/="0000" then
					abcd := 1;
				elsif capt_lcl(7 downto 4)/="0000" then
					abcd := 2;
				elsif capt_lcl(3 downto 0)/="0000" then
					abcd := 3;
				else
					abcd := 4;
				end if;

				if abcd=4 then
					if freq_sig='0' then
						freq_sig <= '1';

						capt_lcl := capt_lcl_init;

						stateOp <= stateOpStep;

					else
						stateOp <= stateOpLoad;
					end if;

				else
					cnt := 0;
					i := 0;

					stateOp <= stateOpRun;
				end if;

			elsif stateOp=stateOpRun then
				i := i + 1;

				if (abcd=0 and i=amax) or (abcd=1 and i=bmax) or (abcd=2 and i=cmax) or (abcd=3 and i=dmax) then
					i := 0;

					cnt := cnt + 1;

					if not bcdNotHex_lcl and cnt>=to_integer(unsigned(capt_lcl)) then
						capt_lcl := (others => '0');
						stateOp <= stateOpStep;
					
					elsif abcd=0 and cnt>=to_integer(unsigned(capt_lcl(15 downto 12))) then
						capt_lcl(15 downto 12) := (others => '0');
						stateOp <= stateOpStep;

					elsif abcd=1 and cnt>=to_integer(unsigned(capt_lcl(11 downto 8))) then
						capt_lcl(11 downto 8) := (others => '0');
						stateOp <= stateOpStep;

					elsif abcd=2 and cnt>=to_integer(unsigned(capt_lcl(7 downto 4))) then
						capt_lcl(7 downto 4) := (others => '0');
						stateOp <= stateOpStep;

					elsif bcdNotHex_lcl and abcd=3 and cnt>=to_integer(unsigned(capt_lcl(3 downto 0))) then
						capt_lcl(3 downto 0) := (others => '0');
						stateOp <= stateOpStep;
					end if;
				end if;
			end if;
		end if;
	end process;

end Rtl;


-- file Sprsaxisfwd_v1_0_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Sprsaxisfwd_v1_0_8c100ea18901433eb4f7c0fdbf115e06 module implementation
-- copyright: (C) 2024 MPSI Technologies GmbH
-- author: Alexander Wirthmueller
-- date created: 17 Nov 2024
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Sprsaxisfwd_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is
	generic (
		wSize: natural range 3 to 16 := 12;
		wIxHshk: natural range 4 to 8 := 4;
		wIxData: natural range 2 to 6 := 4;
		wData: natural range 8 to 256 := 64;
		wUser: natural range 1 to 96 := 6
	);
	port (
		resetIgrclk: in std_logic; -- in mclk domain
		igrclk: in std_logic;

		reset: in std_logic;
		mclk: in std_logic;

		igrAXIS_tready: out std_logic; -- always 1
		igrAXIS_tvalid: in std_logic;
		igrAXIS_tdata: in std_logic_vector(wData-1 downto 0);
		igrAXIS_tkeep: in std_logic_vector(wData/8-1 downto 0);
		igrAXIS_tlast: in std_logic;
		igrAXIS_tuser: in std_logic_vector(wUser-1 downto 0);

		enEgr: in std_logic;

		egrAXIS_tready: in std_logic;
		egrAXIS_tvalid: out std_logic;
		egrAXIS_tdata: out std_logic_vector(wData-1 downto 0);
		egrAXIS_tkeep: out std_logic_vector(wData/8-1 downto 0);
		egrAXIS_tlast: out std_logic;
		egrAXIS_tuser: out std_logic_vector(wUser-1 downto 0)
	);
end Sprsaxisfwd_v1_0_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Sprsaxisfwd_v1_0_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant size: natural := 2**wSize;
	constant sizeIxHshk: natural := 2**wIxHshk;
	constant sizeIxData: natural := 2**wIxData;

	---- AXI stream egress (egr)
	type stateEgr_t is (
		stateEgrInit,
		stateEgrIdle,
		stateEgrWait,
		stateEgrRun,
		stateEgrDone
	);
	signal stateEgr: stateEgr_t := stateEgrInit;

	signal egrAXIS_tvalid_sig: std_logic;
	signal egrAXIS_tdata_sig: std_logic_vector(wData-1 downto 0);
	signal egrAXIS_tkeep_sig: std_logic_vector(wData/8-1 downto 0);
	signal egrAXIS_tlast_sig: std_logic;
	signal egrAXIS_tuser_sig: std_logic_vector(wUser-1 downto 0);

	signal ixDataRd: natural range 0 to sizeIxData-1; -- next position to read from
	signal lenHshkRd: std_logic_vector(wSize-1 downto 0); -- last wIxHshk bits: next position to read from

	signal strbEgrDone: std_logic;

	---- AXI stream ingress (igr)
	type stateIgr_t is (
		stateIgrInit,
		stateIgrIdle,
		stateIgrRun,
		stateIgrDone
	);
	signal stateIgr: stateIgr_t := stateIgrInit;

	type dataitem_t is record
		tdata: std_logic_vector(wData-1 downto 0);
		tkeep: std_logic_vector(wData/8-1 downto 0);
		tuser: std_logic_vector(wUser-1 downto 0);
	end record dataitem_t;

	type data_t is array (0 to sizeIxData-1) of dataitem_t;
	signal data: data_t;

	type hshkitem_t is record
		tvalid: std_logic;
		tlast: std_logic;
	end record hshkitem_t;

	type hshk_t is array (0 to sizeIxHshk-1) of hshkitem_t;
	signal hshk: hshk_t;

	signal ixDataWr: natural range 0 to sizeIxData-1; -- next position to write to
	signal lenHshkWr: std_logic_vector(wSize-1 downto 0); -- last wIxHshk bits: next position to write to

	signal strbIgrStart: std_logic;

	---- handshake

	---- igrclk to mclk CDC sampling (igrclkToMclkSample)

	signal strbIgrStart_mclk: std_logic;
	signal strbIgrStart_to_mclkm1: std_logic;

	---- igrclk to mclk CDC stretching (igrclkToMclkStretch)

	signal strbIgrStart_to_mclk: std_logic;

	---- mclk to igrclk CDC sampling (mclkToIgrclkSample)

	signal strbEgrDone_igrclk: std_logic;
	signal strbEgrDone_to_igrclkm1: std_logic;

	---- mclk to igrclk CDC stretching (mclkToIgrclkStretch)

	signal strbEgrDone_to_igrclk: std_logic;

	------------------------------------------------------------------------
	-- documentation
	------------------------------------------------------------------------

	-- unstable ingress sparse AXI stream forwarder with no back-pressure allowed

	-- assumes fIgrclk approx. fMclk with unreliable igrclk including loss of igrclk or sudden fIgrclk change
	-- sizeHshk to be chosen such that +/- sizeIxHshk clocks delta during transaction can be compensated

	-- for fIgrclk approx. fIgrclk / 2,3,4, ..., egrAXIS_tready can be used to throttle egress

	-- sparsity: fewer data slots (sizeIxData) than handshake slots (sizeIxHshk, each clock) available

	-- egr (mclk) side assumes role of stable monitor:
	-- a. triggers (non-conflicting) read sizeIxHshk/2 clocks behind write
	-- b. invalidates transaction and triggers reset if igr restarts while egr is still running
	-- c. faulty transaction for fMclk < fIgrclk cannot be avoided

begin

	------------------------------------------------------------------------
	-- implementation: AXI stream egress (egr)
	------------------------------------------------------------------------

	egrAXIS_tvalid <= egrAXIS_tvalid_sig;
	egrAXIS_tdata <= egrAXIS_tdata_sig;
	egrAXIS_tkeep <= egrAXIS_tkeep_sig;
	egrAXIS_tlast <= egrAXIS_tlast_sig;
	egrAXIS_tuser <= egrAXIS_tuser_sig;

	process (reset, mclk)
		variable ixHshkRd: natural range 0 to sizeIxHshk-1;

		constant imax: natural := sizeIxHshk/2;
		variable i: natural range 0 to imax;

	begin
		if reset='1' then
			stateEgr <= stateEgrInit;
			egrAXIS_tvalid_sig <= '0';
			egrAXIS_tdata_sig <= (others => '0');
			egrAXIS_tkeep_sig <= (others => '0');
			egrAXIS_tlast_sig <= '1';
			egrAXIS_tuser_sig <= (others => '0');

			ixDataRd <= 0;
			lenHshkRd <= (others => '0');

			strbEgrDone <= '0';

			ixHshkRd := 0;
			i := 0;
		
		elsif rising_edge(mclk) then
			if stateEgr=stateEgrInit then
				egrAXIS_tvalid_sig <= '0';
				egrAXIS_tdata_sig <= (others => '0');
				egrAXIS_tkeep_sig <= (others => '0');
				egrAXIS_tlast_sig <= '1';
				egrAXIS_tuser_sig <= (others => '0');

				ixDataRd <= 0;
				lenHshkRd <= (others => '0');

				strbEgrDone <= '0';

				ixHshkRd := 0;
				i := 0;

				if resetIgrclk='0' then
					stateEgr <= stateEgrIdle;
				else
					stateEgr <= stateEgrInit;
				end if;

			elsif stateEgr=stateEgrIdle then
				if strbIgrStart_mclk='1' then
					stateEgr <= stateEgrWait;
				end if;

			elsif stateEgr=stateEgrWait then
				-- account for strbIgrStart CDC and other delays 
				if i=imax-4-2 then
					if enEgr='1' then
						stateEgr <= stateEgrRun;
					end if;

				else
					i := i + 1;

					stateEgr <= stateEgrWait;
				end if;

			elsif stateEgr=stateEgrRun then
				ixHshkRd := to_integer(unsigned(lenHshkRd(wIxHshk-1 downto 0)));

				if hshk(ixHshkRd).tvalid='1' then
					egrAXIS_tdata_sig <= data(ixDataRd).tdata;
					egrAXIS_tkeep_sig <= data(ixDataRd).tkeep;
					egrAXIS_tuser_sig <= data(ixDataRd).tuser;

					if enEgr='1' then
						if ixDataRd=sizeIxData-1 then
							ixDataRd <= 0;
						else
							ixDataRd <= ixDataRd + 1;
						end if;
					end if;
				end if;

				if hshk(ixHshkRd).tlast='1' or unsigned(lenHshkRd)=size-1 then
					egrAXIS_tvalid_sig <= hshk(ixHshkRd).tvalid;
					egrAXIS_tlast_sig <= hshk(ixHshkRd).tlast;

					strbEgrDone <= '1';

					stateEgr <= stateEgrDone;

				elsif resetIgrclk='1' or strbIgrStart_mclk='1' then
					egrAXIS_tvalid_sig <= '0';
					egrAXIS_tlast_sig <= '1';

					strbEgrDone <= '1';

					stateEgr <= stateEgrDone;

				else
					egrAXIS_tvalid_sig <= hshk(ixHshkRd).tvalid;
					egrAXIS_tlast_sig <= hshk(ixHshkRd).tlast;

					if enEgr='1' then
						lenHshkRd <= std_logic_vector(unsigned(lenHshkRd) + 1);
					end if;

					stateEgr <= stateEgrRun;
				end if;

			elsif stateEgr=stateEgrDone then
				strbEgrDone <= '0';

				if enEgr='1' then
					egrAXIS_tvalid_sig <= '0';

					stateEgr <= stateEgrInit;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: AXI stream ingress (igr)
	------------------------------------------------------------------------

	igrAXIS_tready <= '1';

	process (resetIgrclk, igrclk)
		variable ixHshkWr: natural range 0 to sizeIxHshk-1;
		
		constant imax: natural := sizeIxHshk/2;
		variable i: natural range 0 to imax;

	begin
		if resetIgrclk='1' then
			stateIgr <= stateIgrInit;
			for i in 0 to sizeIxData-1 loop
				data(i).tdata <= (others => '0');
				data(i).tkeep <= (others => '0');
				data(i).tuser <= (others => '0');
			end loop;
			for i in 0 to sizeIxHshk-1 loop
				hshk(i).tvalid <= '0';
				hshk(i).tlast <= '1';
			end loop;
			ixDataWr <= 0;
			lenHshkWr <= (others => '0');
			strbIgrStart <= '0';

			ixHshkWr := 0;
			i := 0;

		elsif rising_edge(igrclk) then
			if stateIgr=stateIgrInit or strbEgrDone_igrclk='1' then
				for i in 0 to sizeIxData-1 loop
					data(i).tdata <= (others => '0');
					data(i).tkeep <= (others => '0');
					data(i).tuser <= (others => '0');
				end loop;
				for i in 0 to sizeIxHshk-1 loop
					hshk(i).tvalid <= '0';
					hshk(i).tlast <= '1';
				end loop;
				ixDataWr <= 0;
				lenHshkWr <= (others => '0');
				strbIgrStart <= '0';

				ixHshkWr := 0;
				i := 0;

				if igrAXIS_tvalid='0' and igrAXIS_tlast='1' then
					stateIgr <= stateIgrIdle;
				else
					stateIgr <= stateIgrInit;
				end if;

			elsif stateIgr=stateIgrIdle then
				if igrAXIS_tvalid='1' then
					data(0).tdata <= igrAXIS_tdata;
					data(0).tkeep <= igrAXIS_tkeep;
					data(0).tuser <= igrAXIS_tuser;
					hshk(0).tvalid <= igrAXIS_tvalid;
					hshk(0).tlast <= igrAXIS_tlast;

					ixDataWr <= ixDataWr + 1;
					lenHshkWr <= std_logic_vector(unsigned(lenHshkWr) + 1);

					strbIgrStart <= '1';

					if igrAXIS_tlast='0' then
						stateIgr <= stateIgrRun;

					else
						i := 0;

						stateIgr <= stateIgrDone;
					end if;
				end if;

			elsif stateIgr=stateIgrRun then
				strbIgrStart <= '0';

				ixHshkWr := to_integer(unsigned(lenHshkWr(wIxHshk-1 downto 0)));

				hshk(ixHshkWr).tvalid <= igrAXIS_tvalid;
				hshk(ixHshkWr).tlast <= igrAXIS_tlast;

				if igrAXIS_tvalid='1' then
					data(ixDataWr).tdata <= igrAXIS_tdata;
					data(ixDataWr).tkeep <= igrAXIS_tkeep;
					data(ixDataWr).tuser <= igrAXIS_tuser;

					if ixDataWr=sizeIxData-1 then
						ixDataWr <= 0;
					else
						ixDataWr <= ixDataWr + 1;
					end if;
				end if;

				if igrAXIS_tlast='1' or unsigned(lenHshkWr)=size-1 then
					i := 0;

					stateIgr <= stateIgrDone;

				else
					lenHshkWr <= std_logic_vector(unsigned(lenHshkWr) + 1);

					stateIgr <= stateIgrRun;
				end if;

			elsif stateIgr=stateIgrDone then
				strbIgrStart <= '0';

				if i=imax then
					-- timeout; else leave via strbEgrDone_igrclk
					stateIgr <= stateIgrInit;

				else
					i := i + 1;

					stateIgr <= stateIgrDone;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: igrclk to mclk CDC sampling (igrclkToMclkSample)
	------------------------------------------------------------------------

	process (reset, mclk)
		variable strbIgrStart_wait: boolean;

	begin
		if reset ='1' then
			strbIgrStart_mclk <= '1';
			strbIgrStart_to_mclkm1 <= '1';

			strbIgrStart_wait := false;

		elsif rising_edge(mclk) then
			if strbIgrStart_mclk='1' then
				strbIgrStart_mclk <= '0';
			elsif strbIgrStart_to_mclkm1='1' and not strbIgrStart_wait then
				strbIgrStart_mclk <= '1';
				strbIgrStart_wait := true;
			end if;
			if strbIgrStart_to_mclkm1='0' and strbIgrStart_wait then
				strbIgrStart_wait := false;
			end if;
			strbIgrStart_to_mclkm1 <= strbIgrStart_to_mclk;

		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: igrclk to mclk CDC stretching (igrclkToMclkStretch)
	------------------------------------------------------------------------

	process (resetIgrclk, igrclk)
		constant imax: natural := 1;

		variable strbIgrStart_i: natural range 0 to imax;

	begin
		if resetIgrclk ='1' then
			strbIgrStart_to_mclk <= '1';

			strbIgrStart_i := 0;

		elsif rising_edge(igrclk) then
			if strbIgrStart='1' then
				strbIgrStart_to_mclk <= '1';
				strbIgrStart_i := 0;
			elsif strbIgrStart_i=imax then
				strbIgrStart_to_mclk <= '0';
			else
				strbIgrStart_i := strbIgrStart_i + 1;
			end if;

		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: mclk to igrclk CDC sampling (mclkToIgrclkSample)
	------------------------------------------------------------------------

	process (resetIgrclk, igrclk)
		variable strbEgrDone_wait: boolean;

	begin
		if resetIgrclk='1' then
			strbEgrDone_igrclk <= '1';
			strbEgrDone_to_igrclkm1 <= '1';

			strbEgrDone_wait := false;

		elsif rising_edge(igrclk) then
			if strbEgrDone_igrclk='1' then
				strbEgrDone_igrclk <= '0';
			elsif strbEgrDone_to_igrclkm1='1' and not strbEgrDone_wait then
				strbEgrDone_igrclk <= '1';
				strbEgrDone_wait := true;
			end if;
			if strbEgrDone_to_igrclkm1='0' and strbEgrDone_wait then
				strbEgrDone_wait := false;
			end if;
			strbEgrDone_to_igrclkm1 <= strbEgrDone_to_igrclk;

		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: mclk to igrclk CDC stretching (mclkToIgrclkStretch)
	------------------------------------------------------------------------

	process (reset, mclk)
		constant imax: natural := 1;

		variable strbEgrDone_i: natural range 0 to imax;

	begin
		if reset='1' then
			strbEgrDone_to_igrclk <= '1';

			strbEgrDone_i := 0;

		elsif rising_edge(mclk) then
			if strbEgrDone='1' then
				strbEgrDone_to_igrclk <= '1';
				strbEgrDone_i := 0;
			elsif strbEgrDone_i=imax then
				strbEgrDone_to_igrclk <= '0';
			else
				strbEgrDone_i := strbEgrDone_i + 1;
			end if;
		end if;
	end process;

end Rtl;


-- file Vidtrack_8c100ea18901433eb4f7c0fdbf115e06.vhd
-- Vidtrack_8c100ea18901433eb4f7c0fdbf115e06 fsmtrack_Easy_v1_0 easy model debug controller implementation
-- copyright: (C) 2023 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 1 Apr 2026
-- IP header --- ABOVE

-- module parameters:
-- trkclk (clock): mclk
-- ratioTrkclk (clock ratio wrt. master clock): 1
-- capts (FSM's to be captured): videoin.igr;videoin.rgbegr;decim.stream;decim.store
-- trigs (triggers): trigA;trigB;trigC;trigD
-- sizeSeqbuf (sequence buffer size [kB]): 4

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Vidtrack_8c100ea18901433eb4f7c0fdbf115e06 is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		trigA: in std_logic;
		trigB: in std_logic;
		trigC: in std_logic;
		trigD: in std_logic;

		getInfoTixVState: out std_logic_vector(7 downto 0);
		getInfoTCapt: out std_logic_vector(31 downto 0);
		getInfoPtr0Seqbuf: out std_logic_vector(15 downto 0);

		reqInvSelect: in std_logic;
		ackInvSelect: out std_logic;

		selectTixVCapture: in std_logic_vector(7 downto 0);
		selectStaTixVTrigger: in std_logic_vector(7 downto 0);
		selectStaFallingNotRising: in std_logic_vector(7 downto 0);
		selectStoTixVTrigger: in std_logic_vector(7 downto 0);
		selectStoFallingNotRising: in std_logic_vector(7 downto 0);

		reqInvSet: in std_logic;
		ackInvSet: out std_logic;

		setRng: in std_logic_vector(7 downto 0);
		setTCaptMax: in std_logic_vector(31 downto 0);

		reqSeqbufToHostif: in std_logic;
		ackSeqbufToHostif: out std_logic;
		dneSeqbufToHostif: in std_logic;
		avllenSeqbufToHostif: out std_logic_vector(31 downto 0);

		seqbufToHostifAXIS_tready: in std_logic;
		seqbufToHostifAXIS_tvalid: out std_logic;
		seqbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
		seqbufToHostifAXIS_tlast: out std_logic;

		videoinStateIgr: in std_logic_vector(7 downto 0);
		videoinStateRgbegr: in std_logic_vector(7 downto 0);
		decimStateStream: in std_logic_vector(7 downto 0);
		decimStateStore: in std_logic_vector(7 downto 0)
	);
end Vidtrack_8c100ea18901433eb4f7c0fdbf115e06;

architecture Rtl of Vidtrack_8c100ea18901433eb4f7c0fdbf115e06 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_size4kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(9 downto 0);
			drdA: out std_logic_vector(31 downto 0);
			dwrA: in std_logic_vector(31 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(9 downto 0);
			drdB: out std_logic_vector(31 downto 0);
			dwrB: in std_logic_vector(31 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant wD: natural := 32;
	constant logWD: natural := 2;

	constant sizeSeqbuf: natural := 4096;
	constant logSizeSeqbuf: natural := 12;

	constant tixVCaptureVideoinIgr: std_logic_vector(7 downto 0) := x"01";
	constant tixVCaptureVideoinRgbegr: std_logic_vector(7 downto 0) := x"02";
	constant tixVCaptureDecimStream: std_logic_vector(7 downto 0) := x"03";
	constant tixVCaptureDecimStore: std_logic_vector(7 downto 0) := x"04";

	constant tixVStateIdle: std_logic_vector(7 downto 0) := x"00";
	constant tixVStateArm: std_logic_vector(7 downto 0) := x"01";
	constant tixVStateAcq: std_logic_vector(7 downto 0) := x"02";
	constant tixVStateDone: std_logic_vector(7 downto 0) := x"03";

	constant tixVTriggerVoid: std_logic_vector(7 downto 0) := x"00";
	constant tixVTriggerTrigA: std_logic_vector(7 downto 0) := x"02";
	constant tixVTriggerTrigB: std_logic_vector(7 downto 0) := x"03";
	constant tixVTriggerTrigC: std_logic_vector(7 downto 0) := x"04";
	constant tixVTriggerTrigD: std_logic_vector(7 downto 0) := x"05";

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv,
		stateOpIdle,
		stateOpStart,
		stateOpRun,
		stateOpStop,
		stateOpClear
	);
	signal stateOp: stateOp_t;

	signal ackInvSelect_sig: std_logic;
	signal ackInvSet_sig: std_logic;

	signal tixVCapture: std_logic_vector(7 downto 0);

	signal staTixVTrigger: std_logic_vector(7 downto 0);
	signal staFallingNotRising: boolean;

	signal stoTixVTrigger: std_logic_vector(7 downto 0);
	signal stoFallingNotRising: boolean;

	signal strbStart: std_logic;
	signal strbStop: std_logic;

	---- sequence operation (seq)
	type stateSeq_t is (
		stateSeqInit,
		stateSeqIdle,
		stateSeqRun,
		stateSeqDone,
		stateSeqClear,
		stateSeqAckClear
	);
	signal stateSeq: stateSeq_t;

	signal rdySeq: std_logic;
	signal dneSeq: std_logic;

	signal TCapt: std_logic_vector(31 downto 0);

	signal ptr0SeqbufTrackNotFixed: std_logic;
	signal ptr0Seqbuf: natural range 0 to sizeSeqbuf/4-1;

	signal enSeqbuf: std_logic;

	signal aSeqbuf: natural range 0 to sizeSeqbuf/4-1;
	signal aSeqbuf_vec: std_logic_vector(logSizeSeqbuf-2-1 downto 0);

	signal dwrSeqbuf: std_logic_vector(31 downto 0);

	---- sequence buffer B/hostif-facing operation (seqbufB)
	type stateSeqbufB_t is (
		stateSeqbufBInit,
		stateSeqbufBIdle,
		stateSeqbufBXferA, stateSeqbufBXferB,
		stateSeqbufBDone,
		stateSeqbufBClear
	);
	signal stateSeqbufB: stateSeqbufB_t;

	signal enSeqbufB: std_logic;

	signal aSeqbufB: natural range 0 to sizeSeqbuf/(wD/8)-1;
	signal aSeqbufB_vec: std_logic_vector(logSizeSeqbuf-logWD-1 downto 0);

	---- sampling operation (sample)
	signal state: std_logic_vector(7 downto 0);

	signal start: std_logic;
	signal stop: std_logic;

	---- handshake

	-- op to (many)
	signal reqOpClear: std_logic;

	-- seqbufB to seq
	signal reqSeqbufBToSeqClear: std_logic;
	signal ackSeqbufBToSeqClear: std_logic;

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	mySeqbuf : Dpbram_size4kB_a32b32_8c100ea18901433eb4f7c0fdbf115e06
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enSeqbuf,
			weA => '1',

			aA => aSeqbuf_vec,
			drdA => open,
			dwrA => dwrSeqbuf,

			rstB => reset,
			clkB => mclk,

			enB => enSeqbufB,
			weB => '0',

			aB => aSeqbufB_vec,
			drdB => seqbufToHostifAXIS_tdata,
			dwrB => (others => '0')
		);

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	ackInvSelect <= ackInvSelect_sig;
	ackInvSet <= ackInvSet_sig;

	getInfoTixVState <= tixVStateArm when stateOp=stateOpIdle
				else tixVStateAcq when stateOp=stateOpRun
				else tixVStateDone when stateOp=stateOpStop
				else tixVStateIdle;
	getInfoTCapt <= TCapt;
	getInfoPtr0Seqbuf <= std_logic_vector(to_unsigned(ptr0Seqbuf, 16));

	strbStart <= '1' when stateOp=stateOpStart else '0';

	reqOpClear <= '1' when stateOp=stateOpClear else '0';

	process (reset, mclk, stateOp)
		variable rng: boolean;
		variable restart: boolean;

		variable TCaptMax: std_logic_vector(31 downto 0);

		variable strb_last: std_logic;

	begin
		if reset='1' then
			stateOp <= stateOpInit;
			ackInvSelect_sig <= '0';
			ackInvSet_sig <= '0';
			tixVCapture <= x"01";
			staTixVTrigger <= tixVTriggerVoid;
			staFallingNotRising <= false;
			stoTixVTrigger <= tixVTriggerVoid;
			stoFallingNotRising <= false;
			strbStop <= '0';

			rng := false;
			restart := false;
			TCaptMax := (others => '0');
			strb_last := '0';

		elsif rising_edge(mclk) then
			if stateOp=stateOpInit or (stateOp/=stateOpInv and (reqInvSelect='1' or reqInvSet='1'))  then
				strbStop <= '0';

				if reqInvSelect='1' then
					tixVCapture <= selectTixVCapture;
					staTixVTrigger <= selectStaTixVTrigger;
					staFallingNotRising <= (selectStaFallingNotRising=tru8);
					stoTixVTrigger <= selectStoTixVTrigger;
					stoFallingNotRising <= (selectStoFallingNotRising=tru8);

					ackInvSelect_sig <= '1';
					stateOp <= stateOpInv;

				elsif reqInvSet='1' then
					if setRng=tru8 then
						rng := true;
					else
						rng := false;
					end if;
					TCaptMax := setTCaptMax;

					ackInvSet_sig <= '1';
					stateOp <= stateOpInv;

				else
					restart := false;

					if rng then
						strb_last := start;

						stateOp <= stateOpIdle;

					else
						stateOp <= stateOpInit;
					end if;
				end if;

			elsif stateOp=stateOpInv then
				if (reqInvSet='0' and ackInvSet_sig='1') or (reqInvSelect='0' and ackInvSelect_sig='1') then
					ackInvSet_sig <= '0';
					ackInvSelect_sig <= '0';

					strbStop <= '1';

					restart := true;

					stateOp <= stateOpStop;
				end if;

			elsif stateOp=stateOpIdle then
				if staTixVTrigger=tixVTriggerVoid or (not staFallingNotRising and strb_last='0' and start='1') or (staFallingNotRising and strb_last='1' and start='0') then
					stateOp <= stateOpStart;
				else
					strb_last := start;
				end if;

			elsif stateOp=stateOpStart then -- strbStart='1'
				strb_last := stop;

				stateOp <= stateOpRun;

			elsif stateOp=stateOpRun then
				if (stoTixVTrigger=tixVTriggerVoid and unsigned(TCaptMax)/=0 and (unsigned(TCapt)>=unsigned(TCaptMax) or dneSeq='1')) or unsigned(TCapt)>=x"FFFFFF00" or (not stoFallingNotRising and strb_last='0' and stop='1') or (stoFallingNotRising and strb_last='1' and stop='0') then
					strbStop <= '1';

					stateOp <= stateOpStop;

				else
					strb_last := stop;
				end if;

			elsif stateOp=stateOpStop then
				strbStop <= '0';

				if restart then
					stateOp <= stateOpClear;

				else
					if rdySeq='1' then
						stateOp <= stateOpInit;
					end if;
				end if;

			elsif stateOp=stateOpClear then -- reqOpClear='1'
				if rdySeq='1' then
					stateOp <= stateOpInit;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: sampling operation (sample)
	------------------------------------------------------------------------

	process (reset, mclk)

	begin
		if reset='1' then
			state <= (others => '1');
			start <= '0';
			stop <= '0';

		elsif rising_edge(mclk) then
			case tixVCapture is
				when tixVCaptureVideoinIgr =>
					state <= videoinStateIgr;
				when tixVCaptureVideoinRgbegr =>
					state <= videoinStateRgbegr;
				when tixVCaptureDecimStream =>
					state <= decimStateStream;
				when tixVCaptureDecimStore =>
					state <= decimStateStore;
				when others =>
					state <= (others => '1');
			end case;

			case staTixVTrigger is
				when tixVTriggerTrigA =>
					start <= trigA;
				when tixVTriggerTrigB =>
					start <= trigB;
				when tixVTriggerTrigC =>
					start <= trigC;
				when tixVTriggerTrigD =>
					start <= trigD;
				when others =>
					start <= '0';
			end case;

			case stoTixVTrigger is
				when tixVTriggerTrigA =>
					stop <= trigA;
				when tixVTriggerTrigB =>
					stop <= trigB;
				when tixVTriggerTrigC =>
					stop <= trigC;
				when tixVTriggerTrigD =>
					stop <= trigD;
				when others =>
					stop <= '0';
			end case;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: sequence operation (seq)
	------------------------------------------------------------------------

	rdySeq <= '1' when stateSeq=stateSeqIdle else '0';
	dneSeq <= '1' when stateSeq=stateSeqDone else '0';

	ptr0Seqbuf <= aSeqbuf when ptr0SeqbufTrackNotFixed='1' else 0;

	aSeqbuf_vec <= std_logic_vector(to_unsigned(aSeqbuf, logSizeSeqbuf-2));

	ackSeqbufBToSeqClear <= '1' when stateSeq=stateSeqAckClear else '0';

	process (reset, mclk, stateSeq)
		variable quad: std_logic_vector(31 downto 0);

		variable i: natural range 0 to 3;

		variable first: boolean;
		variable stop_lcl: boolean;

		variable burstState: std_logic_vector(7 downto 0);
		variable burstCnt: natural range 0 to 65535;

	begin
		if reset='1' then
			stateSeq <= stateSeqInit;
			TCapt <= (others => '0');
			ptr0SeqbufTrackNotFixed <= '0';
			enSeqbuf <= '0';
			aSeqbuf <= 0;
			dwrSeqbuf <= (others => '0');

			quad := (others => '0');
			i := 0;
			first := true;
			stop_lcl := false;
			burstState := (others => '1');
			burstCnt := 0;

		elsif rising_edge(mclk) then
			if stateSeq=stateSeqInit then
				TCapt <= (others => '0');
				ptr0SeqbufTrackNotFixed <= '0';
				enSeqbuf <= '0';
				aSeqbuf <= 0;
				dwrSeqbuf <= (others => '0');

				quad := (others => '0');
				i := 0;
				first := true;
				stop_lcl := false;
				burstState := (others => '1');
				burstCnt := 0;

				stateSeq <= stateSeqIdle;

			elsif stateSeq=stateSeqIdle then -- rdySeq='1'
				if strbStart='1' then
					stateSeq <= stateSeqRun;
				end if;

			elsif stateSeq=stateSeqRun then
				TCapt <= std_logic_vector(unsigned(TCapt) + 1);

				if strbStop='1' or (stoTixVTrigger=tixVTriggerVoid and (i=0 and aSeqbuf=sizeSeqbuf/4-1)) then
					stop_lcl := true;
				end if;

				quad((i+1)*8-1 downto i*8) := state;

				if i=3 then
					if quad(23 downto 16)=state and quad(15 downto 8)=state and quad(7 downto 0)=state then
						if state/=burstState or burstCnt=65535 then
							if not first then
								if aSeqbuf=sizeSeqbuf/4-1 then
									ptr0SeqbufTrackNotFixed <= '1';
									aSeqbuf <= 0;
								else
									aSeqbuf <= aSeqbuf + 1;
								end if;
							end if;

							burstCnt := 0;
						end if;

						burstState := state;
						burstCnt := burstCnt + 1;

						dwrSeqbuf <= x"FF" & burstState & std_logic_vector(to_unsigned(burstCnt, 16));

					else
						burstState := (others => '1');
						burstCnt := 0;

						if not first then
							if aSeqbuf=sizeSeqbuf/4-1 then
								ptr0SeqbufTrackNotFixed <= '1';
								aSeqbuf <= 0;
							else
								aSeqbuf <= aSeqbuf + 1;
							end if;
						end if;

						dwrSeqbuf <= quad;
					end if;

					enSeqbuf <= '1';

					i := 0;
					first := false;

					stateSeq <= stateSeqRun;

				else
					enSeqbuf <= '0';

					if stop_lcl then
						stateSeq <= stateSeqDone;

					else
						i := i + 1;

						stateSeq <= stateSeqRun;
					end if;
				end if;

			elsif stateSeq=stateSeqDone then
				if reqOpClear='1' or reqSeqbufBToSeqClear='1' then
					aSeqbuf <= 0;
					dwrSeqbuf <= (others => '1');

					stateSeq <= stateSeqClear;
				end if;

			elsif stateSeq=stateSeqClear then
				if aSeqbuf=sizeSeqbuf/4-1 then
					if reqSeqbufBToSeqClear='1' then
						stateSeq <= stateSeqAckClear;
					else
						stateSeq <= stateSeqInit;
					end if;

				else
					aSeqbuf <= aSeqbuf + 1;
				end if;

			elsif stateSeq=stateSeqAckClear then -- ackSeqbufBToSeqClear='1'
				if reqSeqbufBToSeqClear='0' then
					stateSeq <= stateSeqInit;
				end if;
			end if;
		end if;
	end process;

	------------------------------------------------------------------------
	-- implementation: sequence buffer B/hostif-facing operation (seqbufB)
	------------------------------------------------------------------------

	ackSeqbufToHostif <= '1' when stateSeqbufB=stateSeqbufBXferA or stateSeqbufB=stateSeqbufBXferB or stateSeqbufB=stateSeqbufBDone else '0';

	avllenSeqbufToHostif <= std_logic_vector(to_unsigned(sizeSeqbuf, 32)) when dneSeq='1'
				else (others => '0');

	seqbufToHostifAXIS_tvalid <= '1' when stateSeqbufB=stateSeqbufBXferB else '0';

	seqbufToHostifAXIS_tlast <= '1' when stateSeqbufB=stateSeqbufBXferB and aSeqbufB=(sizeSeqbuf/(wD/8))-1 else '0';

	enSeqbufB <= '1' when stateSeqbufB=stateSeqbufBXferA else '0';

	aSeqbufB_vec <= std_logic_vector(to_unsigned(aSeqbufB, logSizeSeqbuf-logWD));

	reqSeqbufBToSeqClear <= '1' when stateSeqbufB=stateSeqbufBClear else '0';

	process (reset, mclk, stateSeqbufB)

	begin
		if reset='1' then
			stateSeqbufB <= stateSeqbufBInit;
			aSeqbufB <= 0;

		elsif rising_edge(mclk) then
			if stateSeqbufB=stateSeqbufBInit then
				aSeqbufB <= 0;

				stateSeqbufB <= stateSeqbufBIdle;

			elsif stateSeqbufB=stateSeqbufBIdle then
				if reqSeqbufToHostif='1' then
					stateSeqbufB <= stateSeqbufBXferA;
				end if;

			elsif stateSeqbufB=stateSeqbufBXferA then -- enSeqbufB='1'
				stateSeqbufB <= stateSeqbufBXferB;
				
			elsif stateSeqbufB=stateSeqbufBXferB then -- seqbufToHostifAXIS_tvalid='1'
				if seqbufToHostifAXIS_tready='1' then
					if aSeqbufB=(sizeSeqbuf/(wD/8))-1 then
						stateSeqbufB <= stateSeqbufBDone;

					else
						aSeqbufB <= aSeqbufB + 1;

						stateSeqbufB <= stateSeqbufBXferA;
					end if;

				elsif reqSeqbufToHostif='0' then
					stateSeqbufB <= stateSeqbufBInit;
				end if;

			elsif stateSeqbufB=stateSeqbufBDone then
				if dneSeqbufToHostif='1' then
					stateSeqbufB <= stateSeqbufBClear;

				elsif reqSeqbufToHostif='0' then
					stateSeqbufB <= stateSeqbufBInit;
				end if ;

			elsif stateSeqbufB=stateSeqbufBClear then -- reqSeqbufBToSeqClear='1'
				if reqSeqbufToHostif='0' and ackSeqbufBToSeqClear='1' then
					stateSeqbufB <= stateSeqbufBInit;
				end if;
			end if;
		end if;
	end process;

end Rtl;
