// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.1.110.3.16
// IP Version: 5.2
// =============================================================================

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//                                                                       
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//                                                                       
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.                                                
//
////////////////////////////////////////////////////////////////////////////////

`define IP_UUID _ae17959c5d3b4e31be0c8176462f1383
`define IP_NAME_CONCAT(a,b) a``b
`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
module apb3_2_axi4_lite
(
    input [9:0] s_apb3_paddr,
    input s_apb3_psel,
    input s_apb3_penable,
    input s_apb3_pwrite,
    input [31:0] s_apb3_pwdata,
    output s_apb3_pready,
    output [31:0] s_apb3_prdata,
    output s_apb3_pslverror,
    input clk,
    input rstn,
    input m_axi_awready,
    input m_axi_wready,
    input m_axi_arready,
    input [31:0] m_axi_rdata,
    input m_axi_rvalid,
    output [9:0] m_axi_awaddr,
    output m_axi_awvalid,
    output [31:0] m_axi_wdata,
    output m_axi_wvalid,
    output [9:0] m_axi_araddr,
    output m_axi_arvalid,
    output m_axi_rready
);
`IP_MODULE_NAME(apb3_2_axi4_lite)
#(
    .ADDR_WTH (10)
)
u_apb3_2_axi4_lite
(
    .s_apb3_paddr ( s_apb3_paddr ),
    .s_apb3_psel ( s_apb3_psel ),
    .s_apb3_penable ( s_apb3_penable ),
    .s_apb3_pwrite ( s_apb3_pwrite ),
    .s_apb3_pwdata ( s_apb3_pwdata ),
    .s_apb3_pready ( s_apb3_pready ),
    .s_apb3_prdata ( s_apb3_prdata ),
    .s_apb3_pslverror ( s_apb3_pslverror ),
    .clk ( clk ),
    .rstn ( rstn ),
    .m_axi_awready ( m_axi_awready ),
    .m_axi_wready ( m_axi_wready ),
    .m_axi_arready ( m_axi_arready ),
    .m_axi_rdata ( m_axi_rdata ),
    .m_axi_rvalid ( m_axi_rvalid ),
    .m_axi_awaddr ( m_axi_awaddr ),
    .m_axi_awvalid ( m_axi_awvalid ),
    .m_axi_wdata ( m_axi_wdata ),
    .m_axi_wvalid ( m_axi_wvalid ),
    .m_axi_araddr ( m_axi_araddr ),
    .m_axi_arvalid ( m_axi_arvalid ),
    .m_axi_rready ( m_axi_rready )
);
endmodule

/////////////////////////////////////////////////////////////////////////////
//           _____       
//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
//         / /       \   
//        / /  ..    /   
//       / / .'     /    
//    __/ /.'      /     
//   __   \       /      
//  /_/ /\ \_____/ /     
// ____/  \_______/      
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module `IP_MODULE_NAME(apb3_2_axi4_lite)
(
	s_apb3_paddr,
    s_apb3_psel,
    s_apb3_penable,
    s_apb3_pwrite,
    s_apb3_pwdata,
    s_apb3_pready,
    s_apb3_prdata,
    s_apb3_pslverror,
    clk,
    rstn,
    m_axi_awready,
    m_axi_wready,
    m_axi_arready,
    m_axi_rdata,
    m_axi_rvalid,
    m_axi_awaddr,
    m_axi_awvalid,
    m_axi_wdata,
    m_axi_wvalid,
    m_axi_araddr,
    m_axi_arvalid,
    m_axi_rready
);

parameter ADDR_WTH = 10;
//Globle Signals
input                           clk;
input                           rstn;
//APB3 Slave Interface
input           [ADDR_WTH-1:0]  s_apb3_paddr;
input                           s_apb3_psel;
input                           s_apb3_penable;
output  reg                     s_apb3_pready;
input                           s_apb3_pwrite;//0:rd; 1:wr;
input           [31:0]          s_apb3_pwdata;
output  reg     [31:0]          s_apb3_prdata;
output  reg                     s_apb3_pslverror;
//AXI4-Lite Master Interface
output  reg     [ADDR_WTH-1:0]  m_axi_awaddr;//Write Address. byte address.
output  reg                     m_axi_awvalid;//Write address valid.
input                           m_axi_awready;//Write address ready.
output  reg     [31:0]          m_axi_wdata;//Write data bus.
output  reg                     m_axi_wvalid;//Write valid.
input                           m_axi_wready;//Write ready.
output  reg     [ADDR_WTH-1:0]  m_axi_araddr;//Read address. byte address.
output  reg                     m_axi_arvalid;//Read address valid.
input                           m_axi_arready;//Read address ready.
input           [31:0]          m_axi_rdata;//Read data.
input                           m_axi_rvalid;//Read valid.
output  wire                    m_axi_rready;//Read ready.
// Parameter Define 
parameter State_idle    = 3'd0;
parameter State_wsetup  = 3'd1;
parameter State_rsetup  = 3'd2;
parameter State_ready   = 3'd3;
parameter State_err     = 3'd4;

// Register Define
reg     [2:0]                   cur_state;
reg     [2:0]                   next_state;
reg     [7:0]                   timeout_cnt;

// Wire Define

/*----------------------------------------------------------------------------------*\
                                 The main code
\*----------------------------------------------------------------------------------*/

/*----------------------- FSM Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
    if(rstn == 1'b0)
        cur_state <= State_idle;
    else
		cur_state <= next_state;
end

always @(*)
begin
	case(cur_state)
    State_idle :
        if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
            next_state = State_wsetup;
        else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0))
            next_state = State_rsetup;
        else
            next_state = State_idle;

    State_wsetup : 
        if((m_axi_awvalid == 1'b0) && (m_axi_wvalid == 1'b0))
            next_state = State_ready;
        else if(timeout_cnt[7] == 1'b1)
            next_state = State_err;
        else
            next_state = State_wsetup;

    State_rsetup :
        if(m_axi_rvalid == 1'b1)
            next_state = State_ready;
        else if(timeout_cnt[7] == 1'b1)
            next_state = State_err;
        else
            next_state = State_rsetup;

    State_ready :
        next_state = State_idle;

    State_err :
        next_state = State_idle;

    default :
        next_state = State_idle;
    endcase
end

always @(posedge clk or negedge rstn)
begin
    if(rstn == 1'b0)
        timeout_cnt <= 8'h0;
    else if((cur_state == State_wsetup) || (cur_state == State_rsetup))
        timeout_cnt <= timeout_cnt + 1'b1;
    else
        timeout_cnt <= 8'h0;
end

/*----------------------- APB3 Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
    if(rstn == 1'b0)
        s_apb3_pready <= 1'b0;
    else if((cur_state == State_ready) || (cur_state == State_err))
        s_apb3_pready <= 1'b1;
    else
        s_apb3_pready <= 1'b0;
end

always @(posedge clk or negedge rstn)
begin
    if(rstn == 1'b0)
        s_apb3_pslverror <= 1'b0;
    else if(cur_state == State_err)
        s_apb3_pslverror <= 1'b1;
    else
        s_apb3_pslverror <= 1'b0;
end

always @(posedge clk or negedge rstn)
begin
    if(rstn == 1'b0)
        s_apb3_prdata <= 32'h0;
    else if(m_axi_rvalid == 1'b1)
        s_apb3_prdata <= m_axi_rdata;
end

/*----------------------- AXI4-Lite Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
    if(rstn == 1'b0)
        m_axi_awaddr <= {ADDR_WTH{1'b0}};
    else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
        m_axi_awaddr <= s_apb3_paddr;
end

always @(posedge clk or negedge rstn)
begin
    if(rstn == 1'b0)
        m_axi_awvalid <= 1'b0;
    else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
        m_axi_awvalid <= 1'b1;
    else if((m_axi_awready == 1'b1) || (cur_state == State_idle))
        m_axi_awvalid <= 1'b0;
end

always @(posedge clk or negedge rstn)
begin
    if(rstn == 1'b0)
        m_axi_wdata <= 32'h0;
    else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
        m_axi_wdata <= s_apb3_pwdata;
end

always @(posedge clk or negedge rstn)
begin
    if(rstn == 1'b0)
        m_axi_wvalid <= 1'b0;
    else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
        m_axi_wvalid <= 1'b1;
    else if((m_axi_wready == 1'b1) || (cur_state == State_idle))
        m_axi_wvalid <= 1'b0;
end


always @(posedge clk or negedge rstn)
begin
    if(rstn == 1'b0)
        m_axi_araddr <= {ADDR_WTH{1'b0}};
    else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0))
        m_axi_araddr <= s_apb3_paddr;
end

always @(posedge clk or negedge rstn)
begin
    if(rstn == 1'b0)
        m_axi_arvalid <= 1'b0;
    else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0))
        m_axi_arvalid <= 1'b1;
    else if((m_axi_arready == 1'b1) || (cur_state == State_idle))
        m_axi_arvalid <= 1'b0;
end

assign m_axi_rready = 1'b1;

endmodule

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2020 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
// protected by  copyright. All rights  are reserved.  This notice       
// refers to original work by Efinix, Inc. which may be derivitive       
// of other work distributed under license of the authors.  In the       
// case of derivative work, nothing in this notice overrides the         
// original author's license agreement.  Where applicable, the           
// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
//
// WARRANTY DISCLAIMER.                                                  
//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
//
// LIMITATION OF LIABILITY.                                              
//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
//     APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////

`undef IP_UUID
`undef IP_NAME_CONCAT
`undef IP_MODULE_NAME
