/////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// Description:
// Example top file for SapphireSoC
//
// Language: Verilog 2001
//
// ------------------------------------------------------------------------------
// REVISION:
// $Snapshot: $
// $Id:$
//
// History:
// 1.0 Initial Release. 
// 1.1 Enhance APB3 slave range from 4K to 64K
//	 Enhance AXI4 slave range from 4K to 16MB
// ------------------------------------------------------------------------------
//
// adaptations 2025 by MPSI Technologies GmbH, marked (aw)
//
/////////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module top_ti180 (
	// PLL
	output my_pll_rstn,
	input my_pll_locked,
	output my_ddr_pll_rstn,
	input my_ddr_pll_locked,
	output tse_pll_rstn,
	input tse_pll_locked,
	input mux_clk,
	output[1:0] mux_clk_sw,

	// TSE
	output wire[3:0] rgmii_txd_HI,
	output wire[3:0] rgmii_txd_LO,
	output wire rgmii_tx_ctl_HI,
	output wire rgmii_tx_ctl_LO,
	output wire rgmii_txc_HI,
	output wire rgmii_txc_LO,
	input[3:0] rgmii_rxd_HI,
	input[3:0] rgmii_rxd_LO,
	input rgmii_rx_ctl_HI,
	input rgmii_rx_ctl_LO,

	// DDR memory channel for the SapphireSoC
	output io_ddrA_ar_valid,
	input io_ddrA_ar_ready,
	output[32:0] io_ddrA_ar_payload_addr,
	output[5:0]	io_ddrA_ar_payload_id,
	output[7:0]	io_ddrA_ar_payload_len,
	output[2:0]	io_ddrA_ar_payload_size,
	output[1:0]	io_ddrA_ar_payload_burst,
	output io_ddrA_ar_payload_lock,
	output io_ddrA_ar_apcmd,
	output io_ddrA_ar_payload_qos,
	output io_ddrA_aw_valid,
	input io_ddrA_aw_ready,
	output[32:0] io_ddrA_aw_payload_addr,
	output[5:0]	io_ddrA_aw_payload_id,
	output[7:0]	io_ddrA_aw_payload_len,
	output[2:0]	io_ddrA_aw_payload_size,
	output[1:0]	io_ddrA_aw_payload_burst,
	output io_ddrA_aw_payload_lock,
	output[3:0]	io_ddrA_aw_payload_cache,
	output io_ddrA_aw_payload_qos,
	output io_ddrA_aw_payload_allstrb,
	output io_ddrA_aw_apcmd,
	output io_ddrA_awcobuf,
	output io_ddrA_w_valid,
	input io_ddrA_w_ready,
	output[511:0] io_ddrA_w_payload_data,
	output[63:0] io_ddrA_w_payload_strb,
	output io_ddrA_w_payload_last,
	input io_ddrA_b_valid,
	output io_ddrA_b_ready,
	input[1:0] io_ddrA_b_payload_resp,
	input[5:0] io_ddrA_b_payload_id,
	input io_ddrA_r_valid,
	output io_ddrA_r_ready,
	input [511:0] io_ddrA_r_payload_data,
	input[5:0] io_ddrA_r_payload_id,
	input[1:0] io_ddrA_r_payload_resp,
	input io_ddrA_r_payload_last,

	output io_memoryResetn,

	output cfg_start,
	output cfg_reset,
	output cfg_sel,
	input cfg_done,

	// TEMAC PHY ctr Interface
	output wire phy_rst,

	// TEMAC PHY MDIO Interface
	input phy_mdi,
	output wire phy_mdo,
	output wire phy_mdo_en,
	output wire phy_mdc,

	// SoC
	input io_systemClk,
	// (aw)
	//input io_peripheralClk,
	input io_asyncReset, // active low
	input io_memoryClk,
	input io_tseClk, 
	output system_uart_0_io_txd,
	input system_uart_0_io_rxd,

	// (aw)
	//input[3:0] system_gpio_0_io_read,
	//output[3:0] system_gpio_0_io_write,
	//output[3:0] system_gpio_0_io_writeEnable,

	//output system_i2c_0_io_sda_writeEnable,
	//output system_i2c_0_io_sda_write,
	//input system_i2c_0_io_sda_read,
	//output system_i2c_0_io_scl_writeEnable,
	//output system_i2c_0_io_scl_write,
	//input system_i2c_0_io_scl_read,

	output system_spi_0_io_sclk_write,
	output system_spi_0_io_data_0_writeEnable,
	input system_spi_0_io_data_0_read,
	output system_spi_0_io_data_0_write,
	output system_spi_0_io_data_1_writeEnable,
	input system_spi_0_io_data_1_read,
	output system_spi_0_io_data_1_write,
	output system_spi_0_io_ss,

	input[3:0] sd_dat_IN,
	input sd_cmd_IN,
	output[3:0] sd_dat_OUT,
	output[3:0] sd_dat_OE,
	output sd_clk,
	output sd_cmd_OUT,
	output sd_cmd_OE,

	input jtag_inst1_TCK,
	input jtag_inst1_TDI,
	output jtag_inst1_TDO,
	input jtag_inst1_SEL,
	input jtag_inst1_CAPTURE,
	input jtag_inst1_SHIFT,
	input jtag_inst1_UPDATE,
	input jtag_inst1_RESET,

	// (aw) modifications from here
	//output [5:0]			led

	input io_vspmemClk,

	// DDR memory channel for vsp_core
	output io_vspmemResetn,

	output[5:0] ddrAXI_arid,
	output[32:0] ddrAXI_araddr,
	output[1:0] ddrAXI_arburst,
	output[3:0] ddrAXI_arcache,
	output[7:0] ddrAXI_arlen,
	output[0:0] ddrAXI_arlock,
	output[2:0] ddrAXI_arprot,
	output[3:0] ddrAXI_arqos,
	input ddrAXI_arready,
	output[3:0] ddrAXI_arregion,
	output[2:0] ddrAXI_arsize,
	output ddrAXI_arvalid,

	input[5:0] ddrAXI_rid,
	input[511:0] ddrAXI_rdata,
	input ddrAXI_rlast,
	input[1:0] ddrAXI_rresp,
	output ddrAXI_rready,
	input ddrAXI_rvalid,

	output[5:0] ddrAXI_awid,
	output[32:0] ddrAXI_awaddr,
	output[1:0] ddrAXI_awburst,
	output[3:0] ddrAXI_awcache,
	output[7:0] ddrAXI_awlen,
	output[0:0] ddrAXI_awlock,
	output[2:0] ddrAXI_awprot,
	output[3:0] ddrAXI_awqos,
	input ddrAXI_awready,
	output[3:0] ddrAXI_awregion,
	output[2:0] ddrAXI_awsize,
	output ddrAXI_awvalid,

	output[511:0] ddrAXI_wdata,
	output ddrAXI_wlast,
	input ddrAXI_wready,
	output[63:0] ddrAXI_wstrb,
	output ddrAXI_wvalid,

	input[5:0] ddrAXI_bid,
	output ddrAXI_bready,
	input[1:0] ddrAXI_bresp,
	input ddrAXI_bvalid,

	// MIPI CSI-2 RX for vsp_core
	input clk_byte_HS,
	output mipirx_RESET_N,
	output mipirx_RST0_N,
	input mipirx_ERR_CONTROL_LAN0,
	input mipirx_ERR_CONTROL_LAN1,
	input mipirx_ERR_CONTROL_LAN2,
	input mipirx_ERR_CONTROL_LAN3,
	input mipirx_ERR_ESC_LAN0,
	input mipirx_ERR_ESC_LAN1,
	input mipirx_ERR_ESC_LAN2,
	input mipirx_ERR_ESC_LAN3,
	input mipirx_ERR_SOT_SYNC_HS_LAN0,
	input mipirx_ERR_SOT_SYNC_HS_LAN1,
	input mipirx_ERR_SOT_SYNC_HS_LAN2,
	input mipirx_ERR_SOT_SYNC_HS_LAN3,
	input mipirx_ESC_CLK_LAN0,
	input mipirx_ESC_CLK_LAN1,
	input mipirx_ESC_CLK_LAN2,
	input mipirx_ESC_CLK_LAN3,
	input[15:0] mipirx_RX_DATA_HS_LAN0,
	input[15:0] mipirx_RX_DATA_HS_LAN1,
	input[15:0] mipirx_RX_DATA_HS_LAN2,
	input[15:0] mipirx_RX_DATA_HS_LAN3,
	input mipirx_RX_SKEW_CAL_HS_LAN0,
	input mipirx_RX_SKEW_CAL_HS_LAN1,
	input mipirx_RX_SKEW_CAL_HS_LAN2,
	input mipirx_RX_SKEW_CAL_HS_LAN3,
	input mipirx_RX_SYNC_HS_LAN0,
	input mipirx_RX_SYNC_HS_LAN1,
	input mipirx_RX_SYNC_HS_LAN2,
	input mipirx_RX_SYNC_HS_LAN3,
	input mipirx_RX_ULPS_ACTIVE_CLK_NOT,
	input mipirx_RX_ULPS_ACTIVE_NOT_LAN0,
	input mipirx_RX_ULPS_ACTIVE_NOT_LAN1,
	input mipirx_RX_ULPS_ACTIVE_NOT_LAN2,
	input mipirx_RX_ULPS_ACTIVE_NOT_LAN3,
	input mipirx_RX_ULPS_CLK_NOT,
	input mipirx_RX_ULPS_ESC_LAN0,
	input mipirx_RX_ULPS_ESC_LAN1,
	input mipirx_RX_ULPS_ESC_LAN2,
	input mipirx_RX_ULPS_ESC_LAN3,
	input mipirx_RX_VALID_HS_LAN0,
	input mipirx_RX_VALID_HS_LAN1,
	input mipirx_RX_VALID_HS_LAN2,
	input mipirx_RX_VALID_HS_LAN3,
	input mipirx_STOPSTATE_LAN0,
	input mipirx_STOPSTATE_LAN1,
	input mipirx_STOPSTATE_LAN2,
	input mipirx_STOPSTATE_LAN3,

	// GPIO's for vsp_core
	input scl_in,
	output scl_out,
	output scl_tri,

	input sda_in,
	output sda_out,
	output sda_tri,

	output cs,
	output sclk,
	output mosi,

	output rgb0_r,
	output rgb0_g,
	output rgb0_b,
	output rgb1_r,
	output rgb1_g,
	output rgb1_b,

	output nslp,
	output m0,
	output m0z,
	output m1,
	output m1z,
	output dir,
	output step,

	output[5:0] probe
);

localparam MEM_DW = 512;
localparam AXIS_DW = 64;
localparam [1:0]	IDLE		= 2'b00,
					CFG_START   = 2'b01,
					CFG_DONE	= 2'b11;
wire cfg_ok;
wire phy_active;

// (aw)
//assign led[0] = cfg_ok;
//assign led[1] = phy_active;
/////////////////////////////////////////////////////////////////////////////
//ddr4 config

reg [1:0]   cfg_st, cfg_next;
reg [7:0]   cfg_count;
// (aw)
always@(posedge io_systemClk or negedge io_asyncReset) begin
	if(!io_asyncReset)
		cfg_st <= IDLE;
	else
		cfg_st <= cfg_next;
end

always@(*) begin
	cfg_next = cfg_st;
	case(cfg_st)
	IDLE: begin
		if(cfg_count == 'hff)
			cfg_next = CFG_START;
		else
			cfg_next = IDLE;
	end
	CFG_START: begin
		if(cfg_done)
			cfg_next = CFG_DONE;
		else
			cfg_next = CFG_START;
	end
	CFG_DONE:
		cfg_next = CFG_DONE;
	default:
		cfg_next = IDLE;
	endcase
end

assign cfg_start	= (cfg_st != IDLE);
assign cfg_ok	   = (cfg_st == CFG_DONE);
assign cfg_reset	= (cfg_st == IDLE);
assign cfg_sel	  = 1'b0;

// (aw)
always@(posedge io_systemClk) begin
	if(cfg_st == IDLE)
		cfg_count <= cfg_count + 1'b1;
	else
		cfg_count <= 'h0;
end

wire rgmii_rxc;
assign rgmii_rxc = mux_clk;

//assign system_i2c_0_io_sda_writeEnable = !system_i2c_0_io_sda_write;
//assign system_i2c_0_io_scl_writeEnable = !system_i2c_0_io_scl_write;

/////////////////////////////////////////////////////////////////////////////
wire [31:0] io_ddrA_ar_payload_addr_i;
wire [31:0] io_ddrA_aw_payload_addr_i;
wire [7:0]  io_ddrA_ar_payload_id_i;
wire [7:0]  io_ddrA_aw_payload_id_i;
wire [7:0]  io_ddrA_b_payload_id_i;
wire [7:0]  io_ddrA_r_payload_id_i;


// reset and PLL
wire		mcuReset;
wire		pll_locked;
wire		io_systemReset;
wire		io_ddrMasterReset;
wire		phy_sw_rst;
(* keep , syn_keep *) wire		io_memoryReset /* synthesis syn_keep = 1 */;			  

// APB Slave 0  
wire   [15:0]   eth_apb3_paddr;
wire			eth_apb3_psel;
wire			eth_apb3_penable;
wire			eth_apb3_pready;
wire			eth_apb3_pwrite;
wire   [31:0]   eth_apb3_pwdata;
wire   [31:0]   eth_apb3_prdata;
wire			eth_apb3_pslverror;

// APB Slave 1 
wire   [15:0]   dma_apb3_paddr;
wire			dma_apb3_psel;
wire			dma_apb3_penable;
wire			dma_apb3_pready;
wire			dma_apb3_pwrite;
wire   [31:0]   dma_apb3_pwdata;
wire   [31:0]   dma_apb3_prdata;
wire			dma_apb3_pslverror;

// APB Slave 2
wire   [15:0]   io_apbSlave_2_PADDR;
wire			io_apbSlave_2_PSEL;
wire			io_apbSlave_2_PENABLE;
wire			io_apbSlave_2_PREADY;
wire			io_apbSlave_2_PWRITE;
wire   [31:0]   io_apbSlave_2_PWDATA;
wire   [31:0]   io_apbSlave_2_PRDATA;
wire			io_apbSlave_2_PSLVERROR;

// DMA
wire					dmaaxi_read_arvalid;
wire					dmaaxi_read_arready;
wire	[31:0]		  dmaaxi_read_araddr;
wire	[3:0]		   dmaaxi_read_arregion;
wire	[7:0]		   dmaaxi_read_arlen;
wire	[2:0]		   dmaaxi_read_arsize;
wire	[1:0]		   dmaaxi_read_arburst;
wire	[0:0]		   dmaaxi_read_arlock;
wire	[3:0]		   dmaaxi_read_arcache;
wire	[3:0]		   dmaaxi_read_arqos;
wire	[2:0]		   dmaaxi_read_arprot;
wire					dmaaxi_read_rvalid;
wire					dmaaxi_read_rready;
wire	[AXIS_DW-1:0]   dmaaxi_read_rdata;
wire	[1:0]		   dmaaxi_read_rresp;
wire					dmaaxi_read_rlast;
wire					dmaaxi_write_awvalid;
wire					dmaaxi_write_awready;
wire	[31:0]		  dmaaxi_write_awaddr;
wire	[3:0]		   dmaaxi_write_awregion;
wire	[7:0]		   dmaaxi_write_awlen;
wire	[2:0]		   dmaaxi_write_awsize;
wire	[1:0]		   dmaaxi_write_awburst;
wire	[0:0]		   dmaaxi_write_awlock;
wire	[3:0]		   dmaaxi_write_awcache;
wire	[3:0]		   dmaaxi_write_awqos;
wire	[2:0]		   dmaaxi_write_awprot;
wire					dmaaxi_write_wvalid;
wire					dmaaxi_write_wready;
wire	[AXIS_DW-1:0]   dmaaxi_write_wdata;
wire	[AXIS_DW/8-1:0] dmaaxi_write_wstrb;
wire					dmaaxi_write_wlast;
wire					dmaaxi_write_bvalid;
wire					dmaaxi_write_bready;
wire	[1:0]		   dmaaxi_write_bresp;

wire	[1:0]   dma_interrupts;
// wire			dmaInterrupts;
wire			rx_dma_descriptorUpdate;

wire  [2:0] eth_speed;
assign mux_clk_sw = eth_speed[2] ? 2 : 3;	//select clock 2 when speed == 1000Mbps

/////////////////////////////////////////////////////////////////////////////
core u_core (
	.io_systemReset (io_systemReset),
	.io_ddrMasterReset  (io_ddrMasterReset),
	// (aw)
	.io_peripheralClk   (io_systemClk),
	.io_memoryClk   (io_memoryClk),
	.io_tseClk  (io_tseClk),

	.rgmii_txd_HI	   (rgmii_txd_HI),
	.rgmii_txd_LO	   (rgmii_txd_LO),
	.rgmii_tx_ctl_HI	(rgmii_tx_ctl_HI),
	.rgmii_tx_ctl_LO	(rgmii_tx_ctl_LO),
	.rgmii_txc_HI	   (rgmii_txc_HI),
	.rgmii_txc_LO	   (rgmii_txc_LO),
	.rgmii_rxd_HI	   (rgmii_rxd_HI),
	.rgmii_rxd_LO	   (rgmii_rxd_LO),
	.rgmii_rx_ctl_HI	(rgmii_rx_ctl_HI),
	.rgmii_rx_ctl_LO	(rgmii_rx_ctl_LO),
	.rgmii_rxc		  (rgmii_rxc),

	.phy_mdi	(phy_mdi),
	.phy_mdo	(phy_mdo),
	.phy_mdo_en (phy_mdo_en),
	.phy_mdc	(phy_mdc),

	.dmaaxi_read_arready	(dmaaxi_read_arready),
	.dmaaxi_read_rvalid (dmaaxi_read_rvalid),
	.dmaaxi_read_rdata  (dmaaxi_read_rdata),
	.dmaaxi_read_rresp  (dmaaxi_read_rresp),
	.dmaaxi_read_rlast  (dmaaxi_read_rlast),
	.dmaaxi_write_awready   (dmaaxi_write_awready),
	.dmaaxi_write_wready	(dmaaxi_write_wready),
	.dmaaxi_write_bvalid	(dmaaxi_write_bvalid),
	.dmaaxi_write_bresp (dmaaxi_write_bresp),
	.dmaaxi_read_arvalid	(dmaaxi_read_arvalid),
	.dmaaxi_read_araddr (dmaaxi_read_araddr),
	.dmaaxi_read_arregion   (dmaaxi_read_arregion),
	.dmaaxi_read_arlen  (dmaaxi_read_arlen),
	.dmaaxi_read_arsize (dmaaxi_read_arsize),
	.dmaaxi_read_arburst	(dmaaxi_read_arburst),
	.dmaaxi_read_arlock (dmaaxi_read_arlock),
	.dmaaxi_read_arcache	(dmaaxi_read_arcache),
	.dmaaxi_read_arqos  (dmaaxi_read_arqos),
	.dmaaxi_read_arprot (dmaaxi_read_arprot),
	.dmaaxi_read_rready (dmaaxi_read_rready),
	.dmaaxi_write_awvalid   (dmaaxi_write_awvalid),
	.dmaaxi_write_awaddr	(dmaaxi_write_awaddr),
	.dmaaxi_write_awregion  (dmaaxi_write_awregion),
	.dmaaxi_write_awlen (dmaaxi_write_awlen),
	.dmaaxi_write_awsize	(dmaaxi_write_awsize),
	.dmaaxi_write_awburst   (dmaaxi_write_awburst),
	.dmaaxi_write_awlock	(dmaaxi_write_awlock),
	.dmaaxi_write_awcache   (dmaaxi_write_awcache),
	.dmaaxi_write_awqos (dmaaxi_write_awqos),
	.dmaaxi_write_awprot	(dmaaxi_write_awprot),
	.dmaaxi_write_wvalid	(dmaaxi_write_wvalid),
	.dmaaxi_write_wdata (dmaaxi_write_wdata),
	.dmaaxi_write_wstrb (dmaaxi_write_wstrb),
	.dmaaxi_write_wlast (dmaaxi_write_wlast),
	.dmaaxi_write_bready	(dmaaxi_write_bready),

	.eth_apb3_paddr (eth_apb3_paddr),
	.eth_apb3_psel  (eth_apb3_psel),
	.eth_apb3_penable   (eth_apb3_penable),
	.eth_apb3_pwrite	(eth_apb3_pwrite),
	.eth_apb3_pwdata	(eth_apb3_pwdata),
	.eth_apb3_pready	(eth_apb3_pready),
	.eth_apb3_prdata	(eth_apb3_prdata),
	.eth_apb3_pslverror (eth_apb3_pslverror),

	.dma_apb3_paddr (dma_apb3_paddr),
	.dma_apb3_psel  (dma_apb3_psel),
	.dma_apb3_penable   (dma_apb3_penable),
	.dma_apb3_pready	(dma_apb3_pready),
	.dma_apb3_pwrite	(dma_apb3_pwrite),
	.dma_apb3_pwdata	(dma_apb3_pwdata),
	.dma_apb3_prdata	(dma_apb3_prdata),
	.dma_apb3_pslverror (dma_apb3_pslverror),

	.pll_locked (pll_locked),
	.phy_sw_rst (phy_sw_rst),
	.dma_interrupts (dma_interrupts),
	.eth_speed  (eth_speed)

);

/////////////////////////////////////////////////////////////////////////////
// reset and PLL
assign pll_locked   = io_asyncReset & my_pll_locked & my_ddr_pll_locked & cfg_ok;
assign mcuReset	 = ~pll_locked;
assign my_pll_rstn  = 1'b1;
assign my_ddr_pll_rstn  = 1'b1;
assign tse_pll_rstn = 1'b1;
assign phy_rst	 = phy_sw_rst;

// DDR memory
assign io_memoryResetn = cfg_ok;
assign io_ddrA_w_payload_id='h0;
assign io_ddrA_ar_apcmd = 1'b0;
assign io_ddrA_aw_payload_allstrb = 1'b0;
assign io_ddrA_aw_apcmd = 1'b0;
assign io_ddrA_awcobuf = 1'b0;
assign io_ddrA_ar_payload_addr= {1'b0, io_ddrA_ar_payload_addr_i};
assign io_ddrA_aw_payload_addr= {1'b0, io_ddrA_aw_payload_addr_i};
assign io_ddrA_ar_payload_id  = {io_ddrA_ar_payload_id_i[7:6], io_ddrA_ar_payload_id_i[3:0]};
assign io_ddrA_aw_payload_id  = {io_ddrA_aw_payload_id_i[7:6], io_ddrA_aw_payload_id_i[3:0]};
assign io_ddrA_b_payload_id_i = {io_ddrA_b_payload_id[5:4], 2'b00, io_ddrA_b_payload_id[3:0]};
assign io_ddrA_r_payload_id_i = {io_ddrA_r_payload_id[5:4], 2'b00, io_ddrA_r_payload_id[3:0]};
/////////////////////////////////////////////////////////////////////////////

led_ctl freq_test (
	 .led_o(phy_active),
	 .clk(io_tseClk),
	 .rst_n(tse_pll_locked)
);



/////////////////////////////////////////////////////////////////////////////
assign sd_dat_OE[3] = 1;
assign sd_dat_OE[2] = 0; 
assign sd_dat_OE[1] = 0; 

SapphireCore SapphireGEN_inst (
	.io_systemClk		   (io_systemClk),
	.io_asyncReset		  (mcuReset),
	.io_memoryClk		   (io_memoryClk),
	.io_memoryReset		 (io_memoryReset),
	.io_systemReset		 (io_systemReset),
	// (aw)
	//.io_peripheralClk	   (io_peripheralClk),
	//.io_peripheralReset	 (areset),


	.system_uart_0_io_txd   (system_uart_0_io_txd),
	.system_uart_0_io_rxd   (system_uart_0_io_rxd),
	// (aw)
	//.system_gpio_0_io_read  (system_gpio_0_io_read),
	//.system_gpio_0_io_write (system_gpio_0_io_write),
	//.system_gpio_0_io_writeEnable(system_gpio_0_io_writeEnable),
	//.system_i2c_0_io_sda_write(system_i2c_0_io_sda_write),
	//.system_i2c_0_io_sda_read(system_i2c_0_io_sda_read),
	//.system_i2c_0_io_scl_write(system_i2c_0_io_scl_write),
	//.system_i2c_0_io_scl_read(system_i2c_0_io_scl_read),

	.io_apbSlave_0_PADDR	(eth_apb3_paddr),
	.io_apbSlave_0_PSEL	 (eth_apb3_psel),
	.io_apbSlave_0_PENABLE  (eth_apb3_penable),
	.io_apbSlave_0_PREADY   (eth_apb3_pready),
	.io_apbSlave_0_PWRITE   (eth_apb3_pwrite),
	.io_apbSlave_0_PWDATA   (eth_apb3_pwdata),
	.io_apbSlave_0_PRDATA   (eth_apb3_prdata),
	.io_apbSlave_0_PSLVERROR(eth_apb3_pslverror),
	.io_apbSlave_1_PADDR	(dma_apb3_paddr),
	.io_apbSlave_1_PSEL	 (dma_apb3_psel),
	.io_apbSlave_1_PENABLE  (dma_apb3_penable),
	.io_apbSlave_1_PREADY   (dma_apb3_pready),
	.io_apbSlave_1_PWRITE   (dma_apb3_pwrite),
	.io_apbSlave_1_PWDATA   (dma_apb3_pwdata),
	.io_apbSlave_1_PRDATA   (dma_apb3_prdata),
	.io_apbSlave_1_PSLVERROR(dma_apb3_pslverror),
	.io_apbSlave_2_PADDR	(io_apbSlave_2_PADDR),
	.io_apbSlave_2_PSEL	 (io_apbSlave_2_PSEL),
	.io_apbSlave_2_PENABLE  (io_apbSlave_2_PENABLE),
	.io_apbSlave_2_PREADY   (io_apbSlave_2_PREADY),
	.io_apbSlave_2_PWRITE   (io_apbSlave_2_PWRITE),
	.io_apbSlave_2_PWDATA   (io_apbSlave_2_PWDATA),
	.io_apbSlave_2_PRDATA   (io_apbSlave_2_PRDATA),
	.io_apbSlave_2_PSLVERROR(io_apbSlave_2_PSLVERROR),

	.userInterruptA		 (dma_interrupts[0]),				
	.userInterruptB		 (dma_interrupts[1]),

	.io_ddrA_aw_valid(io_ddrA_aw_valid),
	.io_ddrA_aw_ready(io_ddrA_aw_ready),
	.io_ddrA_aw_payload_addr(io_ddrA_aw_payload_addr_i),
	.io_ddrA_aw_payload_id(io_ddrA_aw_payload_id_i),
	.io_ddrA_aw_payload_len(io_ddrA_aw_payload_len),
	.io_ddrA_aw_payload_size(io_ddrA_aw_payload_size),
	.io_ddrA_aw_payload_burst(io_ddrA_aw_payload_burst),
	.io_ddrA_aw_payload_lock(io_ddrA_aw_payload_lock),
	.io_ddrA_aw_payload_prot(),
	.io_ddrA_aw_payload_qos(io_ddrA_aw_payload_qos),
	.io_ddrA_aw_payload_cache(io_ddrA_aw_payload_cache),
	.io_ddrA_aw_payload_region(),
	.io_ddrA_ar_valid(io_ddrA_ar_valid),
	.io_ddrA_ar_ready(io_ddrA_ar_ready),
	.io_ddrA_ar_payload_addr(io_ddrA_ar_payload_addr_i),
	.io_ddrA_ar_payload_id(io_ddrA_ar_payload_id_i),
	.io_ddrA_ar_payload_len(io_ddrA_ar_payload_len),
	.io_ddrA_ar_payload_size(io_ddrA_ar_payload_size),
	.io_ddrA_ar_payload_burst(io_ddrA_ar_payload_burst),
	.io_ddrA_ar_payload_lock(io_ddrA_ar_payload_lock),
	.io_ddrA_ar_payload_prot(),
	.io_ddrA_ar_payload_qos(io_ddrA_ar_payload_qos),
	.io_ddrA_ar_payload_cache(),
	.io_ddrA_ar_payload_region(),
	.io_ddrA_w_valid(io_ddrA_w_valid),
	.io_ddrA_w_ready(io_ddrA_w_ready),
	.io_ddrA_w_payload_data(io_ddrA_w_payload_data),
	.io_ddrA_w_payload_strb(io_ddrA_w_payload_strb),
	.io_ddrA_w_payload_last(io_ddrA_w_payload_last),
	.io_ddrA_b_valid(io_ddrA_b_valid),
	.io_ddrA_b_ready(io_ddrA_b_ready),
	.io_ddrA_b_payload_id(io_ddrA_b_payload_id_i),
	.io_ddrA_b_payload_resp(io_ddrA_b_payload_resp),
	.io_ddrA_r_valid(io_ddrA_r_valid),
	.io_ddrA_r_ready(io_ddrA_r_ready),
	.io_ddrA_r_payload_data(io_ddrA_r_payload_data),
	.io_ddrA_r_payload_id(io_ddrA_r_payload_id_i),
	.io_ddrA_r_payload_resp(io_ddrA_r_payload_resp),
	.io_ddrA_r_payload_last(io_ddrA_r_payload_last),

	.io_ddrMasters_0_aw_valid		  (dmaaxi_write_awvalid),
	.io_ddrMasters_0_aw_ready		  (dmaaxi_write_awready),
	.io_ddrMasters_0_aw_payload_addr   (dmaaxi_write_awaddr),
	.io_ddrMasters_0_aw_payload_id	 (4'd8),
	.io_ddrMasters_0_aw_payload_region (dmaaxi_write_awregion),
	.io_ddrMasters_0_aw_payload_len	(dmaaxi_write_awlen),
	.io_ddrMasters_0_aw_payload_size   (dmaaxi_write_awsize),
	.io_ddrMasters_0_aw_payload_burst  (dmaaxi_write_awburst),
	.io_ddrMasters_0_aw_payload_lock   (dmaaxi_write_awlock),
	.io_ddrMasters_0_aw_payload_cache  (dmaaxi_write_awcache),
	.io_ddrMasters_0_aw_payload_qos	(dmaaxi_write_awqos),
	.io_ddrMasters_0_aw_payload_prot   (dmaaxi_write_awprot),
	.io_ddrMasters_0_w_valid		   (dmaaxi_write_wvalid),
	.io_ddrMasters_0_w_ready		   (dmaaxi_write_wready),
	.io_ddrMasters_0_w_payload_data	(dmaaxi_write_wdata),
	.io_ddrMasters_0_w_payload_strb	(dmaaxi_write_wstrb),
	.io_ddrMasters_0_w_payload_last	(dmaaxi_write_wlast),
	.io_ddrMasters_0_b_valid		   (dmaaxi_write_bvalid),
	.io_ddrMasters_0_b_ready		   (dmaaxi_write_bready),
	.io_ddrMasters_0_b_payload_id	  (),
	.io_ddrMasters_0_b_payload_resp	(dmaaxi_write_bresp),
	.io_ddrMasters_0_ar_valid		  (dmaaxi_read_arvalid),
	.io_ddrMasters_0_ar_ready		  (dmaaxi_read_arready),
	.io_ddrMasters_0_ar_payload_addr   (dmaaxi_read_araddr),
	.io_ddrMasters_0_ar_payload_id	 (4'd7),
	.io_ddrMasters_0_ar_payload_region (dmaaxi_read_arregion),
	.io_ddrMasters_0_ar_payload_len	(dmaaxi_read_arlen),
	.io_ddrMasters_0_ar_payload_size   (dmaaxi_read_arsize),
	.io_ddrMasters_0_ar_payload_burst  (dmaaxi_read_arburst),
	.io_ddrMasters_0_ar_payload_lock   (dmaaxi_read_arlock),
	.io_ddrMasters_0_ar_payload_cache  (dmaaxi_read_arcache),
	.io_ddrMasters_0_ar_payload_qos	(dmaaxi_read_arqos),
	.io_ddrMasters_0_ar_payload_prot   (dmaaxi_read_arprot),
	.io_ddrMasters_0_r_valid		   (dmaaxi_read_rvalid),
	.io_ddrMasters_0_r_ready		   (dmaaxi_read_rready),
	.io_ddrMasters_0_r_payload_data	(dmaaxi_read_rdata),
	.io_ddrMasters_0_r_payload_id	  (),
	.io_ddrMasters_0_r_payload_resp	(dmaaxi_read_rresp),
	.io_ddrMasters_0_r_payload_last	(dmaaxi_read_rlast),
	.io_ddrMasters_0_clk			   (io_memoryClk),
	.io_ddrMasters_0_reset			 (io_ddrMasterReset),
	.system_spi_0_io_sclk_write		(system_spi_0_io_sclk_write),
	.system_spi_0_io_data_0_writeEnable(system_spi_0_io_data_0_writeEnable),
	.system_spi_0_io_data_0_read	   (system_spi_0_io_data_0_read),
	.system_spi_0_io_data_0_write	  (system_spi_0_io_data_0_write),
	.system_spi_0_io_data_1_writeEnable(system_spi_0_io_data_1_writeEnable),
	.system_spi_0_io_data_1_read	   (system_spi_0_io_data_1_read),
	.system_spi_0_io_data_1_write	  (system_spi_0_io_data_1_write),
	.system_spi_0_io_ss				(system_spi_0_io_ss),

	.system_spi_1_io_sclk_write(sd_clk),
	.system_spi_1_io_data_0_writeEnable(sd_cmd_OE),
	.system_spi_1_io_data_0_read(sd_cmd_IN),
	.system_spi_1_io_data_0_write(sd_cmd_OUT),
	.system_spi_1_io_data_1_writeEnable(sd_dat_OE[0]),
	.system_spi_1_io_data_1_read(sd_dat_IN[0]),
	.system_spi_1_io_data_1_write(sd_dat_OUT[0]),
	.system_spi_1_io_data_2_writeEnable(),
	.system_spi_1_io_data_2_read(),
	.system_spi_1_io_data_2_write(),
	.system_spi_1_io_data_3_writeEnable(),
	.system_spi_1_io_data_3_read(),
	.system_spi_1_io_data_3_write(),
	.system_spi_1_io_ss(sd_dat_OUT[3]),

	.jtagCtrl_tck	(jtag_inst1_TCK),
	.jtagCtrl_tdi	(jtag_inst1_TDI),
	.jtagCtrl_tdo	(jtag_inst1_TDO),
	.jtagCtrl_enable (jtag_inst1_SEL),
	.jtagCtrl_capture(jtag_inst1_CAPTURE),
	.jtagCtrl_shift  (jtag_inst1_SHIFT),
	.jtagCtrl_update (jtag_inst1_UPDATE),
	.jtagCtrl_reset  (jtag_inst1_RESET),
	
	// (aw)
	.axiA_awready(apuAXIL_awready),
	.axiA_awlen(apuAXIL_awlen),
	.axiA_awsize(apuAXIL_awsize),
	.axiA_arburst(apuAXIL_arburst),
	.axiA_awlock(apuAXIL_awlock),
	.axiA_arcache(apuAXIL_arcache),
	.axiA_awqos(apuAXIL_awqos),
	.axiA_awprot(apuAXIL_awprot),
	.axiA_arsize(apuAXIL_arsize),
	.axiA_arregion(apuAXIL_arregion),
	.axiA_arready(apuAXIL_arready),
	.axiA_arqos(apuAXIL_arqos),
	.axiA_arprot(apuAXIL_arprot),
	.axiA_arlock(apuAXIL_arlock),
	.axiA_arlen(apuAXIL_arlen),
	.axiA_arid(apuAXIL_arid),
	.axiA_awcache(apuAXIL_awcache),
	.axiA_awburst(apuAXIL_awburst),
	.axiA_awaddr(apuAXIL_awaddr),
	.axiAInterrupt(1'b0),
	.axiA_rlast(apuAXIL_rlast),
	.axiA_araddr(apuAXIL_araddr),
	.axiA_wvalid(apuAXIL_wvalid),
	.axiA_wready(apuAXIL_wready),
	.axiA_wdata(apuAXIL_wdata),
	.axiA_wstrb(apuAXIL_wstrb),
	.axiA_wlast(apuAXIL_wlast),
	.axiA_bvalid(apuAXIL_bvalid),
	.axiA_bready(apuAXIL_bready),
	.axiA_bid(apuAXIL_bid),
	.axiA_bresp(apuAXIL_bresp),
	.axiA_rvalid(apuAXIL_rvalid),
	.axiA_rready(apuAXIL_rready),
	.axiA_rdata(apuAXIL_rdata),
	.axiA_rid(apuAXIL_rid),
	.axiA_rresp(apuAXIL_rresp),
	.axiA_arvalid(apuAXIL_arvalid),
	.axiA_awid(apuAXIL_awid),
	.axiA_awregion(apuAXIL_awregion),
	.axiA_awvalid(apuAXIL_awvalid)
);

/////////////////////////////////////////////////////////////////////////////
// (aw)

wire apuAXIL_awready;
wire[7:0] apuAXIL_awlen;
wire[2:0] apuAXIL_awsize;
wire[1:0] apuAXIL_arburst;
wire apuAXIL_awlock;
wire[3:0] apuAXIL_arcache;
wire[3:0] apuAXIL_awqos;
wire[2:0] apuAXIL_awprot;
wire[2:0] apuAXIL_arsize;
wire[3:0] apuAXIL_arregion;
wire apuAXIL_arready;
wire[3:0] apuAXIL_arqos;
wire[2:0] apuAXIL_arprot;
wire apuAXIL_arlock;
wire[7:0] apuAXIL_arlen;
wire[7:0] apuAXIL_arid;
wire[3:0] apuAXIL_awcache;
wire[1:0] apuAXIL_awburst;
wire[31:0] apuAXIL_awaddr;
wire apuAXIL_rlast;
wire[31:0] apuAXIL_araddr;
wire apuAXIL_wvalid;
wire apuAXIL_wready;
wire[31:0] apuAXIL_wdata;
wire[3:0] apuAXIL_wstrb;
wire apuAXIL_wlast;
wire apuAXIL_bvalid;
wire apuAXIL_bready;
wire[7:0] apuAXIL_bid = 8'b0;
wire[1:0] apuAXIL_bresp;
wire apuAXIL_rvalid;
wire apuAXIL_rready;
wire[31:0] apuAXIL_rdata;
wire[7:0] apuAXIL_rid = 8'b0;
wire[1:0] apuAXIL_rresp;
wire apuAXIL_arvalid;
wire[7:0] apuAXIL_awid;
wire[3:0] apuAXIL_awregion;
wire apuAXIL_awvalid;

//wire areset;
wire aresetn;
assign aresetn = ~io_systemReset;

Vsp_core myVsp_core (
	.aresetn(aresetn),
	.aclk(io_systemClk), // 200 MHz
	.pixrxclk(io_memoryClk), // 100 MHz
	.memclk(io_vspmemClk),
	
	.resetnMemclk(io_vspmemResetn),

	.apuAXIL_araddr(apuAXIL_araddr),
	.apuAXIL_arprot(apuAXIL_arprot),
	.apuAXIL_arready(apuAXIL_arready),
	.apuAXIL_arvalid(apuAXIL_arvalid),

	.apuAXIL_rdata(apuAXIL_rdata),
	.apuAXIL_rready(apuAXIL_rready),
	.apuAXIL_rresp(apuAXIL_rresp),
	.apuAXIL_rvalid(apuAXIL_rvalid),
	.apuAXIL_rlast(apuAXIL_rlast),

	.apuAXIL_awaddr(apuAXIL_awaddr),
	.apuAXIL_awprot(apuAXIL_awprot),
	.apuAXIL_awready(apuAXIL_awready),
	.apuAXIL_awvalid(apuAXIL_awvalid),

	.apuAXIL_wdata(apuAXIL_wdata),
	.apuAXIL_wready(apuAXIL_wready),
	.apuAXIL_wstrb(apuAXIL_wstrb),
	.apuAXIL_wvalid(apuAXIL_wvalid),

	.apuAXIL_bready(apuAXIL_bready),
	.apuAXIL_bresp(apuAXIL_bresp),
	.apuAXIL_bvalid(apuAXIL_bvalid),

	.clk_byte_HS(clk_byte_HS),
	.mipirx_RESET_N(mipirx_RESET_N),
	.mipirx_RST0_N(mipirx_RST0_N),
	.mipirx_ERR_CONTROL_LAN0(mipirx_ERR_CONTROL_LAN0),
	.mipirx_ERR_CONTROL_LAN1(mipirx_ERR_CONTROL_LAN1),
	.mipirx_ERR_CONTROL_LAN2(mipirx_ERR_CONTROL_LAN2),
	.mipirx_ERR_CONTROL_LAN3(mipirx_ERR_CONTROL_LAN3),
	.mipirx_ERR_ESC_LAN0(mipirx_ERR_ESC_LAN0),
	.mipirx_ERR_ESC_LAN1(mipirx_ERR_ESC_LAN1),
	.mipirx_ERR_ESC_LAN2(mipirx_ERR_ESC_LAN2),
	.mipirx_ERR_ESC_LAN3(mipirx_ERR_ESC_LAN3),
	.mipirx_ERR_SOT_SYNC_HS_LAN0(mipirx_ERR_SOT_SYNC_HS_LAN0),
	.mipirx_ERR_SOT_SYNC_HS_LAN1(mipirx_ERR_SOT_SYNC_HS_LAN1),
	.mipirx_ERR_SOT_SYNC_HS_LAN2(mipirx_ERR_SOT_SYNC_HS_LAN2),
	.mipirx_ERR_SOT_SYNC_HS_LAN3(mipirx_ERR_SOT_SYNC_HS_LAN3),
	.mipirx_ESC_CLK_LAN0(mipirx_ESC_CLK_LAN0),
	.mipirx_ESC_CLK_LAN1(mipirx_ESC_CLK_LAN1),
	.mipirx_ESC_CLK_LAN2(mipirx_ESC_CLK_LAN2),
	.mipirx_ESC_CLK_LAN3(mipirx_ESC_CLK_LAN3),
	.mipirx_RX_DATA_HS_LAN0(mipirx_RX_DATA_HS_LAN0),
	.mipirx_RX_DATA_HS_LAN1(mipirx_RX_DATA_HS_LAN1),
	.mipirx_RX_DATA_HS_LAN2(mipirx_RX_DATA_HS_LAN2),
	.mipirx_RX_DATA_HS_LAN3(mipirx_RX_DATA_HS_LAN3),
	.mipirx_RX_SKEW_CAL_HS_LAN0(mipirx_RX_SKEW_CAL_HS_LAN0),
	.mipirx_RX_SKEW_CAL_HS_LAN1(mipirx_RX_SKEW_CAL_HS_LAN1),
	.mipirx_RX_SKEW_CAL_HS_LAN2(mipirx_RX_SKEW_CAL_HS_LAN2),
	.mipirx_RX_SKEW_CAL_HS_LAN3(mipirx_RX_SKEW_CAL_HS_LAN3),
	.mipirx_RX_SYNC_HS_LAN0(mipirx_RX_SYNC_HS_LAN0),
	.mipirx_RX_SYNC_HS_LAN1(mipirx_RX_SYNC_HS_LAN1),
	.mipirx_RX_SYNC_HS_LAN2(mipirx_RX_SYNC_HS_LAN2),
	.mipirx_RX_SYNC_HS_LAN3(mipirx_RX_SYNC_HS_LAN3),
	.mipirx_RX_ULPS_ACTIVE_CLK_NOT(mipirx_RX_ULPS_ACTIVE_CLK_NOT),
	.mipirx_RX_ULPS_ACTIVE_NOT_LAN0(mipirx_RX_ULPS_ACTIVE_NOT_LAN0),
	.mipirx_RX_ULPS_ACTIVE_NOT_LAN1(mipirx_RX_ULPS_ACTIVE_NOT_LAN1),
	.mipirx_RX_ULPS_ACTIVE_NOT_LAN2(mipirx_RX_ULPS_ACTIVE_NOT_LAN2),
	.mipirx_RX_ULPS_ACTIVE_NOT_LAN3(mipirx_RX_ULPS_ACTIVE_NOT_LAN3),
	.mipirx_RX_ULPS_CLK_NOT(mipirx_RX_ULPS_CLK_NOT),
	.mipirx_RX_ULPS_ESC_LAN0(mipirx_RX_ULPS_ESC_LAN0),
	.mipirx_RX_ULPS_ESC_LAN1(mipirx_RX_ULPS_ESC_LAN1),
	.mipirx_RX_ULPS_ESC_LAN2(mipirx_RX_ULPS_ESC_LAN2),
	.mipirx_RX_ULPS_ESC_LAN3(mipirx_RX_ULPS_ESC_LAN3),
	.mipirx_RX_VALID_HS_LAN0(mipirx_RX_VALID_HS_LAN0),
	.mipirx_RX_VALID_HS_LAN1(mipirx_RX_VALID_HS_LAN1),
	.mipirx_RX_VALID_HS_LAN2(mipirx_RX_VALID_HS_LAN2),
	.mipirx_RX_VALID_HS_LAN3(mipirx_RX_VALID_HS_LAN3),
	.mipirx_STOPSTATE_LAN0(mipirx_STOPSTATE_LAN0),
	.mipirx_STOPSTATE_LAN1(mipirx_STOPSTATE_LAN1),
	.mipirx_STOPSTATE_LAN2(mipirx_STOPSTATE_LAN2),
	.mipirx_STOPSTATE_LAN3(mipirx_STOPSTATE_LAN3),

	.ddrAXI_arid(ddrAXI_arid),
	.ddrAXI_araddr(ddrAXI_araddr),
	.ddrAXI_arburst(ddrAXI_arburst),
	.ddrAXI_arcache(ddrAXI_arcache),
	.ddrAXI_arlen(ddrAXI_arlen),
	.ddrAXI_arlock(ddrAXI_arlock),
	.ddrAXI_arprot(ddrAXI_arprot),
	.ddrAXI_arqos(ddrAXI_arqos),
	.ddrAXI_arready(ddrAXI_arready),
	.ddrAXI_arregion(ddrAXI_arregion),
	.ddrAXI_arsize(ddrAXI_arsize),
	.ddrAXI_arvalid(ddrAXI_arvalid),

	.ddrAXI_rid(ddrAXI_rid),
	.ddrAXI_rdata(ddrAXI_rdata),
	.ddrAXI_rlast(ddrAXI_rlast),
	.ddrAXI_rresp(ddrAXI_rresp),
	.ddrAXI_rready(ddrAXI_rready),
	.ddrAXI_rvalid(ddrAXI_rvalid),

	.ddrAXI_awid(ddrAXI_awid),
	.ddrAXI_awaddr(ddrAXI_awaddr),
	.ddrAXI_awburst(ddrAXI_awburst),
	.ddrAXI_awcache(ddrAXI_awcache),
	.ddrAXI_awlen(ddrAXI_awlen),
	.ddrAXI_awlock(ddrAXI_awlock),
	.ddrAXI_awprot(ddrAXI_awprot),
	.ddrAXI_awqos(ddrAXI_awqos),
	.ddrAXI_awready(ddrAXI_awready),
	.ddrAXI_awregion(ddrAXI_awregion),
	.ddrAXI_awsize(ddrAXI_awsize),
	.ddrAXI_awvalid(ddrAXI_awvalid),

	.ddrAXI_wdata(ddrAXI_wdata),
	.ddrAXI_wlast(ddrAXI_wlast),
	.ddrAXI_wready(ddrAXI_wready),
	.ddrAXI_wstrb(ddrAXI_wstrb),
	.ddrAXI_wvalid(ddrAXI_wvalid),

	.ddrAXI_bid(ddrAXI_bid),
	.ddrAXI_bready(ddrAXI_bready),
	.ddrAXI_bresp(ddrAXI_bresp),
	.ddrAXI_bvalid(ddrAXI_bvalid),

	.scl_in(scl_in),
	.scl_out(scl_out),
	.scl_tri(scl_tri),

	.sda_in(sda_in),
	.sda_out(sda_out),
	.sda_tri(sda_tri),

	.cs(cs),
	.sclk(sclk),
	.mosi(mosi),

	.rgb0_r(rgb0_r),
	.rgb0_g(rgb0_g),
	.rgb0_b(rgb0_b),
	.rgb1_r(rgb1_r),
	.rgb1_g(rgb1_g),
	.rgb1_b(rgb1_b),

	.nslp(nslp),
	.m0(m0),
	.m0z(m0z),
	.m1(m1),
	.m1z(m1z),
	.dir(dir),
	.step(step),

	.probe(probe)
);

endmodule

