////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.              
//
// This   document  contains  proprietary information  which   is        
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// original license agreement is included in it's original               
// unmodified form immediately below this header.                        
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////////////////////////////////////////////////////////////////////////////////
#pragma once
/************************** Project Header File ***************************/
#define PRINTF_EN           1
#define TEST_MODE           0               //0 : Normal Mode; 
                                            //1 : Link partner Test Mode;

#define PAT_NUM 	        0
#define PAT_DLEN	        100
#define PAT_IPG		        100
#define PAT_TYPE	        0               //0 : UDP Pattern; 
                                            //1 : MAC Pattern;
#define DST_MAC_H 	        0xffff
#define DST_MAC_L 	        0xffffffff
#define SRC_MAC_H 	        0xeae8
#define SRC_MAC_L 	        0x5e0060c8
#define SRC_IP 		        0xc0a80164
#define DST_IP 		        0xc0a80165
#define SRC_PORT	        0x0521
#define DST_PORT	        0x2715

/************************** System Header File ***************************/
#define PHY_ADDR            0x7

/************************** HW Header File ***************************/
#define TSEMAC_CSR          IO_APB_SLAVE_0_INPUT

/************************** Application Header File ***************************/
#define TX_ENA_MASK    		0xFFFFFFFE
#define RX_ENA_MASK    		0xFFFFFFFD
#define XON_GEN_MASK 		0xFFFFFFFB
#define PROMIS_EN_MASK   	0xFFFFFFEF
#define PAD_EN_MASK   		0xFFFFFFDF
#define CRC_FWD_MASK   		0xFFFFFFBF
#define PAUSE_IGNORE_MASK   0xFFFFFEFF
#define TX_ADDR_INS_MASK   	0xFFFFFBFF
#define LOOP_ENA_MASK   	0xFFFF7FFF
#define ETH_SPEED_MASK   	0xFFF8FFFF
#define XOFF_GEN_MASK 		0xFFBFFFFF
#define CNT_RST_MASK 		0x7FFFFFFF
