"/opt/Efinix/efinity/2025.1/bin/efx_map" --project "vsp_core" --root "vsp_core" --write-efx-verilog "/home/mpsitech/fpgacode/titdvk/vsp_core/outflow/vsp_core.map.v" --write-premap-module "/home/mpsitech/fpgacode/titdvk/vsp_core/outflow/vsp_core.elab.vdb" --binary-db "/home/mpsitech/fpgacode/titdvk/vsp_core/outflow/vsp_core.vdb" --device "Ti180M484" --family "Titanium" --veri_option "verilog_mode=verilog_2k,vhdl_mode=vhdl_2008" --work-dir "/home/mpsitech/fpgacode/titdvk/vsp_core/work_syn" --output-dir "/home/mpsitech/fpgacode/titdvk/vsp_core/outflow" --project-xml "/home/mpsitech/fpgacode/titdvk/vsp_core/vsp_core.xml" --I "/home/mpsitech/fpgacode/titdvk/vsp_core" --I "/home/mpsitech/fpgacode/titdvk/vsp_core/ip/Dpbram_efnx_size8kB_a32b128" --I "/home/mpsitech/fpgacode/titdvk/vsp_core/ip/Dpbram_efnx_size4kB_a64b64" --I "/home/mpsitech/fpgacode/titdvk/vsp_core/ip/Dpbram_efnx_size16kB_a8b8" --I "/home/mpsitech/fpgacode/titdvk/vsp_core/ip/Dpbram_efnx_size16kB_a32b128" --I "/home/mpsitech/fpgacode/titdvk/vsp_core/ip/Dpbram_efnx_size2kB_a32b32" --I "/home/mpsitech/fpgacode/titdvk/vsp_core/ip/Dpbram_efnx_size2kB_a8b8" --I "/home/mpsitech/fpgacode/titdvk/vsp_core/ip/Dpbram_efnx_size4kB_a32b32" --I "/home/mpsitech/fpgacode/titdvk/vsp_core/ip/Dpbram_efnx_size8kB_a64b64" --I "/home/mpsitech/fpgacode/titdvk/vsp_core/ip/Dpbram_efnx_size2kB_a64b64" --I "/home/mpsitech/fpgacode/titdvk/vsp_core/ip/Dpbram_efnx_size32kb_a32b8" --I "/home/mpsitech/fpgacode/titdvk/vsp_core/ip/Csi2_hard_mipi_rx_efnx_w4"