-- file Camif.vhd
-- Camif easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Camif is
	generic (
		fMclk: natural -- in kHz
	);
	port (
		reset: in std_logic;
		mclk: in std_logic;
		resetPixrxclk: in std_logic;
		pixrxclk: in std_logic;
		tkclk: in std_logic;

		NRowRaw: in std_logic_vector(11 downto 0);
		NCol: in std_logic_vector(10 downto 0);

		toVideoinAXIS_tready: in std_logic;
		toVideoinAXIS_tvalid: out std_logic;
		toVideoinAXIS_tdata: out std_logic_vector(23 downto 0);
		toVideoinAXIS_tlast: out std_logic;

		reqInvConfig: in std_logic;
		ackInvConfig: out std_logic;

		configHdrNotFix: in std_logic_vector(7 downto 0);
		configSynthNotLive: in std_logic_vector(7 downto 0);

		reqInvConfigSynth: in std_logic;
		ackInvConfigSynth: out std_logic;

		configSynthTixVSynthmode: in std_logic_vector(7 downto 0);
		configSynthTFramepad: in std_logic_vector(15 downto 0);
		configSynthTLinepad: in std_logic_vector(7 downto 0);

		reqInvSetReg: in std_logic;
		ackInvSetReg: out std_logic;

		setRegAddr: in std_logic_vector(15 downto 0);
		setRegVal: in std_logic_vector(7 downto 0);

		reqInvGetReg: in std_logic;
		ackInvGetReg: out std_logic;

		getRegAddr: in std_logic_vector(15 downto 0);
		getRegVal: out std_logic_vector(7 downto 0);

		reqInvModReg: in std_logic;
		ackInvModReg: out std_logic;

		modRegAddr: in std_logic_vector(15 downto 0);
		modRegMask: in std_logic_vector(7 downto 0);
		modRegVal: in std_logic_vector(7 downto 0);

		reqInvSetCorereg: in std_logic;
		ackInvSetCorereg: out std_logic;

		setCoreregAddr: in std_logic_vector(7 downto 0);
		setCoreregVal: in std_logic_vector(31 downto 0);

		reqInvGetCorereg: in std_logic;
		ackInvGetCorereg: out std_logic;

		getCoreregAddr: in std_logic_vector(7 downto 0);
		getCoreregVal: out std_logic_vector(31 downto 0);

		rng: in std_logic;

		vsync: out std_logic;
		ixTExp: out std_logic_vector(3 downto 0);

		clk_byte_HS: in std_logic;

		mipirx_RESET_N: out std_logic;
		mipirx_RST0_N: out std_logic;
		mipirx_ERR_CONTROL_LAN0: in std_logic;
		mipirx_ERR_CONTROL_LAN1: in std_logic;
		mipirx_ERR_CONTROL_LAN2: in std_logic;
		mipirx_ERR_CONTROL_LAN3: in std_logic;
		mipirx_ERR_ESC_LAN0: in std_logic;
		mipirx_ERR_ESC_LAN1: in std_logic;
		mipirx_ERR_ESC_LAN2: in std_logic;
		mipirx_ERR_ESC_LAN3: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN0: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN1: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN2: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN3: in std_logic;
		mipirx_ESC_CLK_LAN0: in std_logic;
		mipirx_ESC_CLK_LAN1: in std_logic;
		mipirx_ESC_CLK_LAN2: in std_logic;
		mipirx_ESC_CLK_LAN3: in std_logic;
		mipirx_RX_DATA_HS_LAN0: in std_logic_vector(15 downto 0);
		mipirx_RX_DATA_HS_LAN1: in std_logic_vector(15 downto 0);
		mipirx_RX_DATA_HS_LAN2: in std_logic_vector(15 downto 0);
		mipirx_RX_DATA_HS_LAN3: in std_logic_vector(15 downto 0);
		mipirx_RX_SKEW_CAL_HS_LAN0: in std_logic;
		mipirx_RX_SKEW_CAL_HS_LAN1: in std_logic;
		mipirx_RX_SKEW_CAL_HS_LAN2: in std_logic;
		mipirx_RX_SKEW_CAL_HS_LAN3: in std_logic;
		mipirx_RX_SYNC_HS_LAN0: in std_logic;
		mipirx_RX_SYNC_HS_LAN1: in std_logic;
		mipirx_RX_SYNC_HS_LAN2: in std_logic;
		mipirx_RX_SYNC_HS_LAN3: in std_logic;
		mipirx_RX_ULPS_ACTIVE_CLK_NOT: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN0: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN1: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN2: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN3: in std_logic;
		mipirx_RX_ULPS_CLK_NOT: in std_logic;
		mipirx_RX_ULPS_ESC_LAN0: in std_logic;
		mipirx_RX_ULPS_ESC_LAN1: in std_logic;
		mipirx_RX_ULPS_ESC_LAN2: in std_logic;
		mipirx_RX_ULPS_ESC_LAN3: in std_logic;
		mipirx_RX_VALID_HS_LAN0: in std_logic;
		mipirx_RX_VALID_HS_LAN1: in std_logic;
		mipirx_RX_VALID_HS_LAN2: in std_logic;
		mipirx_RX_VALID_HS_LAN3: in std_logic;
		mipirx_STOPSTATE_LAN0: in std_logic;
		mipirx_STOPSTATE_LAN1: in std_logic;
		mipirx_STOPSTATE_LAN2: in std_logic;
		mipirx_STOPSTATE_LAN3: in std_logic;

		scl_in: in std_logic;
		scl_out: out std_logic;
		scl_tri: out std_logic;

		sda_in: in std_logic;
		sda_out: out std_logic;
		sda_tri: out std_logic;

		RxDataHS0: in std_logic_vector(15 downto 0);
		RxDataHS1: in std_logic_vector(15 downto 0);
		RxDataHS2: in std_logic_vector(15 downto 0);
		RxDataHS3: in std_logic_vector(15 downto 0);

		datatype_dbg: out std_logic_vector(5 downto 0);
		mipiAXIS_dbg: out std_logic_vector(3 downto 0);
		video_out_dbg: out std_logic_vector(3 downto 0);

		stateConfig_dbg: out std_logic_vector(7 downto 0)
	);
end Camif;

architecture Rtl of Camif is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component I2cmaster_v1_0 is
		generic (
			fMclk: natural := 50000;
			clkFastNotStd: std_logic := '0';
			clkFastplusNotFast: std_logic := '0'
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;

			req: in std_logic;
			ack: out std_logic;
			dne: out std_logic;

			devaddr: in std_logic_vector(7 downto 0);
			r16Not8: in std_logic;
			d16Not8: in std_logic;
			readNotWrite: in std_logic;
			readAradNotArd: in std_logic;
			writeAdNotArd: in std_logic;
			regaddr: in std_logic_vector(15 downto 0);
			send: in std_logic_vector(15 downto 0);
			recv: out std_logic_vector(15 downto 0);

			scl_in: in std_logic;
			scl_out: out std_logic;
			scl_tri: out std_logic;

			sda_in: in std_logic;
			sda_out: out std_logic;
			sda_tri: out std_logic
		);
	end component;

	component Csi2_hard_mipi_rx_efnx_w4 is
		port (
			reset_n: in std_logic;
			reset_byte_HS_n: in std_logic;
			reset_pixel_n: in std_logic;
			axi_reset_n: in std_logic;
			clk: in std_logic;
			clk_byte_HS: in std_logic;
			clk_pixel: in std_logic;
			axi_clk: in std_logic;

			RxClkEsc: in std_logic_vector(3 downto 0);
			RxErrEsc: in std_logic_vector(3 downto 0);
			RxErrControl: in std_logic_vector(3 downto 0);
			RxErrSotSyncHS: in std_logic_vector(3 downto 0);
			RxUlpsEsc: in std_logic_vector(3 downto 0);
			RxUlpsActiveNot: in std_logic_vector(3 downto 0);
			RxSkewCalHS: in std_logic_vector(3 downto 0);
			RxStopState: in std_logic_vector(3 downto 0);
			RxSyncHS: in std_logic_vector(3 downto 0);

			RxValidHS0: in std_logic_vector(1 downto 0);
			RxValidHS1: in std_logic_vector(1 downto 0);
			RxValidHS2: in std_logic_vector(1 downto 0);
			RxValidHS3: in std_logic_vector(1 downto 0);
			RxValidHS4: in std_logic_vector(1 downto 0);
			RxValidHS5: in std_logic_vector(1 downto 0);
			RxValidHS6: in std_logic_vector(1 downto 0);
			RxValidHS7: in std_logic_vector(1 downto 0);

			irq: out std_logic;
			pixel_per_clk: out std_logic_vector(3 downto 0);
			pixel_data: out std_logic_vector(63 downto 0);
			pixel_data_valid: out std_logic;
			datatype: out std_logic_vector(5 downto 0);
			shortpkt_data_field: out std_logic_vector(15 downto 0);
			word_count: out std_logic_vector(15 downto 0);
			vc: out std_logic_vector(1 downto 0);

			vsync_vc0: out std_logic;
			vsync_vc1: out std_logic;
			vsync_vc2: out std_logic;
			vsync_vc3: out std_logic;
			vsync_vc4: out std_logic;
			vsync_vc5: out std_logic;
			vsync_vc6: out std_logic;
			vsync_vc7: out std_logic;
			vsync_vc8: out std_logic;
			vsync_vc9: out std_logic;
			vsync_vc10: out std_logic;
			vsync_vc11: out std_logic;
			vsync_vc12: out std_logic;
			vsync_vc13: out std_logic;
			vsync_vc14: out std_logic;
			vsync_vc15: out std_logic;

			hsync_vc0: out std_logic;
			hsync_vc1: out std_logic;
			hsync_vc2: out std_logic;
			hsync_vc3: out std_logic;
			hsync_vc4: out std_logic;
			hsync_vc5: out std_logic;
			hsync_vc6: out std_logic;
			hsync_vc7: out std_logic;
			hsync_vc8: out std_logic;
			hsync_vc9: out std_logic;
			hsync_vc10: out std_logic;
			hsync_vc11: out std_logic;
			hsync_vc12: out std_logic;
			hsync_vc13: out std_logic;
			hsync_vc14: out std_logic;
			hsync_vc15: out std_logic;

			axi_araddr: in std_logic_vector(5 downto 0);
			axi_arready: out std_logic;
			axi_arvalid: in std_logic;
			axi_rdata: out std_logic_vector(31 downto 0);
			axi_rready: in std_logic;
			axi_rvalid: out std_logic;
			axi_awaddr: in std_logic_vector(5 downto 0);
			axi_awready: out std_logic;
			axi_awvalid: in std_logic;
			axi_wdata: in std_logic_vector(31 downto 0);
			axi_wready: out std_logic;
			axi_wvalid: in std_logic;
			axi_bready: in std_logic;
			axi_bvalid: out std_logic;

			RxUlpsClkNot: in std_logic_vector(0 downto 0);
			RxUlpsActiveClkNot: in std_logic_vector(0 downto 0);

			RxDataHS0: in std_logic_vector(15 downto 0);
			RxDataHS1: in std_logic_vector(15 downto 0);
			RxDataHS2: in std_logic_vector(15 downto 0);
			RxDataHS3: in std_logic_vector(15 downto 0);
			RxDataHS4: in std_logic_vector(15 downto 0);
			RxDataHS5: in std_logic_vector(15 downto 0);
			RxDataHS6: in std_logic_vector(15 downto 0);
			RxDataHS7: in std_logic_vector(15 downto 0)
		);
	end component;

	component Spram_v1_0_size2kB_w8 is
		port (
			reset: in std_logic;
			clk: in std_logic;

			en: in std_logic;
			we: in std_logic;

			a: in std_logic_vector(10 downto 0);
			drd: out std_logic_vector(7 downto 0);
			dwr: in std_logic_vector(7 downto 0)
		);
	end component;

	component Sprsaxisfwd_v1_0 is
		generic (
			wSize: natural range 3 to 16 := 12;
			wIxHshk: natural range 4 to 8 := 4;
			wIxData: natural range 2 to 6 := 4;
			wData: natural range 8 to 256 := 64;
			wUser: natural range 1 to 96 := 6
		);
		port (
			resetIgrclk: in std_logic;
			igrclk: in std_logic;

			reset: in std_logic;
			mclk: in std_logic;

			igrAXIS_tready: out std_logic;
			igrAXIS_tvalid: in std_logic;
			igrAXIS_tdata: in std_logic_vector(wData-1 downto 0);
			igrAXIS_tkeep: in std_logic_vector(wData/8-1 downto 0);
			igrAXIS_tlast: in std_logic;
			igrAXIS_tuser: in std_logic_vector(wUser-1 downto 0);

			enEgr: in std_logic;

			egrAXIS_tready: in std_logic;
			egrAXIS_tvalid: out std_logic;
			egrAXIS_tdata: out std_logic_vector(wData-1 downto 0);
			egrAXIS_tkeep: out std_logic_vector(wData/8-1 downto 0);
			egrAXIS_tlast: out std_logic;
			egrAXIS_tuser: out std_logic_vector(wUser-1 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant tixVSynthmodeRgb: std_logic_vector(7 downto 0) := x"00";
	constant tixVSynthmodeHdr: std_logic_vector(7 downto 0) := x"01";
	constant tixVSynthmodeChk: std_logic_vector(7 downto 0) := x"02";

	constant tixVFormatRaw8: std_logic_vector(7 downto 0) := x"2A";
	constant tixVFormatRaw10: std_logic_vector(7 downto 0) := x"2B";
	constant tixVFormatRaw12: std_logic_vector(7 downto 0) := x"2C";
	constant tixVFormatRaw14: std_logic_vector(7 downto 0) := x"2D";

	---- bytehsclk wiring and reset (bytehsclk)
	type stateBytehsclk_t is (
		stateBytehsclkReset,
		stateBytehsclkRun
	);
	signal stateBytehsclk: stateBytehsclk_t;

	signal resetnBytehsclk: std_logic;

	signal reset_bytehsclk: std_logic;
	signal reset_to_bytehsclkm1: std_logic;
	signal reset_to_bytehsclkm2: std_logic;

	-- IP sigs.bytehsclk.cust --- INSERT

	---- I2C configuration (config)
	type stateConfig_t is (
		stateConfigInit,
		stateConfigPrepA, stateConfigPrepB, stateConfigPrepC, stateConfigPrepD,
		stateConfigLoadA, stateConfigLoadB,
		stateConfigXfer,
		stateConfigStep,
		stateConfigPwupdnA, stateConfigPwupdnB,
		stateConfigInv
	);
	signal stateConfig: stateConfig_t;

	signal ackInvSetReg_sig: std_logic;
	signal ackInvGetReg_sig: std_logic;
	signal regVal: std_logic_vector(7 downto 0);
	signal ackInvModReg_sig: std_logic;
	signal enParrom: std_logic;

	signal aParrom_vec: std_logic_vector(10 downto 0);
	signal aParrom: natural range 0 to 2047;

	signal i2cReadNotWrite: std_logic;
	signal i2cRegaddr: std_logic_vector(15 downto 0);
	signal i2cSend: std_logic_vector(15 downto 0);

	-- IP sigs.config.cust --- INSERT

	---- MIPI RX core configuration (corecfg)
	type stateCorecfg_t is (
		stateCorecfgInit,
		stateCorecfgReadA, stateCorecfgReadB, stateCorecfgReadC,
		stateCorecfgWriteA, stateCorecfgWriteB, stateCorecfgWriteC,
		stateCorecfgInv
	);
	signal stateCorecfg: stateCorecfg_t;

	signal ackInvGetCorereg_sig: std_logic;
	signal getCoreregVal_sig: std_logic_vector(31 downto 0);
	signal ackInvSetCorereg_sig: std_logic;
	signal corecfgAXIL_araddr: std_logic_vector(5 downto 0);

	signal corecfgAXIL_awaddr: std_logic_vector(5 downto 0);
	signal corecfgAXIL_wdata: std_logic_vector(31 downto 0);

	-- IP sigs.corecfg.cust --- INSERT

	---- gearing from quad-RAW12 to dual-RAW12 (gear)

	signal enEgr: std_logic;
	signal pixrxclk_mclk: std_logic_vector(2 downto 0);

	signal video_out_tvalid: std_logic;
	signal video_out_tdata: std_logic_vector(23 downto 0);
	signal video_out_tlast: std_logic;
	signal video_out_tuser: std_logic_vector(5 downto 0);

	-- IP sigs.gear.cust --- INSERT

	---- live streaming operation (live)
	type stateLive_t is (
		stateLiveInit,
		stateLivePre,
		stateLiveRun,
		stateLiveUpdTExpA, stateLiveUpdTExpB
	);
	signal stateLive: stateLive_t;

	constant regShr0_0: std_logic_vector(15 downto 0) := x"3058";
	constant regShr0_1: std_logic_vector(15 downto 0) := x"3059";

	constant TExp0: std_logic_vector(15 downto 0) := x"0009"; -- longest, 66.47 ms / 2
	constant TExp1: std_logic_vector(15 downto 0) := x"0F44";
	constant TExp2: std_logic_vector(15 downto 0) := x"114A";
	constant TExp3: std_logic_vector(15 downto 0) := x"118B";
	constant TExp4: std_logic_vector(15 downto 0) := x"1193"; -- shortest, 17.1 us / 2

	constant rowRawStart: natural := 20;
	constant ixTExpLast: natural := 4;
	signal resetn: std_logic;
	signal resetnPixrxclk: std_logic;

	signal mipirx_ERR_CONTROL: std_logic_vector(3 downto 0);
	signal mipirx_ERR_ESC: std_logic_vector(3 downto 0);
	signal mipirx_ERR_SOT_SYNC_HS: std_logic_vector(3 downto 0);
	signal mipirx_ESC_CLK: std_logic_vector(3 downto 0);
	signal mipirx_RX_SKEW_CAL_HS: std_logic_vector(3 downto 0);
	signal mipirx_RX_SYNC_HS: std_logic_vector(3 downto 0);
	signal mipirx_RX_ULPS_ACTIVE_NOT: std_logic_vector(3 downto 0);
	signal mipirx_RX_ULPS_ESC: std_logic_vector(3 downto 0);
	signal mipirx_RX_VALID_HS_LAN0_sig: std_logic_vector(1 downto 0);
	signal mipirx_RX_VALID_HS_LAN1_sig: std_logic_vector(1 downto 0);
	signal mipirx_RX_VALID_HS_LAN2_sig: std_logic_vector(1 downto 0);
	signal mipirx_RX_VALID_HS_LAN3_sig: std_logic_vector(1 downto 0);
	signal mipirx_RX_ULPS_CLK_NOT_sig: std_logic_vector(0 downto 0);
	signal mipirx_RX_ULPS_ACTIVE_CLK_NOT_sig: std_logic_vector(0 downto 0);
	signal mipirx_STOPSTATE: std_logic_vector(3 downto 0);

	signal rowRawLast: natural range 0 to 2999;
	signal liveIxTExp: natural range 0 to ixTExpLast;

	signal liveSetRegAddr: std_logic_vector(15 downto 0);
	signal liveSetRegVal: std_logic_vector(7 downto 0);

	signal video_out_tlastm1: std_logic;

	-- IP sigs.live.cust --- INSERT

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv
	);
	signal stateOp: stateOp_t;

	signal ackInvConfig_sig: std_logic;
	signal hdrNotFix: std_logic;
	signal synthNotLive: std_logic;
	signal ackInvConfigSynth_sig: std_logic;
	signal tixVSynthmode: std_logic_vector(7 downto 0);
	signal TFramepad: std_logic_vector(15 downto 0);
	signal TLinepad: std_logic_vector(7 downto 0);
	signal tixVFormat: std_logic_vector(5 downto 0);

	-- IP sigs.op.cust --- INSERT

	---- forwarding of raw pixel data (rxfwd)

	signal pixel_datap1: std_logic_vector(63 downto 0);
	signal pixel_data_validp1: std_logic;
	signal datatypep1: std_logic_vector(5 downto 0);

	signal hsync_vc0n: std_logic;

	-- IP sigs.rxfwd.cust --- INSERT

	---- frame synthesis operation (synth)
	type stateSynth_t is (
		stateSynthInit,
		stateSynthRgb,
		stateSynthHdr,
		stateSynthChk,
		stateSynthEol,
		stateSynthEofA, stateSynthEofB
	);
	signal stateSynth: stateSynth_t;

	signal toVideoinAXIS_tvalid_sig: std_logic;
	signal toVideoinAXIS_tdata_sig: std_logic_vector(23 downto 0);
	signal toVideoinAXIS_tlast_sig: std_logic;

	signal vsync_sig: std_logic;
	signal ixTExp_sig: natural range 0 to ixTExpLast;

	signal row: unsigned(11 downto 0);
	signal col: unsigned(10 downto 0);

	-- IP sigs.synth.cust --- INSERT

	---- myI2c
	signal i2cRecv: std_logic_vector(15 downto 0);

	---- myMipirx
	signal pixel_per_clk: std_logic_vector(3 downto 0);

	signal pixel_data: std_logic_vector(63 downto 0);
	signal pixel_data_valid: std_logic;
	signal datatype: std_logic_vector(5 downto 0);

	signal word_count: std_logic_vector(15 downto 0);

	signal vsync_vc0: std_logic;
	signal hsync_vc0: std_logic;

	signal corecfgAXIL_rdata: std_logic_vector(31 downto 0);

	---- myParrom
	signal drdParrom: std_logic_vector(7 downto 0);

	---- myRawfwd
	signal video_out_x2_tvalid: std_logic;
	signal video_out_x2_tdata: std_logic_vector(63 downto 0);
	signal video_out_x2_tlast: std_logic;
	signal video_out_x2_tuser: std_logic_vector(5 downto 0);

	---- handshake
	-- config to myI2c
	signal reqI2c: std_logic;
	signal ackI2c: std_logic;
	signal dneI2c: std_logic;

	-- myMipirx to corecfg
	signal corecfgAXIL_arready: std_logic;
	signal corecfgAXIL_arvalid: std_logic;

	-- corecfg to myMipirx
	signal corecfgAXIL_rready: std_logic;
	signal corecfgAXIL_rvalid: std_logic;

	-- myMipirx to corecfg
	signal corecfgAXIL_awready: std_logic;
	signal corecfgAXIL_awvalid: std_logic;

	-- myMipirx to corecfg
	signal corecfgAXIL_wready: std_logic;
	signal corecfgAXIL_wvalid: std_logic;

	-- corecfg to myMipirx
	signal corecfgAXIL_bready: std_logic;
	signal corecfgAXIL_bvalid: std_logic;

	-- live to config
	signal reqLiveToConfigSetReg: std_logic;
	signal ackLiveToConfigSetReg: std_logic;

	---- other
	-- IP sigs.oth.cust --- IBEGIN

	------------------------------------------------------------------------
	-- functional description
	------------------------------------------------------------------------

	-- for simplicity (cross-platform and dphy clock required for Xilinx), target fMclk = 200 MHz

	-- IMX335 line rate 1188 Mbps x4 lanes @RAW12 allows for 396 Mpix/s
	-- 60 fps @ 2592x1944 corresponds to 302 Mpix/s (not a good indication for during-row rate because of h/v blanks)
	-- condensed gray or rgb format features 1296x972 pixels at quarter data date 

	-- for 1188 Mbps four-lane, Xilinx PG232 mandates pixclk > 148.5 MHz
	-- i.e. 200 MHz, 2 ppi should be fine for video_out_tdata

	-- with 200 MHz pixel clock, 12 MP = 4000x3000 -> 2000x1500 should be attainable at 66.67 fps
	-- however, 4ppi might be required and videoinToManyAXIS may have to keep tvalid high continuously

	-- IP sigs.oth.cust --- IEND

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myI2c : I2cmaster_v1_0
		generic map (
			fMclk => fMclk,
			clkFastNotStd => '0',
			clkFastplusNotFast => '0'
		)
		port map (
			reset => reset,
			mclk => mclk,

			req => reqI2c,
			ack => open,
			dne => dneI2c,

			devaddr => "00011010",
			r16Not8 => '1',
			d16Not8 => '0',
			readNotWrite => i2cReadNotWrite,
			readAradNotArd => '1',
			writeAdNotArd => '0',
			regaddr => i2cRegaddr,
			send => i2cSend,
			recv => i2cRecv,

			scl_in => scl_in,
			scl_out => scl_out,
			scl_tri => scl_tri,

			sda_in => sda_in,
			sda_out => sda_out,
			sda_tri => sda_tri
		);

	myMipirx : Csi2_hard_mipi_rx_efnx_w4
		port map (
			reset_n => resetnPixrxclk,
			reset_byte_HS_n => resetnBytehsclk,
			reset_pixel_n => resetn,
			axi_reset_n => resetn,
			clk => pixrxclk,
			clk_byte_HS => clk_byte_HS,
			clk_pixel => pixrxclk,
			axi_clk => mclk,

			RxClkEsc => mipirx_ESC_CLK,
			RxErrEsc => mipirx_ERR_ESC,
			RxErrControl => mipirx_ERR_CONTROL,
			RxErrSotSyncHS => mipirx_ERR_SOT_SYNC_HS,
			RxUlpsEsc => mipirx_RX_ULPS_ESC,
			RxUlpsActiveNot => mipirx_RX_ULPS_ACTIVE_NOT,
			RxSkewCalHS => mipirx_RX_SKEW_CAL_HS,
			RxStopState => mipirx_STOPSTATE,
			RxSyncHS => mipirx_RX_SYNC_HS,

			RxValidHS0 => mipirx_RX_VALID_HS_LAN0_sig,
			RxValidHS1 => mipirx_RX_VALID_HS_LAN1_sig,
			RxValidHS2 => mipirx_RX_VALID_HS_LAN2_sig,
			RxValidHS3 => mipirx_RX_VALID_HS_LAN3_sig,
			RxValidHS4 => (others => '0'),
			RxValidHS5 => (others => '0'),
			RxValidHS6 => (others => '0'),
			RxValidHS7 => (others => '0'),

			irq => open,
			pixel_per_clk => pixel_per_clk,
			pixel_data => pixel_data,
			pixel_data_valid => pixel_data_valid,
			datatype => datatype,
			shortpkt_data_field => open,
			word_count => word_count,
			vc => open,

			vsync_vc0 => vsync_vc0,
			vsync_vc1 => open,
			vsync_vc2 => open,
			vsync_vc3 => open,
			vsync_vc4 => open,
			vsync_vc5 => open,
			vsync_vc6 => open,
			vsync_vc7 => open,
			vsync_vc8 => open,
			vsync_vc9 => open,
			vsync_vc10 => open,
			vsync_vc11 => open,
			vsync_vc12 => open,
			vsync_vc13 => open,
			vsync_vc14 => open,
			vsync_vc15 => open,

			hsync_vc0 => hsync_vc0,
			hsync_vc1 => open,
			hsync_vc2 => open,
			hsync_vc3 => open,
			hsync_vc4 => open,
			hsync_vc5 => open,
			hsync_vc6 => open,
			hsync_vc7 => open,
			hsync_vc8 => open,
			hsync_vc9 => open,
			hsync_vc10 => open,
			hsync_vc11 => open,
			hsync_vc12 => open,
			hsync_vc13 => open,
			hsync_vc14 => open,
			hsync_vc15 => open,

			axi_araddr => corecfgAXIL_araddr,
			axi_arready => corecfgAXIL_arready,
			axi_arvalid => corecfgAXIL_arvalid,
			axi_rdata => corecfgAXIL_rdata,
			axi_rready => corecfgAXIL_rready,
			axi_rvalid => corecfgAXIL_rvalid,
			axi_awaddr => corecfgAXIL_awaddr,
			axi_awready => corecfgAXIL_awready,
			axi_awvalid => corecfgAXIL_awvalid,
			axi_wdata => corecfgAXIL_wdata,
			axi_wready => corecfgAXIL_wready,
			axi_wvalid => corecfgAXIL_wvalid,
			axi_bready => corecfgAXIL_bready,
			axi_bvalid => corecfgAXIL_bvalid,

			RxUlpsClkNot => mipirx_RX_ULPS_CLK_NOT_sig,
			RxUlpsActiveClkNot => mipirx_RX_ULPS_ACTIVE_CLK_NOT_sig,

			RxDataHS0 => RxDataHS0,
			RxDataHS1 => RxDataHS1,
			RxDataHS2 => RxDataHS2,
			RxDataHS3 => RxDataHS3,
			RxDataHS4 => (others => '0'),
			RxDataHS5 => (others => '0'),
			RxDataHS6 => (others => '0'),
			RxDataHS7 => (others => '0')
		);

	myParrom : Spram_v1_0_size2kB_w8
		port map (
			reset => reset,
			clk => mclk,

			en => enParrom,
			we => '0',

			a => aParrom_vec,
			drd => drdParrom,
			dwr => (others => '0')
		);

	myRawfwd : Sprsaxisfwd_v1_0
		generic map (
			wSize => 12,
			wIxHshk => 4,
			wIxData => 4,
			wData => 64,
			wUser => 6
		)
		port map (
			resetIgrclk => reset, -- in mclk domain
			igrclk => pixrxclk,

			reset => reset,
			mclk => mclk,

			igrAXIS_tready => open, -- always 1
			igrAXIS_tvalid => pixel_data_validp1,
			igrAXIS_tdata => pixel_datap1,
			igrAXIS_tkeep => (others => '1'),
			igrAXIS_tlast => hsync_vc0n,
			igrAXIS_tuser => datatypep1,

			enEgr => enEgr,

			egrAXIS_tready => '1',
			egrAXIS_tvalid => video_out_x2_tvalid,
			egrAXIS_tdata => video_out_x2_tdata,
			egrAXIS_tkeep => open,
			egrAXIS_tlast => video_out_x2_tlast,
			egrAXIS_tuser => video_out_x2_tuser
		);

	------------------------------------------------------------------------
	-- implementation: bytehsclk wiring and reset (bytehsclk)
	------------------------------------------------------------------------

	-- IP impl.bytehsclk.wiring --- BEGIN
	-- IP impl.bytehsclk.wiring --- END

	-- IP impl.bytehsclk.wiring.cust --- LINE

	-- IP impl.bytehsclk.rising --- BEGIN
	process (reset, clk_byte_HS)
		-- IP impl.bytehsclk.vars --- RBEGIN
		constant fBytehsclk: natural := 148500; -- at 1188 Mbps, expect 148.5 MHz
		constant imax: natural := (16*fBytehsclk)/fMclk+1;
		variable i: natural range 0 to imax;
		-- IP impl.bytehsclk.vars --- REND

	begin
		if reset='1' then
			-- IP impl.bytehsclk.asyncrst --- BEGIN
			stateBytehsclk <= stateBytehsclkReset;
			resetnBytehsclk <= '0';
			reset_bytehsclk <= '1';
			reset_to_bytehsclkm1 <= '1';
			reset_to_bytehsclkm2 <= '1';

			-- IP impl.bytehsclk.asyncrst --- END
			-- IP impl.bytehsclk.asyncrst.cust --- IBEGIN
			i := 0;
			-- IP impl.bytehsclk.asyncrst.cust --- IEND

		elsif rising_edge(clk_byte_HS) then
		-- IP impl.bytehsclk.pre --- IBEGIN
			if reset_to_bytehsclkm1=reset_to_bytehsclkm2 then
				reset_bytehsclk <= reset_to_bytehsclkm2;
			end if;
			reset_to_bytehsclkm1 <= reset;
			reset_to_bytehsclkm2 <= reset_to_bytehsclkm1;
		-- IP impl.bytehsclk.pre --- IEND

			if stateBytehsclk=stateBytehsclkReset then
				-- IP impl.bytehsclk.syncrst --- RBEGIN

				-- IP impl.bytehsclk.syncrst --- REND
				-- IP impl.bytehsclk.syncrst.cust --- INSERT

				if i=imax then
					if reset_bytehsclk='0' then
						resetnBytehsclk <= '1'; -- IP impl.bytehsclk.reset.done --- ILINE

						stateBytehsclk <= stateBytehsclkRun;

					else
						stateBytehsclk <= stateBytehsclkReset;
					end if;

				else
					i := i + 1; -- IP impl.bytehsclk.reset.inc --- ILINE

					stateBytehsclk <= stateBytehsclkReset;
				end if;

			elsif stateBytehsclk=stateBytehsclkRun then
				if reset_bytehsclk='1' then
					resetnBytehsclk <= '0'; -- IP impl.bytehsclk.run --- ILINE

					stateBytehsclk <= stateBytehsclkReset;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.bytehsclk.rising --- END

	------------------------------------------------------------------------
	-- implementation: I2C configuration (config)
	------------------------------------------------------------------------

	-- IP impl.config.wiring --- RBEGIN
	ackInvSetReg <= ackInvSetReg_sig;

	ackInvGetReg <= ackInvGetReg_sig;
	getRegVal <= regVal;

	ackInvModReg <= ackInvModReg_sig;

	enParrom <= '1' when stateConfig=stateConfigLoadA else '0';
	
	aParrom_vec <= std_logic_vector(to_unsigned(aParrom, 11));

	reqI2c <= '1' when stateConfig=stateConfigXfer else '0';
	-- IP impl.config.wiring --- REND

	-- IP impl.config.wiring.cust --- LINE

	stateConfig_dbg <= x"00" when stateConfig=stateConfigInit
				else x"10" when stateConfig=stateConfigPrepA
				else x"11" when stateConfig=stateConfigPrepB
				else x"12" when stateConfig=stateConfigPrepC
				else x"13" when stateConfig=stateConfigPrepD
				else x"20" when stateConfig=stateConfigLoadA
				else x"21" when stateConfig=stateConfigLoadB
				else x"30" when stateConfig=stateConfigXfer
				else x"40" when stateConfig=stateConfigStep
				else x"50" when stateConfig=stateConfigPwupdnA
				else x"51" when stateConfig=stateConfigPwupdnB
				else x"60" when stateConfig=stateConfigInv
				else (others => '1');

	-- IP impl.config.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.config.vars --- RBEGIN
		constant a0ParromGnr: natural := 0; -- IMX219 (or IMX227?)
		constant a0ParromSpec: natural := 512;

		constant a0ParromGnr2: natural := 1024; -- IMX335
		constant a0ParromSpec2: natural := 1536;

		variable prepdone: boolean;

		variable specNotGnr: boolean; -- during preparation: general vs. resolution-specific (leftover from OV5640)

		variable modNotGetSet: boolean;
		variable liveNotExt: boolean;

		variable bytecnt: natural range 0 to 4;

		constant imax: natural := 10; -- 1ms power up to reset high
		variable i: natural range 0 to imax;
		
		constant jmax: natural := 200; -- 20ms reset high to parrom initialization
		variable j: natural range 0 to jmax;
		
		constant kmax: natural := 2; -- parrom load
		variable k: natural range 0 to kmax;
		-- IP impl.config.vars --- REND

	begin
		if reset='1' then
			-- IP impl.config.asyncrst --- RBEGIN
			stateConfig <= stateConfigInit;

			ackInvSetReg_sig <= '0';
			ackInvGetReg_sig <= '0';
			regVal <= (others => '0');
			ackInvModReg_sig <= '0';

			i2cReadNotWrite <= '0';
			i2cRegaddr <= (others => '0');
			i2cSend <= (others => '0');

			aParrom <= 0;

			ackLiveToConfigSetReg <= '0';

			prepdone := false;
			-- IP impl.config.asyncrst --- REND
			-- IP impl.config.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if stateConfig=stateConfigInit then
				-- IP impl.config.syncrst --- RBEGIN
				ackInvSetReg_sig <= '0';
				ackInvGetReg_sig <= '0';
				regVal <= (others => '0');
				ackInvModReg_sig <= '0';

				aParrom <= 0;
				-- IP impl.config.syncrst --- REND
				-- IP impl.config.syncrst.cust --- INSERT

				if not prepdone then
					-- IP impl.config.init.prep --- IBEGIN
					i := 0;
					-- IP impl.config.init.prep --- IEND

					stateConfig <= stateConfigPrepB;

				elsif reqInvSetReg='1' then
					-- IP impl.config.init.invSetReg --- IBEGIN
					modNotGetSet := false;
					liveNotExt := false;
					
					i2cReadNotWrite <= '0';
					i2cRegaddr <= setRegAddr;
					i2cSend <= x"00" & setRegVal;
					-- IP impl.config.init.invSetReg --- IEND

					stateConfig <= stateConfigXfer;

				elsif reqInvGetReg='1' then
					-- IP impl.config.init.invGetReg --- IBEGIN
					modNotGetSet := false;
					liveNotExt := false;

					i2cReadNotWrite <= '1';
					i2cRegaddr <= getRegAddr;
					-- IP impl.config.init.invGetReg --- IEND

					stateConfig <= stateConfigXfer;

				elsif reqInvModReg='1' then
					-- IP impl.config.init.invModReg --- IBEGIN
					modNotGetSet := true;
					liveNotExt := false;

					i2cReadNotWrite <= '1';
					i2cRegaddr <= modRegAddr;
					-- IP impl.config.init.invModReg --- IEND

					stateConfig <= stateConfigXfer;

				elsif reqLiveToConfigSetReg='1' then
					-- IP impl.config.init.liveSetReg --- IBEGIN
					modNotGetSet := false;
					liveNotExt := true;
					
					i2cReadNotWrite <= '0';
					i2cRegaddr <= liveSetRegAddr;
					i2cSend <= x"00" & liveSetRegVal;
					-- IP impl.config.init.liveSetReg --- IEND

					stateConfig <= stateConfigXfer;
				end if;

			elsif stateConfig=stateConfigPrepA then
				if tkclk='1' then
					if i=imax then
						-- IP impl.config.prepA.done --- IBEGIN
						j := 0;
						-- IP impl.config.prepA.done --- IEND

						stateConfig <= stateConfigPrepD;

					else
						stateConfig <= stateConfigPrepB;
					end if;
				end if;

			elsif stateConfig=stateConfigPrepB then
				if tkclk='0' then
					i := i + 1; -- IP impl.config.prepB.inc --- ILINE

					stateConfig <= stateConfigPrepA;
				end if;

			elsif stateConfig=stateConfigPrepC then
				if tkclk='1' then
					if j=jmax then
						-- IP impl.config.prepC.done --- IBEGIN
						specNotGnr := false;
	
						i2cReadNotWrite <= '0';
	
						-- modification so camera is turned on with delay (no actual spec section for IMX335)
						--aParrom <= a0ParromGnr;
						aParrom <= a0ParromGnr2;
	
						bytecnt := 0;
						
						k := 0;
						-- IP impl.config.prepC.done --- IEND

						stateConfig <= stateConfigLoadA;

					else
						stateConfig <= stateConfigPrepD;
					end if;
				end if;

			elsif stateConfig=stateConfigPrepD then
				if tkclk='0' then
					j := j + 1; -- IP impl.config.prepD.inc --- ILINE

					stateConfig <= stateConfigPrepC;
				end if;

			elsif stateConfig=stateConfigLoadA then
				k := k + 1; -- IP impl.config.loadA.pre --- ILINE

				if k=kmax then
					stateConfig <= stateConfigLoadB;
				end if;

			elsif stateConfig=stateConfigLoadB then
				-- IP impl.config.loadB.pre --- IBEGIN
				bytecnt := bytecnt + 1;

				if bytecnt=4 then
					bytecnt := 0;
				end if;
				-- IP impl.config.loadB.pre --- IEND

				if (bytecnt=1 and drdParrom=x"00") then
					if not specNotGnr then
						-- IP impl.config.loadB.prepSpec --- IBEGIN
						--aParrom <= a0ParromSpec;
						aParrom <= a0ParromSpec2;
						
						specNotGnr := true;

						bytecnt := 0;
						
						k := 0;

						-- modification: use pwupdn to wait
						j := 0;

						--stateConfig <= stateConfigLoadA;
						-- IP impl.config.loadB.prepSpec --- IEND

						stateConfig <= stateConfigPwupdnB;

					else
						prepdone := true; -- IP impl.config.loadB.done --- ILINE

						stateConfig <= stateConfigInit;
					end if;

				else
					aParrom <= aParrom + 1; -- IP impl.config.loadB.inc --- ILINE

					if bytecnt=0 then
						stateConfig <= stateConfigXfer;

					elsif bytecnt=1 then
						-- IP impl.config.loadB.addrmsb --- IBEGIN
						i2cRegaddr(15 downto 8) <= drdParrom;

						k := 0;
						-- IP impl.config.loadB.addrmsb --- IEND

						stateConfig <= stateConfigLoadA;

					elsif bytecnt=2 then
						-- IP impl.config.loadB.addrlsb --- IBEGIN
						i2cRegaddr(7 downto 0) <= drdParrom;

						k := 0;
						-- IP impl.config.loadB.addrlsb --- IEND

						stateConfig <= stateConfigLoadA;

					elsif bytecnt=3 then
						-- IP impl.config.loadB.val --- IBEGIN
						i2cSend <= x"00" & drdParrom;

						k := 0;
						-- IP impl.config.loadB.val --- IEND

						stateConfig <= stateConfigLoadA;
					end if;
				end if;

			elsif stateConfig=stateConfigXfer then
				if dneI2c='1' then
					stateConfig <= stateConfigStep;
				end if;

			elsif stateConfig=stateConfigStep then
				if i2cReadNotWrite='0' then
					if not prepdone then
						-- IP impl.config.step.prep --- IBEGIN
						bytecnt := 0;

						k := 0;
						-- IP impl.config.step.prep --- IEND

						stateConfig <= stateConfigLoadA;

					else
						-- IP impl.config.step.cmdDone --- IBEGIN
						if not modNotGetSet then
							if not liveNotExt then
								ackInvSetReg_sig <= '1';
							else
								ackLiveToConfigSetReg <= '1';
							end if;
						else
							ackInvModReg_sig <= '1';
						end if;
						-- IP impl.config.step.cmdDone --- IEND

						stateConfig <= stateConfigInv;
					end if;

				else
					if not modNotGetSet then
						-- IP impl.config.step.get --- IBEGIN
						regVal <= i2cRecv(7 downto 0);

						ackInvGetReg_sig <= '1';
						-- IP impl.config.step.get --- IEND

						stateConfig <= stateConfigInv;

					else
						-- IP impl.config.step.mod --- IBEGIN
						i2cReadNotWrite <= '0';
						i2cSend <= x"00" & ((i2cRecv(7 downto 0) and (not modRegMask)) or (modRegVal and modRegMask));
						-- IP impl.config.step.mod --- IEND

						stateConfig <= stateConfigXfer;
					end if;
				end if;

			elsif stateConfig=stateConfigPwupdnA then
				if tkclk='1' then
					if j=jmax then
						stateConfig <= stateConfigLoadA;

					else
						stateConfig <= stateConfigPwupdnB;
					end if;
				end if;

			elsif stateConfig=stateConfigPwupdnB then
				if tkclk='0' then
					j := j + 1; -- IP impl.config.pwupdnB.inc --- ILINE

					stateConfig <= stateConfigPwupdnA;
				end if;

			elsif stateConfig=stateConfigInv then
				if ((reqInvSetReg='0' and ackInvSetReg_sig='1') or (reqInvGetReg='0' and ackInvGetReg_sig='1') or (reqInvModReg='0' and ackInvModReg_sig='1') or (reqLiveToConfigSetReg='0' and ackLiveToConfigSetReg='1')) then
					-- IP impl.config.inv.reset --- IBEGIN
					ackInvSetReg_sig <= '0';
					ackInvGetReg_sig <= '0';
					ackInvModReg_sig <= '0';
					ackLiveToConfigSetReg <= '0';
					-- IP impl.config.inv.reset --- IEND

					stateConfig <= stateConfigInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.config.rising --- END

	------------------------------------------------------------------------
	-- implementation: MIPI RX core configuration (corecfg)
	------------------------------------------------------------------------

	-- IP impl.corecfg.wiring --- BEGIN
	ackInvGetCorereg <= ackInvGetCorereg_sig;
	getCoreregVal <= getCoreregVal_sig;
	ackInvSetCorereg <= ackInvSetCorereg_sig;

	corecfgAXIL_arvalid <= '1' when stateCorecfg=stateCorecfgReadA else '0';

	corecfgAXIL_rready <= '1' when (stateCorecfg=stateCorecfgReadA or stateCorecfg=stateCorecfgReadB) else '0';

	corecfgAXIL_awvalid <= '1' when stateCorecfg=stateCorecfgWriteA else '0';

	corecfgAXIL_wvalid <= '1' when (stateCorecfg=stateCorecfgWriteA or stateCorecfg=stateCorecfgWriteB) else '0';

	corecfgAXIL_bready <= '1' when stateCorecfg=stateCorecfgWriteC else '0';
	-- IP impl.corecfg.wiring --- END

	-- IP impl.corecfg.wiring.cust --- LINE

	-- IP impl.corecfg.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.corecfg.vars --- BEGIN
		-- IP impl.corecfg.vars --- END

	begin
		if reset='1' then
			-- IP impl.corecfg.asyncrst --- BEGIN
			stateCorecfg <= stateCorecfgInit;
			ackInvGetCorereg_sig <= '0';
			getCoreregVal_sig <= (others => '0');
			ackInvSetCorereg_sig <= '0';
			corecfgAXIL_araddr <= (others => '0');
			corecfgAXIL_awaddr <= (others => '0');
			corecfgAXIL_wdata <= (others => '0');

			-- IP impl.corecfg.asyncrst --- END
			-- IP impl.corecfg.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if stateCorecfg=stateCorecfgInit then
				if reqInvGetCorereg='1' then
					-- IP impl.corecfg.init.invGetCorereg --- IBEGIN
					corecfgAXIL_araddr <= getCoreregAddr(5 downto 0);
					-- IP impl.corecfg.init.invGetCorereg --- IEND

					stateCorecfg <= stateCorecfgReadA;

				elsif reqInvSetCorereg='1' then
					-- IP impl.corecfg.init.invSetCorereg --- IBEGIN
					corecfgAXIL_awaddr <= setCoreregAddr(5 downto 0);
					corecfgAXIL_wdata <= setCoreregVal;
					-- IP impl.corecfg.init.invSetCorereg --- IEND

					stateCorecfg <= stateCorecfgWriteA;

				else
					-- IP impl.corecfg.syncrst --- RBEGIN
					ackInvGetCorereg_sig <= '0';
					ackInvSetCorereg_sig <= '0';
					corecfgAXIL_araddr <= (others => '0');
					corecfgAXIL_awaddr <= (others => '0');
					corecfgAXIL_wdata <= (others => '0');

					-- IP impl.corecfg.syncrst --- REND
					-- IP impl.corecfg.syncrst.cust --- INSERT

					stateCorecfg <= stateCorecfgInit;
				end if;

			elsif stateCorecfg=stateCorecfgReadA then
				if corecfgAXIL_arready='1' then
					if corecfgAXIL_rvalid='1' then
						getCoreregVal_sig <= corecfgAXIL_rdata; -- IP impl.corecfg.readA.copy --- ILINE

						stateCorecfg <= stateCorecfgReadC;

					else
						stateCorecfg <= stateCorecfgReadB;
					end if;
				end if;

			elsif stateCorecfg=stateCorecfgReadB then
				if corecfgAXIL_rvalid='1' then
					getCoreregVal_sig <= corecfgAXIL_rdata; -- IP impl.corecfg.readB.copy --- ILINE

					stateCorecfg <= stateCorecfgReadC;
				end if;

			elsif stateCorecfg=stateCorecfgReadC then
				ackInvGetCorereg_sig <= '1'; -- IP impl.corecfg.readC --- ILINE

				stateCorecfg <= stateCorecfgInv;

			elsif stateCorecfg=stateCorecfgWriteA then
				if corecfgAXIL_awready='1' then
					if corecfgAXIL_wready='1' then
						stateCorecfg <= stateCorecfgWriteC;

					else
						stateCorecfg <= stateCorecfgWriteB;
					end if;
				end if;

			elsif stateCorecfg=stateCorecfgWriteB then
				if corecfgAXIL_wready='1' then
					stateCorecfg <= stateCorecfgWriteC;
				end if;

			elsif stateCorecfg=stateCorecfgWriteC then
				if corecfgAXIL_bvalid='1' then
					ackInvSetCorereg_sig <= '1'; -- IP impl.corecfg.writeC --- ILINE

					stateCorecfg <= stateCorecfgInv;
				end if;

			elsif stateCorecfg=stateCorecfgInv then
				if ((reqInvGetCorereg='0' and ackInvGetCorereg_sig='1') or (reqInvSetCorereg='0' and ackInvSetCorereg_sig='1')) then
					-- IP impl.corecfg.inv.reset --- IBEGIN
					ackInvGetCorereg_sig <= '0';
					ackInvSetCorereg_sig <= '0';
					-- IP impl.corecfg.inv.reset --- IEND

					stateCorecfg <= stateCorecfgInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.corecfg.rising --- END

	------------------------------------------------------------------------
	-- implementation: gearing from quad-RAW12 to dual-RAW12 (gear)
	------------------------------------------------------------------------

	-- IP impl.gear.wiring --- BEGIN
	-- IP impl.gear.wiring --- END

	-- IP impl.gear.wiring.cust --- LINE

	-- IP impl.gear.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.gear.vars --- RBEGIN
		variable video_out_tdata_next: std_logic_vector(23 downto 0);
		-- IP impl.gear.vars --- REND

	begin
		if reset='1' then
			-- IP impl.gear.asyncrst --- BEGIN
			enEgr <= '0';
			pixrxclk_mclk <= (others => '0');
			video_out_tvalid <= '0';
			video_out_tdata <= (others => '0');
			video_out_tlast <= '1';
			video_out_tuser <= (others => '0');

			-- IP impl.gear.asyncrst --- END
			-- IP impl.gear.asyncrst.cust --- IBEGIN
			video_out_tdata_next := (others => '0');
			-- IP impl.gear.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			-- IP impl.gear --- IBEGIN
			enEgr <= not enEgr;

			if enEgr='1' then
				video_out_tvalid <= video_out_x2_tvalid;
				video_out_tdata_next := video_out_x2_tdata(24+23 downto 24+0); -- by design, video_out_x2_tdata should not change when sampled next
				video_out_tdata <= video_out_x2_tdata(23 downto 0);
				if video_out_x2_tlast='0' then
					video_out_tlast <= '0';
				end if;
				video_out_tuser <= video_out_x2_tuser;
			else
				video_out_tdata <= video_out_tdata_next;
				if video_out_x2_tlast='1' then
					video_out_tlast <= '1';
				end if;
			end if;
			-- IP impl.gear --- IEND
		end if;
	end process;
	-- IP impl.gear.rising --- END

	------------------------------------------------------------------------
	-- implementation: live streaming operation (live)
	------------------------------------------------------------------------

	-- IP impl.live.wiring --- RBEGIN

	-- liveIxTExp 0 | 1 | 2 | 3 | 4 |
	-- ixTExp_lcl   2   3   4   0   1

	resetn <= not reset;
	resetnPixrxclk <= not resetPixrxclk;

	vsync <= vsync_sig when synthNotLive='1'
				else '0' when stateLive=stateLivePre or stateLive=stateLiveRun else '1';

	ixTExp <= std_logic_vector(to_unsigned(ixTExp_sig, 4)) when synthNotLive='1'
				else std_logic_vector(to_unsigned(liveIxTExp, 4));

	toVideoinAXIS_tvalid <= toVideoinAXIS_tvalid_sig when synthNotLive='1'
				else '1' when stateLive=stateLiveRun and video_out_tvalid='1' and video_out_tuser=tixVFormat else '0';
	toVideoinAXIS_tdata <= toVideoinAXIS_tdata_sig when synthNotLive='1'
				else video_out_tdata;
	toVideoinAXIS_tlast <= toVideoinAXIS_tlast_sig when synthNotLive='1'
				else '0' when stateLive=stateLiveRun and video_out_tlast='0' else '1';

	rowRawLast <= to_integer(unsigned(NRowRaw) - 1);

	reqLiveToConfigSetReg <= '1' when stateLive=stateLiveUpdTExpB else '0';
	-- IP impl.live.wiring --- REND

	-- IP impl.live.wiring.cust --- LINE

	-- IP impl.live.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.live.vars --- RBEGIN
		variable rowRaw_lcl: natural range 0 to 2999;

		variable ixTExp_lcl: natural range 0 to ixTExpLast;
		variable i: natural range 0 to 1;
		-- IP impl.live.vars --- REND

	begin
		if reset='1' then
			-- IP impl.live.asyncrst --- BEGIN
			stateLive <= stateLiveInit;
			liveIxTExp <= 0;
			liveSetRegAddr <= (others => '0');
			liveSetRegVal <= (others => '0');
			video_out_tlastm1 <= '1';

			-- IP impl.live.asyncrst --- END
			-- IP impl.live.asyncrst.cust --- IBEGIN
			rowRaw_lcl := 0;

			ixTExp_lcl := 1;
			i := 0;
			-- IP impl.live.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			video_out_tlastm1 <= video_out_tlast; -- IP impl.live.pre --- ILINE

			if stateLive=stateLiveInit then
				-- IP impl.live.syncrst --- RBEGIN
				liveSetRegAddr <= (others => '0');
				liveSetRegVal <= (others => '0');
				-- IP impl.live.syncrst --- REND
				-- IP impl.live.syncrst.cust --- IBEGIN
				rowRaw_lcl := 0;

				i := 0;
				-- IP impl.live.syncrst.cust --- IEND

				if (video_out_tvalid='1' and video_out_tuser/=tixVFormat) then
					stateLive <= stateLivePre;

				else
					stateLive <= stateLiveInit;
				end if;

			elsif stateLive=stateLivePre then
				if (video_out_tlastm1='0' and video_out_tlast='1') then
					if rowRaw_lcl=rowRawStart then
						rowRaw_lcl := 0; -- IP impl.live.pre.done --- ILINE

						stateLive <= stateLiveRun;

					else
						rowRaw_lcl := rowRaw_lcl + 1; -- IP impl.live.pre.nextRow --- ILINE

						stateLive <= stateLivePre;
					end if;
				end if;

			elsif stateLive=stateLiveRun then
				if (video_out_tlastm1='0' and video_out_tlast='1') then
					if rowRaw_lcl=rowRawLast then
						rowRaw_lcl := 0; -- IP impl.live.run.TExpDone --- ILINE

						if hdrNotFix='0' then
							stateLive <= stateLiveInit;

						else
							-- IP impl.live.run.nextTExp --- IBEGIN
							if ixTExp_lcl=ixTExpLast then
								ixTExp_lcl := 0;
							else
								ixTExp_lcl := ixTExp_lcl + 1;
							end if;

							i := 0;
							-- IP impl.live.run.nextTExp --- IEND

							stateLive <= stateLiveUpdTExpA;
						end if;

					else
						rowRaw_lcl := rowRaw_lcl + 1; -- IP impl.live.run.nextRow --- ILINE

						stateLive <= stateLiveRun;
					end if;
				end if;

			elsif stateLive=stateLiveUpdTExpA then
				-- IP impl.live.updTExpA --- IBEGIN
				if i=0 then
					liveSetRegAddr <= regShr0_0;
				else
					liveSetRegAddr <= regShr0_1;
				end if;

				case ixTExp_lcl is
					when 0 =>
						liveSetRegVal <= TExp0(i*8+7 downto i*8);
					when 1 =>						
						liveSetRegVal <= TExp1(i*8+7 downto i*8);
					when 2 =>						
						liveSetRegVal <= TExp2(i*8+7 downto i*8);
					when 3 =>						
						liveSetRegVal <= TExp3(i*8+7 downto i*8);
					when 4 =>						
						liveSetRegVal <= TExp4(i*8+7 downto i*8);
					when others =>						
				end case;
				-- IP impl.live.updTExpA --- IEND

				stateLive <= stateLiveUpdTExpB;

			elsif stateLive=stateLiveUpdTExpB then
				if ackLiveToConfigSetReg='1' then
					if i=1 then
						-- IP impl.live.updTExpB.done --- IBEGIN
						if ixTExp_lcl=0 then
							liveIxTExp <= ixTExpLast;
						else
							liveIxTexp <= ixTExp_lcl - 1;
						end if;
						-- IP impl.live.updTExpB.done --- IEND

						stateLive <= stateLiveInit;

					else
						i := i + 1; -- IP impl.live.updTExpB.nextWord --- ILINE

						stateLive <= stateLiveUpdTExpA;
					end if;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.live.rising --- END

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	ackInvConfig <= ackInvConfig_sig;
	ackInvConfigSynth <= ackInvConfigSynth_sig;
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- LINE

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- BEGIN
		-- IP impl.op.vars --- END

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- BEGIN
			stateOp <= stateOpInit;
			ackInvConfig_sig <= '0';
			hdrNotFix <= '0';
			synthNotLive <= '0';
			ackInvConfigSynth_sig <= '0';
			tixVSynthmode <= (others => '0');
			TFramepad <= (others => '0');
			TLinepad <= (others => '0');
			tixVFormat <= tixVFormatRaw12(5 downto 0);

			-- IP impl.op.asyncrst --- END
			-- IP impl.op.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateOp=stateOpInit or (stateOp/=stateOpInv and (reqInvConfig='1' or reqInvConfigSynth='1'))) then
				if reqInvConfig='1' then
					-- IP impl.op.init.invConfig --- IBEGIN
					if configHdrNotFix=tru8 then
						hdrNotFix <= '1';
					else
						hdrNotFix <= '0';
					end if;
					if configSynthNotLive=tru8 then
						synthNotLive <= '1';
					else
						synthNotLive <= '0';
					end if;

					ackInvConfig_sig <= '1';
					ackInvConfigSynth_sig <= '0';
					-- IP impl.op.init.invConfig --- IEND

					stateOp <= stateOpInv;

				elsif reqInvConfigSynth='1' then
					-- IP impl.op.init.invConfigSynth --- IBEGIN
					tixVSynthmode <= configSynthTixVSynthmode;
					TFramepad <= configSynthTFramepad;
					TLinepad <= configSynthTLinepad;

					ackInvConfig_sig <= '0';
					ackInvConfigSynth_sig <= '1';
					-- IP impl.op.init.invConfigSynth --- IEND

					stateOp <= stateOpInv;

				else
					-- IP impl.op.syncrst --- RBEGIN
					ackInvConfig_sig <= '0';
					ackInvConfigSynth_sig <= '0';
					tixVFormat <= tixVFormatRaw12(5 downto 0);

					-- IP impl.op.syncrst --- REND
					-- IP impl.op.syncrst.cust --- INSERT

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpInv then
				if ((reqInvConfig='0' and ackInvConfig_sig='1') or (reqInvConfigSynth='0' and ackInvConfigSynth_sig='1')) then
					-- IP impl.op.inv.reset --- IBEGIN
					ackInvConfig_sig <= '0';
					ackInvConfigSynth_sig <= '0';
					-- IP impl.op.inv.reset --- IEND

					stateOp <= stateOpInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: forwarding of raw pixel data (rxfwd)
	------------------------------------------------------------------------

	-- IP impl.rxfwd.wiring --- BEGIN
	hsync_vc0n <= not hsync_vc0;
	-- IP impl.rxfwd.wiring --- END

	-- IP impl.rxfwd.wiring.cust --- LINE

	-- IP impl.rxfwd.rising --- BEGIN
	process (resetPixrxclk, pixrxclk)
		-- IP impl.rxfwd.vars --- BEGIN
		-- IP impl.rxfwd.vars --- END

	begin
		if resetPixrxclk='1' then
			-- IP impl.rxfwd.asyncrst --- BEGIN
			pixel_datap1 <= (others => '0');
			pixel_data_validp1 <= '0';
			datatypep1 <= (others => '0');

			-- IP impl.rxfwd.asyncrst --- END
			-- IP impl.rxfwd.asyncrst.cust --- INSERT

		elsif rising_edge(pixrxclk) then
			-- IP impl.rxfwd --- IBEGIN
			pixel_data_validp1 <= pixel_data_valid;
			pixel_datap1 <= pixel_data;
			datatypep1 <= datatype;
			-- IP impl.rxfwd --- IEND
		end if;
	end process;
	-- IP impl.rxfwd.rising --- END

	------------------------------------------------------------------------
	-- implementation: frame synthesis operation (synth)
	------------------------------------------------------------------------

	-- IP impl.synth.wiring --- BEGIN
	toVideoinAXIS_tlast_sig <= '0' when (stateSynth=stateSynthRgb or stateSynth=stateSynthHdr or stateSynth=stateSynthChk) else '1';

	vsync_sig <= '0' when (stateSynth=stateSynthRgb or stateSynth=stateSynthHdr or stateSynth=stateSynthChk
				 or stateSynth=stateSynthEol or stateSynth=stateSynthEofA) else '1';
	-- IP impl.synth.wiring --- END

	-- IP impl.synth.wiring.cust --- LINE

	-- IP impl.synth.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.synth.vars --- RBEGIN
		variable i: natural range 0 to 255; -- linepad counter
		variable j: natural range 0 to 65535; -- framepad counter

		variable r_lcl, g0_lcl, g1_lcl, b_lcl: natural range 0 to 4095;
		variable rsh, gsh, bsh: natural range 0 to 2;

		variable w0, w1: std_logic_vector(23 downto 0);

		-- chk related
		constant NSqr: natural := 10;
		variable rowchk: natural range 0 to NSqr-1;
		variable colchk: natural range 0 to NSqr-1;
		variable whtNotBlk0: boolean;
		variable whtNotBlk: boolean;
		variable blk: unsigned(11 downto 0);
		variable wht: unsigned(11 downto 0);
		-- IP impl.synth.vars --- REND

	begin
		if reset='1' then
			-- IP impl.synth.asyncrst --- RBEGIN
			stateSynth <= stateSynthInit;

			toVideoinAXIS_tvalid_sig <= '0';
			toVideoinAXIS_tdata_sig <= (others => '0');

			ixTExp_sig <= 0;

			row <= (others => '0');
			col <= (others => '0');

			r_lcl := 0;
			g0_lcl := 0;
			g1_lcl := 0;
			b_lcl := 0;

			rsh := 0;
			gsh := 0;
			bsh := 0;

			w0 := (others => '0');
			w1 := (others => '0');

			rowchk := 0;
			colchk := 0;
			whtNotBlk0 := false;
			whtNotBlk := false;
			blk := (others => '0');
			wht := (others => '0');
			-- IP impl.synth.asyncrst --- REND
			-- IP impl.synth.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateSynth=stateSynthInit or rng='0') then
				-- IP impl.synth.syncrst --- RBEGIN
				toVideoinAXIS_tvalid_sig <= '0';
				toVideoinAXIS_tdata_sig <= (others => '0');

				ixTExp_sig <= 0;

				row <= (others => '0');
				col <= (others => '0');
				-- IP impl.synth.syncrst --- REND
				-- IP impl.synth.syncrst.cust --- INSERT

				if rng='0' then
					stateSynth <= stateSynthInit;

				else
					if tixVSynthmode=tixVSynthmodeRgb then
						-- IP impl.synth.init.startRgb --- IBEGIN
						r_lcl := 0;
						g0_lcl := 2048;
						g1_lcl := 2048;
						b_lcl := 4095;
						-- IP impl.synth.init.startRgb --- IEND

						stateSynth <= stateSynthRgb;

					elsif tixVSynthmode=tixVSynthmodeHdr then
						-- IP impl.synth.init.startHdr --- IBEGIN
						r_lcl := 0;
						g0_lcl := 2048;
						g1_lcl := 2048;
						b_lcl := 4095;
			
						rsh := 0;
						gsh := 1;
						bsh := 2;
						-- IP impl.synth.init.startHdr --- IEND

						stateSynth <= stateSynthHdr;

					elsif tixVSynthmode=tixVSynthmodeChk then
						-- IP impl.synth.init.startChk --- IBEGIN
						whtNotBlk0 := false;
						whtNotBlk := false;
						rowchk := 0;
						colchk := 0;
						blk := (others => '0');
						wht := (others => '1');
						-- IP impl.synth.init.startChk --- IEND

						stateSynth <= stateSynthChk;
					end if;
				end if;

			elsif stateSynth=stateSynthRgb then
				-- IP impl.synth.rgb.pre --- IBEGIN
				-- pattern I: non HDR rgb ramp, r0..4095, g2048..2047, b4095..0
				toVideoinAXIS_tvalid_sig <= '1';

				if row(0)='0' then
					toVideoinAXIS_tdata_sig <= std_logic_vector(to_unsigned(r_lcl, 12)) & std_logic_vector(to_unsigned(g0_lcl, 12));
				else
					toVideoinAXIS_tdata_sig <= std_logic_vector(to_unsigned(g1_lcl, 12)) & std_logic_vector(to_unsigned(b_lcl, 12));
				end if;
				-- IP impl.synth.rgb.pre --- IEND

				if col=unsigned(NCol)-1 then
					i := 0; -- IP impl.synth.rgb.rowDone --- ILINE

					stateSynth <= stateSynthEol;

				else
					-- IP impl.synth.rgb.nextCol --- IBEGIN
					col <= col + 1;

					if row(0)='0' then
						if r_lcl=4095 then
							r_lcl := 0;
						else
							r_lcl := r_lcl + 1;
						end if;
						if g0_lcl=4095 then
							g0_lcl := 0;
						else
							g0_lcl := g0_lcl + 1;
						end if;
					else
						if b_lcl=0 then
							b_lcl := 4095;
						else
							b_lcl := b_lcl - 1;
						end if;
						if g1_lcl=4095 then
							g1_lcl := 0;
						else
							g1_lcl := g1_lcl + 1;
						end if;
					end if;
					-- IP impl.synth.rgb.nextCol --- IEND

					stateSynth <= stateSynthRgb;
				end if;

			elsif stateSynth=stateSynthHdr then
				-- IP impl.synth.hdr.pre --- IBEGIN
				-- pattern II: HDR rgb ramp where per line central 16 of 24 bits are shifted 0-2-4-0-2-4 bits
				toVideoinAXIS_tvalid_sig <= '1';

				if row(0)='0' then
					w1 := (others => '0');
					w1(2*rsh+4+11 downto 2*rsh+4) := std_logic_vector(to_unsigned(r_lcl, 12));

					w0 := (others => '0');
					w0(2*gsh+4+11 downto 2*gsh+4) := std_logic_vector(to_unsigned(g0_lcl, 12));
				else
					w1 := (others => '0');
					w1(2*gsh+4+11 downto 2*gsh+4) := std_logic_vector(to_unsigned(g1_lcl, 12));

					w0 := (others => '0');
					w0(2*bsh+4+11 downto 2*bsh+4) := std_logic_vector(to_unsigned(b_lcl, 12));
				end if;

				toVideoinAXIS_tdata_sig(23 downto 12) <= w1(3*ixTExp_sig+11 downto 3*ixTExp_sig);
				toVideoinAXIS_tdata_sig(11 downto 0) <= w0(3*ixTExp_sig+11 downto 3*ixTExp_sig);
				-- IP impl.synth.hdr.pre --- IEND

				if col=unsigned(NCol)-1 then
					i := 0; -- IP impl.synth.hdr.rowDone --- ILINE

					stateSynth <= stateSynthEol;

				else
					-- IP impl.synth.hdr.nextCol --- IBEGIN
					col <= col + 1;

					if row(0)='0' then
						if r_lcl=4095 then
							r_lcl := 0;
						else
							r_lcl := r_lcl + 1;
						end if;
						if g0_lcl=4095 then
							g0_lcl := 0;
						else
							g0_lcl := g0_lcl + 1;
						end if;
					else
						if b_lcl=0 then
							b_lcl := 4095;
						else
							b_lcl := b_lcl - 1;
						end if;
						if g1_lcl=4095 then
							g1_lcl := 0;
						else
							g1_lcl := g1_lcl + 1;
						end if;
					end if;
					-- IP impl.synth.hdr.nextCol --- IEND

					stateSynth <= stateSynthHdr;
				end if;

			elsif stateSynth=stateSynthChk then
				-- IP impl.synth.chk.pre --- IBEGIN
				-- pattern III: grayscale checkerboard with contrast from 0 vs. 4095 via 1024 vs. 4095-1024 via 1024+512 via 1024+512+256 ... up to 2047 vs. 2048 (11 steps)
				toVideoinAXIS_tvalid_sig <= '1';

				if not whtNotBlk then
					toVideoinAXIS_tdata_sig <= std_logic_vector(blk) & std_logic_vector(blk);
				else
					toVideoinAXIS_tdata_sig <= std_logic_vector(wht) & std_logic_vector(wht);
				end if;
				-- IP impl.synth.chk.pre --- IEND

				if col=unsigned(NCol)-1 then
					i := 0; -- IP impl.synth.chk.rowDone --- ILINE

					stateSynth <= stateSynthEol;

				else
					-- IP impl.synth.chk.nextCol --- IBEGIN
					col <= col + 1;

					if colchk=NSqr-1 then
						colchk := 0;
						whtNotBlk := not whtNotBlk;
					else
						colchk := colchk + 1;
					end if;
					-- IP impl.synth.chk.nextCol --- IEND

					stateSynth <= stateSynthChk;
				end if;

			elsif stateSynth=stateSynthEol then
				toVideoinAXIS_tvalid_sig <= '0'; -- IP impl.synth.eol.pre --- ILINE

				if i=to_integer(unsigned(Tlinepad)) then
					if row=unsigned(NRowRaw)-1 then
						j := 0; -- IP impl.synth.eol.done --- ILINE

						stateSynth <= stateSynthEofA;

					else
						-- IP impl.synth.eol.nextRow --- IBEGIN
						row <= row + 1;
						col <= (others => '0');
						-- IP impl.synth.eol.nextRow --- IEND

						if tixVSynthmode=tixVSynthmodeRgb then
							-- IP impl.synth.eol.restartRgb --- IBEGIN
							if row(0)='1' then
								r_lcl := 0;
								g0_lcl := 2048;
								g1_lcl := 2048;
								b_lcl := 4095;
							end if;
							-- IP impl.synth.eol.restartRgb --- IEND

							stateSynth <= stateSynthRgb;

						elsif tixVSynthmode=tixVSynthmodeHdr then
							-- IP impl.synth.eol.restartHdr --- IBEGIN
							if row(0)='1' then
								r_lcl := 0;
								g0_lcl := 2048;
								g1_lcl := 2048;
								b_lcl := 4095;

								if rsh=2 then
									rsh := 0;
								else
									rsh := rsh + 1;
								end if;
								if gsh=2 then
									gsh := 0;
								else
									gsh := gsh + 1;
								end if;
								if bsh=2 then
									bsh := 0;
								else
									bsh := bsh + 1;
								end if;
							end if;
							-- IP impl.synth.eol.restartHdr --- IEND

							stateSynth <= stateSynthHdr;

						elsif tixVSynthmode=tixVSynthmodeChk then
							-- IP impl.synth.eol.restartChk --- IBEGIN
							if rowchk=NSqr-1 then
								rowchk := 0;

								whtNotBlk0 := not whtNotBlk0;

								if blk(0)='1' then
									blk := (others => '0');
									wht := (others => '1');
								else
									-- delta 4095, 2047, 1023, ...,  1
									blk(10 downto 0) := "1" & blk(10 downto 1);
									wht(10 downto 0) := "0" & wht(10 downto 1);
								end if;
				
							else
								rowchk := rowchk + 1;
							end if;

							colchk := 0;

							whtNotBlk := whtNotBlk0;
							-- IP impl.synth.eol.restartChk --- IEND

							stateSynth <= stateSynthChk;
						end if;
					end if;

				else
					i := i + 1; -- IP impl.synth.eol.inc --- ILINE

					stateSynth <= stateSynthEol;
				end if;

			elsif stateSynth=stateSynthEofA then
				if j=to_integer(unsigned(TFramepad(15 downto 1))) then
					-- IP impl.synth.eofA.done --- IBEGIN
					if hdrNotFix='1' then
						if ixTExp_sig=ixTExpLast then -- require ixTExp to increment before vsync goes down
							ixTExp_sig <= 0;
						else
							ixTExp_sig <= ixTExp_sig + 1;
						end if;
					end if;
					
					j := 0;
					-- IP impl.synth.eofA.done --- IEND

					stateSynth <= stateSynthEofB;

				else
					j := j + 1; -- IP impl.synth.eofA.inc --- ILINE

					stateSynth <= stateSynthEofA;
				end if;

			elsif stateSynth=stateSynthEofB then
				if j=to_integer(unsigned(TFramepad(15 downto 1))) then
					-- IP impl.synth.eofB.done --- IBEGIN
					row <= (others => '0');
					col <= (others => '0');
					-- IP impl.synth.eofB.done --- IEND

					if tixVSynthmode=tixVSynthmodeRgb then
						-- IP impl.synth.eofB.restartRgb --- IBEGIN
						r_lcl := 0;
						g0_lcl := 2048;
						g1_lcl := 2048;
						b_lcl := 4095;
						-- IP impl.synth.eofB.restartRgb --- IEND

						stateSynth <= stateSynthRgb;

					elsif tixVSynthmode=tixVSynthmodeHdr then
						-- IP impl.synth.eofB.restartHdr --- IBEGIN
						r_lcl := 0;
						g0_lcl := 2048;
						g1_lcl := 2048;
						b_lcl := 4095;
			
						rsh := 0;
						gsh := 1;
						bsh := 2;
						-- IP impl.synth.eofB.restartHdr --- IEND

						stateSynth <= stateSynthHdr;

					elsif tixVSynthmode=tixVSynthmodeChk then
						-- IP impl.synth.eofB.restartChk --- IBEGIN
						whtNotBlk0 := false;
						whtNotBlk := false;
						rowchk := 0;
						colchk := 0;
						blk := (others => '0');
						wht := (others => '1');
						-- IP impl.synth.eofB.restartChk --- IEND

						stateSynth <= stateSynthChk;
					end if;

				else
					j := j + 1; -- IP impl.synth.eofB.inc --- ILINE

					stateSynth <= stateSynthEofB;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.synth.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- IBEGIN
	mipiAXIS_dbg(0) <= pixel_data_valid;
	mipiAXIS_dbg(1) <= '1' when datatype=tixVFormatRaw12(5 downto 0) else '0';
	mipiAXIS_dbg(2) <= datatype(0);
	mipiAXIS_dbg(3) <= hsync_vc0n;

	video_out_dbg(0) <= video_out_tvalid;
	video_out_dbg(1) <= '1' when video_out_tuser(5 downto 0)=tixVFormatRaw12(5 downto 0) else '0';
	video_out_dbg(2) <= video_out_tuser(0);
	video_out_dbg(3) <= video_out_tlast;

	mipirx_RESET_N <= resetn;
	mipirx_RST0_N <= resetnPixrxclk;

	mipirx_ERR_CONTROL <= mipirx_ERR_CONTROL_LAN3 & mipirx_ERR_CONTROL_LAN2 & mipirx_ERR_CONTROL_LAN1 & mipirx_ERR_CONTROL_LAN0;
	mipirx_ERR_ESC <= mipirx_ERR_ESC_LAN3 & mipirx_ERR_ESC_LAN2 & mipirx_ERR_ESC_LAN1 & mipirx_ERR_ESC_LAN0;
	mipirx_ERR_SOT_SYNC_HS <= mipirx_ERR_SOT_SYNC_HS_LAN3 & mipirx_ERR_SOT_SYNC_HS_LAN2 & mipirx_ERR_SOT_SYNC_HS_LAN1 & mipirx_ERR_SOT_SYNC_HS_LAN0; -- eliminated
	mipirx_ESC_CLK <= mipirx_ESC_CLK_LAN3 & mipirx_ESC_CLK_LAN2 & mipirx_ESC_CLK_LAN1 & mipirx_ESC_CLK_LAN0; -- eliminated
	mipirx_RX_SKEW_CAL_HS <= mipirx_RX_SKEW_CAL_HS_LAN3 & mipirx_RX_SKEW_CAL_HS_LAN2 & mipirx_RX_SKEW_CAL_HS_LAN1 & mipirx_RX_SKEW_CAL_HS_LAN0;
	mipirx_RX_SYNC_HS <= mipirx_RX_SYNC_HS_LAN3 & mipirx_RX_SYNC_HS_LAN2 & mipirx_RX_SYNC_HS_LAN1 & mipirx_RX_SYNC_HS_LAN0; -- eliminated
	mipirx_RX_ULPS_ACTIVE_NOT <= mipirx_RX_ULPS_ACTIVE_NOT_LAN3 & mipirx_RX_ULPS_ACTIVE_NOT_LAN2 & mipirx_RX_ULPS_ACTIVE_NOT_LAN1 & mipirx_RX_ULPS_ACTIVE_NOT_LAN0;
	mipirx_RX_ULPS_ESC <= mipirx_RX_ULPS_ESC_LAN3 & mipirx_RX_ULPS_ESC_LAN2 & mipirx_RX_ULPS_ESC_LAN1 & mipirx_RX_ULPS_ESC_LAN0;

	mipirx_RX_VALID_HS_LAN0_sig <= mipirx_RX_VALID_HS_LAN0 & mipirx_RX_VALID_HS_LAN0; -- all these are eliminated
	mipirx_RX_VALID_HS_LAN1_sig <= mipirx_RX_VALID_HS_LAN1 & mipirx_RX_VALID_HS_LAN1;
	mipirx_RX_VALID_HS_LAN2_sig <= mipirx_RX_VALID_HS_LAN2 & mipirx_RX_VALID_HS_LAN2;
	mipirx_RX_VALID_HS_LAN3_sig <= mipirx_RX_VALID_HS_LAN3 & mipirx_RX_VALID_HS_LAN3;

	mipirx_RX_ULPS_CLK_NOT_sig(0) <= mipirx_RX_ULPS_CLK_NOT;
	mipirx_RX_ULPS_ACTIVE_CLK_NOT_sig(0) <= mipirx_RX_ULPS_ACTIVE_CLK_NOT;
	
	mipirx_STOPSTATE <= mipirx_STOPSTATE_LAN3 & mipirx_STOPSTATE_LAN2 & mipirx_STOPSTATE_LAN1 & mipirx_STOPSTATE_LAN0;

	datatype_dbg <= datatype;
	-- IP impl.oth.cust --- IEND

end Rtl;
