-- file Dpbram_size8kB_a64b64.vhd
-- Dpbram_size8kB_a64b64 dpbram_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 4 Nov 2025
-- IP header --- ABOVE

-- module parameters:
-- size (size [kB]): 8
-- wA (A-side width [bit]): 64
-- wB (B-side width [bit]): 64

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Dpbram_size8kB_a64b64 is
	port (
		rstA: in std_logic;
		clkA: in std_logic;

		enA: in std_logic;
		weA: in std_logic;

		aA: in std_logic_vector(9 downto 0);
		drdA: out std_logic_vector(63 downto 0);
		dwrA: in std_logic_vector(63 downto 0);

		rstB: in std_logic;
		clkB: in std_logic;

		enB: in std_logic;
		weB: in std_logic;

		aB: in std_logic_vector(9 downto 0);
		drdB: out std_logic_vector(63 downto 0);
		dwrB: in std_logic_vector(63 downto 0)
	);
end Dpbram_size8kB_a64b64;

architecture Rtl of Dpbram_size8kB_a64b64 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_efnx_size8kB_a64b64 is
		port (
			clk_a: in std_logic;

			addren_a: in std_logic;
			we_a: in std_logic_vector(0 downto 0);

			addr_a: in std_logic_vector(9 downto 0);
			rdata_a: out std_logic_vector(63 downto 0);
			wdata_a: in std_logic_vector(63 downto 0);

			clk_b: in std_logic;

			addren_b: in std_logic;
			we_b: in std_logic_vector(0 downto 0);

			addr_b: in std_logic_vector(9 downto 0);
			rdata_b: out std_logic_vector(63 downto 0);
			wdata_b: in std_logic_vector(63 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	signal we_a_sig: std_logic_vector(0 downto 0);
	signal we_b_sig: std_logic_vector(0 downto 0);
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myMnfcore : Dpbram_efnx_size8kB_a64b64
		port map (
			clk_a => clkA,

			addren_a => enA,
			we_a => we_a_sig,

			addr_a => aA,
			rdata_a => drdA,
			wdata_a => dwrA,

			clk_b => clkB,

			addren_b => enB,
			we_b => we_b_sig,

			addr_b => aB,
			rdata_b => drdB,
			wdata_b => dwrB
		);

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	we_a_sig(0) <= weA and enA;
	we_b_sig(0) <= weB and enB;

end Rtl;
