-- file State.vhd
-- State easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity State is
	port (
		reset: in std_logic;
		mclk: in std_logic;
		tkclk: in std_logic;
		commok: in std_logic;
		rng: in std_logic;
		rgb: out std_logic_vector(23 downto 0)
	);
end State;

architecture Rtl of State is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant rgbWhite: std_logic_vector(23 downto 0) := x"555555";
	constant rgbRed: std_logic_vector(23 downto 0) := x"FF0000";
	constant rgbOrange: std_logic_vector(23 downto 0) := x"7F7F00";

	constant rgbGreen: std_logic_vector(23 downto 0) := x"00FF00";
	constant rgbGreenD1: std_logic_vector(23 downto 0) := x"00D000";
	constant rgbGreenD2: std_logic_vector(23 downto 0) := x"00A000";
	constant rgbGreenD3: std_logic_vector(23 downto 0) := x"007000";
	constant rgbGreenD4: std_logic_vector(23 downto 0) := x"004000";

	constant rgbBluegreen: std_logic_vector(23 downto 0) := x"007F7F";
	constant rgbBlue: std_logic_vector(23 downto 0) := x"0000FF";
	constant rgbPink: std_logic_vector(23 downto 0) := x"7F007F";

	---- RGB LED control (led)
	type stateLed_t is (
		stateLedRunA, stateLedRunB
	);
	signal stateLed: stateLed_t;

	constant sizeSeq: natural := 5;
	type seq_t is array (0 to sizeSeq-1) of std_logic_vector(23 downto 0);
	signal seq: seq_t;
	signal ixSeq: natural range 0 to sizeSeq-1;

	-- IP sigs.led.cust --- INSERT

	---- other
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- implementation: RGB LED control (led)
	------------------------------------------------------------------------

	-- IP impl.led.wiring --- BEGIN
	-- IP impl.led.wiring --- END

	-- IP impl.led.wiring.cust --- RBEGIN
	rgb <= seq(ixSeq);
	-- IP impl.led.wiring.cust --- REND

	-- IP impl.led.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.led.vars --- RBEGIN
		variable rgb_lcl: std_logic_vector(23 downto 0);

		constant imax: natural := 2000; -- 200ms slice time
		variable i: natural range 0 to imax;
		-- IP impl.led.vars --- REND

	begin
		if reset='1' then
			-- IP impl.led.asyncrst --- BEGIN
			stateLed <= stateLedRunA;
			ixSeq <= 0;

			-- IP impl.led.asyncrst --- END
			-- IP impl.led.asyncrst.cust --- IBEGIN
			seq <= (others => (others => '0'));

			rgb_lcl := (others => '0');
			i := 0;
			-- IP impl.led.asyncrst.cust --- IEND

		elsif rising_edge(mclk) then
			if stateLed=stateLedRunA then
				if tkclk='1' then
					-- IP impl.led.runA --- IBEGIN
					if i=imax then
						i := 0;

						if ixSeq=sizeSeq-1 then
							ixSeq <= 0;

							if commok='0' then
								seq <= (rgbRed, x"000000", x"000000", x"000000", x"000000");

							elsif rng='1' then
								rgb_lcl := rgbBlue;
	
								for j in 0 to sizeSeq-1 loop
									seq(j) <= rgb_lcl;
								end loop;

							else
								seq(0) <= rgbGreenD4;
								seq(1) <= rgbGreenD3;
								seq(2) <= rgbGreenD2;
								seq(3) <= rgbGreenD1;
								seq(4) <= rgbGreen;
							end if;

						else
							ixSeq <= ixSeq + 1;
						end if;
					end if;
					-- IP impl.led.runA --- IEND

					stateLed <= stateLedRunB;
				end if;

			elsif stateLed=stateLedRunB then
				if tkclk='0' then
					i := i + 1; -- IP impl.led.runB --- ILINE

					stateLed <= stateLedRunA;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.led.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;
