
//
// Verific Verilog Description of module vsp_core
//

module vsp_core (aresetn, aclk, pixrxclk, memclk, resetnMemclk, probe, 
            clk_byte_HS, cs, sclk, mosi, rgb0_r, rgb0_g, rgb0_b, 
            rgb1_r, rgb1_g, rgb1_b, nslp, m0, m0z, m1, m1z, 
            dir, step, apuAXIL_araddr, apuAXIL_arprot, apuAXIL_arready, 
            apuAXIL_arvalid, apuAXIL_rdata, apuAXIL_rready, apuAXIL_rresp, 
            apuAXIL_rvalid, apuAXIL_rlast, apuAXIL_awaddr, apuAXIL_awprot, 
            apuAXIL_awready, apuAXIL_awvalid, apuAXIL_wdata, apuAXIL_wready, 
            apuAXIL_wstrb, apuAXIL_wvalid, apuAXIL_bready, apuAXIL_bresp, 
            apuAXIL_bvalid, ddrAXI_rready, ddrAXI_wvalid, mipirx_RESET_N, 
            mipirx_RST0_N, mipirx_ERR_CONTROL_LAN0, mipirx_ERR_CONTROL_LAN1, 
            mipirx_ERR_CONTROL_LAN2, mipirx_ERR_CONTROL_LAN3, mipirx_ERR_ESC_LAN0, 
            mipirx_ERR_ESC_LAN1, mipirx_ERR_ESC_LAN2, mipirx_ERR_ESC_LAN3, 
            mipirx_ERR_SOT_SYNC_HS_LAN0, mipirx_ERR_SOT_SYNC_HS_LAN1, mipirx_ERR_SOT_SYNC_HS_LAN2, 
            mipirx_ERR_SOT_SYNC_HS_LAN3, mipirx_ESC_CLK_LAN0, mipirx_ESC_CLK_LAN1, 
            mipirx_ESC_CLK_LAN2, mipirx_ESC_CLK_LAN3, mipirx_RX_DATA_HS_LAN0, 
            mipirx_RX_DATA_HS_LAN1, mipirx_RX_DATA_HS_LAN2, mipirx_RX_DATA_HS_LAN3, 
            mipirx_RX_SKEW_CAL_HS_LAN0, mipirx_RX_SKEW_CAL_HS_LAN1, mipirx_RX_SKEW_CAL_HS_LAN2, 
            mipirx_RX_SKEW_CAL_HS_LAN3, mipirx_RX_SYNC_HS_LAN0, mipirx_RX_SYNC_HS_LAN1, 
            mipirx_RX_SYNC_HS_LAN2, mipirx_RX_SYNC_HS_LAN3, mipirx_RX_ULPS_ACTIVE_CLK_NOT, 
            mipirx_RX_ULPS_ACTIVE_NOT_LAN0, mipirx_RX_ULPS_ACTIVE_NOT_LAN1, 
            mipirx_RX_ULPS_ACTIVE_NOT_LAN2, mipirx_RX_ULPS_ACTIVE_NOT_LAN3, 
            mipirx_RX_ULPS_CLK_NOT, mipirx_RX_ULPS_ESC_LAN0, mipirx_RX_ULPS_ESC_LAN1, 
            mipirx_RX_ULPS_ESC_LAN2, mipirx_RX_ULPS_ESC_LAN3, mipirx_RX_VALID_HS_LAN0, 
            mipirx_RX_VALID_HS_LAN1, mipirx_RX_VALID_HS_LAN2, mipirx_RX_VALID_HS_LAN3, 
            mipirx_STOPSTATE_LAN0, mipirx_STOPSTATE_LAN1, mipirx_STOPSTATE_LAN2, 
            mipirx_STOPSTATE_LAN3, scl_in, scl_out, scl_tri, sda_in, 
            sda_out, sda_tri, ddrAXI_arid, ddrAXI_araddr, ddrAXI_arburst, 
            ddrAXI_arcache, ddrAXI_arlen, ddrAXI_arlock, ddrAXI_arprot, 
            ddrAXI_arqos, ddrAXI_arready, ddrAXI_arregion, ddrAXI_arsize, 
            ddrAXI_arvalid, ddrAXI_rid, ddrAXI_rdata, ddrAXI_rlast, 
            ddrAXI_rresp, ddrAXI_rvalid, ddrAXI_awid, ddrAXI_awaddr, 
            ddrAXI_awburst, ddrAXI_awcache, ddrAXI_awlen, ddrAXI_awlock, 
            ddrAXI_awprot, ddrAXI_awqos, ddrAXI_awready, ddrAXI_awregion, 
            ddrAXI_awsize, ddrAXI_awvalid, ddrAXI_wdata, ddrAXI_wlast, 
            ddrAXI_wready, ddrAXI_wstrb, ddrAXI_bid, ddrAXI_bready, 
            ddrAXI_bresp, ddrAXI_bvalid) /* verific EFX_ATTRIBUTE_NETLIST__TOP_IS_VHDL=TRUE */ ;
    input aresetn /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(36)
    input aclk /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(37)
    input pixrxclk /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(38)
    input memclk /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(39)
    output resetnMemclk /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(40)
    output [5:0]probe /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(41)
    input clk_byte_HS /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(42)
    output cs /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(43)
    output sclk /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(44)
    output mosi /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(45)
    output rgb0_r /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(46)
    output rgb0_g /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(47)
    output rgb0_b /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(48)
    output rgb1_r /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(49)
    output rgb1_g /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(50)
    output rgb1_b /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(51)
    output nslp /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(52)
    output m0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(53)
    output m0z /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(54)
    output m1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(55)
    output m1z /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(56)
    output dir /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(57)
    output step /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(58)
    input [31:0]apuAXIL_araddr /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(60)
    input [2:0]apuAXIL_arprot /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(61)
    output apuAXIL_arready /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(62)
    input apuAXIL_arvalid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(63)
    output [31:0]apuAXIL_rdata /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    input apuAXIL_rready /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(66)
    output [1:0]apuAXIL_rresp /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(67)
    output apuAXIL_rvalid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(68)
    output apuAXIL_rlast /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(69)
    input [31:0]apuAXIL_awaddr /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(71)
    input [2:0]apuAXIL_awprot /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(72)
    output apuAXIL_awready /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(73)
    input apuAXIL_awvalid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(74)
    input [31:0]apuAXIL_wdata /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(76)
    output apuAXIL_wready /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(77)
    input [3:0]apuAXIL_wstrb /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(78)
    input apuAXIL_wvalid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(79)
    input apuAXIL_bready /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(81)
    output [1:0]apuAXIL_bresp /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(82)
    output apuAXIL_bvalid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(83)
    output ddrAXI_rready /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(85)
    output ddrAXI_wvalid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(86)
    output mipirx_RESET_N /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(88)
    output mipirx_RST0_N /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(89)
    input mipirx_ERR_CONTROL_LAN0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(90)
    input mipirx_ERR_CONTROL_LAN1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(91)
    input mipirx_ERR_CONTROL_LAN2 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(92)
    input mipirx_ERR_CONTROL_LAN3 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(93)
    input mipirx_ERR_ESC_LAN0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(94)
    input mipirx_ERR_ESC_LAN1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(95)
    input mipirx_ERR_ESC_LAN2 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(96)
    input mipirx_ERR_ESC_LAN3 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(97)
    input mipirx_ERR_SOT_SYNC_HS_LAN0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(98)
    input mipirx_ERR_SOT_SYNC_HS_LAN1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(99)
    input mipirx_ERR_SOT_SYNC_HS_LAN2 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(100)
    input mipirx_ERR_SOT_SYNC_HS_LAN3 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(101)
    input mipirx_ESC_CLK_LAN0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(102)
    input mipirx_ESC_CLK_LAN1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(103)
    input mipirx_ESC_CLK_LAN2 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(104)
    input mipirx_ESC_CLK_LAN3 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(105)
    input [15:0]mipirx_RX_DATA_HS_LAN0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(106)
    input [15:0]mipirx_RX_DATA_HS_LAN1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(107)
    input [15:0]mipirx_RX_DATA_HS_LAN2 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(108)
    input [15:0]mipirx_RX_DATA_HS_LAN3 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(109)
    input mipirx_RX_SKEW_CAL_HS_LAN0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(110)
    input mipirx_RX_SKEW_CAL_HS_LAN1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(111)
    input mipirx_RX_SKEW_CAL_HS_LAN2 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(112)
    input mipirx_RX_SKEW_CAL_HS_LAN3 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(113)
    input mipirx_RX_SYNC_HS_LAN0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(114)
    input mipirx_RX_SYNC_HS_LAN1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(115)
    input mipirx_RX_SYNC_HS_LAN2 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(116)
    input mipirx_RX_SYNC_HS_LAN3 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(117)
    input mipirx_RX_ULPS_ACTIVE_CLK_NOT /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(118)
    input mipirx_RX_ULPS_ACTIVE_NOT_LAN0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(119)
    input mipirx_RX_ULPS_ACTIVE_NOT_LAN1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(120)
    input mipirx_RX_ULPS_ACTIVE_NOT_LAN2 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(121)
    input mipirx_RX_ULPS_ACTIVE_NOT_LAN3 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(122)
    input mipirx_RX_ULPS_CLK_NOT /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(123)
    input mipirx_RX_ULPS_ESC_LAN0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(124)
    input mipirx_RX_ULPS_ESC_LAN1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(125)
    input mipirx_RX_ULPS_ESC_LAN2 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(126)
    input mipirx_RX_ULPS_ESC_LAN3 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(127)
    input mipirx_RX_VALID_HS_LAN0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(128)
    input mipirx_RX_VALID_HS_LAN1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(129)
    input mipirx_RX_VALID_HS_LAN2 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(130)
    input mipirx_RX_VALID_HS_LAN3 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(131)
    input mipirx_STOPSTATE_LAN0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(132)
    input mipirx_STOPSTATE_LAN1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(133)
    input mipirx_STOPSTATE_LAN2 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(134)
    input mipirx_STOPSTATE_LAN3 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(135)
    input scl_in /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(137)
    output scl_out /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(138)
    output scl_tri /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(139)
    input sda_in /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(141)
    output sda_out /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(142)
    output sda_tri /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(143)
    output [5:0]ddrAXI_arid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(145)
    output [32:0]ddrAXI_araddr /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    output [1:0]ddrAXI_arburst /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(147)
    output [3:0]ddrAXI_arcache /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(148)
    output [7:0]ddrAXI_arlen /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(149)
    output [0:0]ddrAXI_arlock /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(150)
    output [2:0]ddrAXI_arprot /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(151)
    output [3:0]ddrAXI_arqos /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(152)
    input ddrAXI_arready /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(153)
    output [3:0]ddrAXI_arregion /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(154)
    output [2:0]ddrAXI_arsize /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(155)
    output ddrAXI_arvalid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(156)
    input [5:0]ddrAXI_rid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(158)
    input [511:0]ddrAXI_rdata /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(159)
    input ddrAXI_rlast /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(160)
    input [1:0]ddrAXI_rresp /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(161)
    input ddrAXI_rvalid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(162)
    output [5:0]ddrAXI_awid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(164)
    output [32:0]ddrAXI_awaddr /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    output [1:0]ddrAXI_awburst /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(166)
    output [3:0]ddrAXI_awcache /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(167)
    output [7:0]ddrAXI_awlen /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(168)
    output [0:0]ddrAXI_awlock /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(169)
    output [2:0]ddrAXI_awprot /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(170)
    output [3:0]ddrAXI_awqos /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(171)
    input ddrAXI_awready /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(172)
    output [3:0]ddrAXI_awregion /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(173)
    output [2:0]ddrAXI_awsize /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(174)
    output ddrAXI_awvalid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(175)
    output [511:0]ddrAXI_wdata /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    output ddrAXI_wlast /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(178)
    input ddrAXI_wready /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(179)
    output [63:0]ddrAXI_wstrb /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    input [5:0]ddrAXI_bid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(182)
    output ddrAXI_bready /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(183)
    input [1:0]ddrAXI_bresp /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(184)
    input ddrAXI_bvalid /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_INPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(185)
    
    
    wire stateMemclk;
    wire [4:0]i_3;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3635)
    
    wire resetMemclk, statePixrxclk;
    wire [3:0]i;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3698)
    
    wire resetPixrxclk, ceg_net8765;
    wire [4:0]n8868;
    
    wire ceg_net8771, ceg_net10031;
    wire [3:0]n8923;
    
    wire n1419, n1420, n1526, n1527;
    
    assign probe[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(41)
    assign probe[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(41)
    assign probe[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(41)
    assign probe[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(41)
    assign probe[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(41)
    assign probe[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(41)
    assign cs = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(43)
    assign sclk = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(44)
    assign mosi = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(45)
    assign rgb0_r = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(46)
    assign rgb0_g = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(47)
    assign rgb0_b = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(48)
    assign rgb1_r = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(49)
    assign rgb1_g = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(50)
    assign rgb1_b = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(51)
    assign nslp = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(52)
    assign m0 = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(53)
    assign m0z = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(54)
    assign m1 = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(55)
    assign m1z = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(56)
    assign dir = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(57)
    assign step = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(58)
    assign apuAXIL_arready = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(62)
    assign apuAXIL_rdata[31] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[30] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[29] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[28] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[27] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[26] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[25] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[24] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[23] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[22] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[21] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[20] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[19] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[18] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[17] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[16] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[15] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[14] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[13] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[12] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[11] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[10] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[9] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[8] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rdata[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(65)
    assign apuAXIL_rresp[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(67)
    assign apuAXIL_rresp[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(67)
    assign apuAXIL_rvalid = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(68)
    assign apuAXIL_rlast = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(69)
    assign apuAXIL_awready = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(73)
    assign apuAXIL_wready = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(77)
    assign apuAXIL_bresp[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(82)
    assign apuAXIL_bresp[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(82)
    assign apuAXIL_bvalid = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(83)
    assign ddrAXI_rready = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(85)
    assign ddrAXI_wvalid = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(86)
    assign mipirx_RESET_N = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(88)
    assign scl_out = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(138)
    assign scl_tri = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(139)
    assign sda_out = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(142)
    assign sda_tri = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(143)
    assign ddrAXI_arid[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(145)
    assign ddrAXI_arid[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(145)
    assign ddrAXI_arid[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(145)
    assign ddrAXI_arid[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(145)
    assign ddrAXI_arid[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(145)
    assign ddrAXI_arid[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(145)
    assign ddrAXI_araddr[32] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[31] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[30] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[29] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[28] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[27] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[26] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[25] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[24] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[23] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[22] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[21] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[20] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[19] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[18] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[17] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[16] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[15] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[14] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[13] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[12] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[11] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[10] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[9] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[8] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_araddr[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(146)
    assign ddrAXI_arburst[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(147)
    assign ddrAXI_arburst[0] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(147)
    assign ddrAXI_arcache[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(148)
    assign ddrAXI_arcache[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(148)
    assign ddrAXI_arcache[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(148)
    assign ddrAXI_arcache[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(148)
    assign ddrAXI_arlen[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(149)
    assign ddrAXI_arlen[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(149)
    assign ddrAXI_arlen[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(149)
    assign ddrAXI_arlen[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(149)
    assign ddrAXI_arlen[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(149)
    assign ddrAXI_arlen[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(149)
    assign ddrAXI_arlen[1] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(149)
    assign ddrAXI_arlen[0] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(149)
    assign ddrAXI_arlock[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(150)
    assign ddrAXI_arprot[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(151)
    assign ddrAXI_arprot[1] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(151)
    assign ddrAXI_arprot[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(151)
    assign ddrAXI_arqos[3] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(152)
    assign ddrAXI_arqos[2] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(152)
    assign ddrAXI_arqos[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(152)
    assign ddrAXI_arqos[0] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(152)
    assign ddrAXI_arregion[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(154)
    assign ddrAXI_arregion[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(154)
    assign ddrAXI_arregion[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(154)
    assign ddrAXI_arregion[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(154)
    assign ddrAXI_arsize[2] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(155)
    assign ddrAXI_arsize[1] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(155)
    assign ddrAXI_arsize[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(155)
    assign ddrAXI_arvalid = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(156)
    assign ddrAXI_awid[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(164)
    assign ddrAXI_awid[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(164)
    assign ddrAXI_awid[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(164)
    assign ddrAXI_awid[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(164)
    assign ddrAXI_awid[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(164)
    assign ddrAXI_awid[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(164)
    assign ddrAXI_awaddr[32] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[31] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[30] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[29] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[28] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[27] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[26] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[25] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[24] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[23] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[22] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[21] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[20] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[19] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[18] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[17] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[16] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[15] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[14] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[13] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[12] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[11] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[10] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[9] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[8] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awaddr[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(165)
    assign ddrAXI_awburst[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(166)
    assign ddrAXI_awburst[0] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(166)
    assign ddrAXI_awcache[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(167)
    assign ddrAXI_awcache[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(167)
    assign ddrAXI_awcache[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(167)
    assign ddrAXI_awcache[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(167)
    assign ddrAXI_awlen[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(168)
    assign ddrAXI_awlen[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(168)
    assign ddrAXI_awlen[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(168)
    assign ddrAXI_awlen[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(168)
    assign ddrAXI_awlen[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(168)
    assign ddrAXI_awlen[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(168)
    assign ddrAXI_awlen[1] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(168)
    assign ddrAXI_awlen[0] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(168)
    assign ddrAXI_awlock[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(169)
    assign ddrAXI_awprot[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(170)
    assign ddrAXI_awprot[1] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(170)
    assign ddrAXI_awprot[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(170)
    assign ddrAXI_awqos[3] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(171)
    assign ddrAXI_awqos[2] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(171)
    assign ddrAXI_awqos[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(171)
    assign ddrAXI_awqos[0] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(171)
    assign ddrAXI_awregion[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(173)
    assign ddrAXI_awregion[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(173)
    assign ddrAXI_awregion[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(173)
    assign ddrAXI_awregion[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(173)
    assign ddrAXI_awsize[2] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(174)
    assign ddrAXI_awsize[1] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(174)
    assign ddrAXI_awsize[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(174)
    assign ddrAXI_awvalid = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(175)
    assign ddrAXI_wdata[511] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[510] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[509] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[508] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[507] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[506] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[505] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[504] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[503] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[502] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[501] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[500] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[499] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[498] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[497] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[496] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[495] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[494] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[493] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[492] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[491] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[490] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[489] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[488] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[487] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[486] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[485] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[484] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[483] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[482] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[481] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[480] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[479] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[478] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[477] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[476] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[475] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[474] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[473] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[472] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[471] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[470] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[469] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[468] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[467] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[466] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[465] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[464] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[463] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[462] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[461] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[460] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[459] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[458] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[457] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[456] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[455] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[454] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[453] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[452] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[451] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[450] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[449] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[448] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[447] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[446] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[445] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[444] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[443] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[442] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[441] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[440] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[439] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[438] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[437] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[436] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[435] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[434] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[433] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[432] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[431] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[430] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[429] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[428] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[427] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[426] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[425] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[424] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[423] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[422] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[421] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[420] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[419] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[418] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[417] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[416] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[415] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[414] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[413] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[412] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[411] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[410] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[409] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[408] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[407] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[406] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[405] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[404] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[403] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[402] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[401] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[400] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[399] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[398] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[397] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[396] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[395] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[394] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[393] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[392] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[391] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[390] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[389] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[388] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[387] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[386] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[385] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[384] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[383] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[382] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[381] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[380] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[379] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[378] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[377] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[376] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[375] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[374] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[373] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[372] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[371] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[370] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[369] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[368] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[367] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[366] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[365] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[364] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[363] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[362] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[361] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[360] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[359] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[358] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[357] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[356] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[355] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[354] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[353] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[352] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[351] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[350] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[349] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[348] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[347] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[346] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[345] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[344] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[343] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[342] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[341] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[340] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[339] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[338] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[337] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[336] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[335] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[334] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[333] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[332] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[331] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[330] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[329] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[328] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[327] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[326] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[325] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[324] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[323] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[322] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[321] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[320] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[319] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[318] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[317] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[316] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[315] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[314] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[313] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[312] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[311] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[310] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[309] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[308] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[307] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[306] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[305] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[304] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[303] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[302] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[301] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[300] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[299] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[298] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[297] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[296] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[295] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[294] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[293] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[292] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[291] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[290] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[289] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[288] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[287] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[286] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[285] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[284] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[283] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[282] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[281] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[280] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[279] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[278] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[277] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[276] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[275] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[274] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[273] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[272] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[271] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[270] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[269] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[268] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[267] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[266] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[265] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[264] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[263] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[262] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[261] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[260] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[259] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[258] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[257] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[256] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[255] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[254] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[253] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[252] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[251] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[250] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[249] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[248] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[247] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[246] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[245] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[244] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[243] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[242] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[241] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[240] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[239] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[238] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[237] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[236] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[235] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[234] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[233] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[232] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[231] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[230] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[229] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[228] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[227] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[226] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[225] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[224] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[223] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[222] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[221] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[220] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[219] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[218] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[217] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[216] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[215] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[214] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[213] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[212] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[211] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[210] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[209] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[208] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[207] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[206] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[205] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[204] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[203] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[202] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[201] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[200] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[199] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[198] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[197] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[196] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[195] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[194] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[193] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[192] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[191] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[190] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[189] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[188] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[187] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[186] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[185] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[184] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[183] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[182] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[181] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[180] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[179] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[178] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[177] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[176] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[175] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[174] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[173] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[172] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[171] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[170] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[169] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[168] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[167] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[166] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[165] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[164] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[163] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[162] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[161] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[160] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[159] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[158] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[157] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[156] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[155] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[154] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[153] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[152] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[151] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[150] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[149] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[148] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[147] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[146] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[145] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[144] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[143] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[142] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[141] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[140] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[139] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[138] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[137] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[136] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[135] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[134] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[133] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[132] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[131] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[130] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[129] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[128] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[127] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[126] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[125] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[124] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[123] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[122] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[121] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[120] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[119] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[118] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[117] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[116] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[115] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[114] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[113] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[112] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[111] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[110] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[109] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[108] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[107] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[106] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[105] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[104] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[103] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[102] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[101] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[100] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[99] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[98] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[97] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[96] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[95] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[94] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[93] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[92] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[91] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[90] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[89] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[88] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[87] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[86] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[85] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[84] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[83] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[82] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[81] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[80] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[79] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[78] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[77] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[76] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[75] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[74] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[73] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[72] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[71] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[70] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[69] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[68] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[67] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[66] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[65] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[64] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[63] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[62] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[61] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[60] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[59] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[58] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[57] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[56] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[55] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[54] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[53] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[52] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[51] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[50] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[49] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[48] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[47] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[46] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[45] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[44] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[43] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[42] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[41] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[40] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[39] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[38] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[37] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[36] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[35] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[34] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[33] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[32] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[31] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[29] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[28] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[27] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[26] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[25] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[24] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[23] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[22] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[21] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[20] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[19] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[18] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[17] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[16] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[15] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[14] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[13] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[12] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[11] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[10] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[9] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[8] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[7] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[6] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[5] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[4] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[3] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[2] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[1] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wdata[0] = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(177)
    assign ddrAXI_wstrb[63] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[62] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[61] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[60] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[59] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[58] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[57] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[56] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[55] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[54] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[53] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[52] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[51] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[50] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[49] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[48] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[47] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[46] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[45] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[44] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[43] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[42] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[41] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[40] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[39] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[38] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[37] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[36] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[35] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[34] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[33] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[32] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[31] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[30] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[29] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[28] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[27] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[26] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[25] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[24] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[23] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[22] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[21] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[20] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[19] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[18] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[17] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[16] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[15] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[14] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[13] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[12] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[11] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[10] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[9] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[8] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[7] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[6] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[5] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[4] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[3] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[2] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[1] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_wstrb[0] = 1'b1 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(180)
    assign ddrAXI_bready = 1'b0 /* verific EFX_ATTRIBUTE_PORT__IS_PRIMARY_OUTPUT=TRUE, EFX_ATTRIBUTE_PORT__IS_VHDL_PORT_NAME=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(183)
    assign ddrAXI_wlast = 1'b1 /* verific EFX_ATTRIBUTE_CELL_NAME=VCC */ ;
    assign ddrAXI_wdata[30] = 1'b0 /* verific EFX_ATTRIBUTE_CELL_NAME=GND */ ;
    EFX_LUT4 LUT__3727 (.I0(stateMemclk), .I1(i_3[1]), .I2(n1419), .O(ceg_net8765)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1010 */ ;
    defparam LUT__3727.LUTMASK = 16'h1010;
    EFX_FF \stateMemclk~FF  (.D(ceg_net8765), .CE(ceg_net8765), .CLK(memclk), 
           .SR(aresetn), .Q(stateMemclk)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3681)
    defparam \stateMemclk~FF .CLK_POLARITY = 1'b1;
    defparam \stateMemclk~FF .CE_POLARITY = 1'b0;
    defparam \stateMemclk~FF .SR_POLARITY = 1'b0;
    defparam \stateMemclk~FF .D_POLARITY = 1'b1;
    defparam \stateMemclk~FF .SR_SYNC = 1'b0;
    defparam \stateMemclk~FF .SR_VALUE = 1'b0;
    defparam \stateMemclk~FF .SR_SYNC_PRIORITY = 1'b1;
    EFX_FF \i[0]_3~FF  (.D(n8868[0]), .CE(ceg_net8765), .CLK(memclk), 
           .SR(aresetn), .Q(i_3[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3681)
    defparam \i[0]_3~FF .CLK_POLARITY = 1'b1;
    defparam \i[0]_3~FF .CE_POLARITY = 1'b0;
    defparam \i[0]_3~FF .SR_POLARITY = 1'b0;
    defparam \i[0]_3~FF .D_POLARITY = 1'b1;
    defparam \i[0]_3~FF .SR_SYNC = 1'b0;
    defparam \i[0]_3~FF .SR_VALUE = 1'b0;
    defparam \i[0]_3~FF .SR_SYNC_PRIORITY = 1'b1;
    EFX_FF \resetMemclk~FF  (.D(stateMemclk), .CE(stateMemclk), .CLK(memclk), 
           .SR(aresetn), .Q(resetMemclk)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3681)
    defparam \resetMemclk~FF .CLK_POLARITY = 1'b1;
    defparam \resetMemclk~FF .CE_POLARITY = 1'b1;
    defparam \resetMemclk~FF .SR_POLARITY = 1'b0;
    defparam \resetMemclk~FF .D_POLARITY = 1'b1;
    defparam \resetMemclk~FF .SR_SYNC = 1'b0;
    defparam \resetMemclk~FF .SR_VALUE = 1'b1;
    defparam \resetMemclk~FF .SR_SYNC_PRIORITY = 1'b1;
    EFX_FF \statePixrxclk~FF  (.D(ceg_net8771), .CE(ceg_net10031), .CLK(pixrxclk), 
           .SR(aresetn), .Q(statePixrxclk)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3744)
    defparam \statePixrxclk~FF .CLK_POLARITY = 1'b1;
    defparam \statePixrxclk~FF .CE_POLARITY = 1'b0;
    defparam \statePixrxclk~FF .SR_POLARITY = 1'b0;
    defparam \statePixrxclk~FF .D_POLARITY = 1'b1;
    defparam \statePixrxclk~FF .SR_SYNC = 1'b0;
    defparam \statePixrxclk~FF .SR_VALUE = 1'b0;
    defparam \statePixrxclk~FF .SR_SYNC_PRIORITY = 1'b1;
    EFX_FF \i[0]~FF  (.D(n8923[0]), .CE(ceg_net10031), .CLK(pixrxclk), 
           .SR(aresetn), .Q(i[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3744)
    defparam \i[0]~FF .CLK_POLARITY = 1'b1;
    defparam \i[0]~FF .CE_POLARITY = 1'b0;
    defparam \i[0]~FF .SR_POLARITY = 1'b0;
    defparam \i[0]~FF .D_POLARITY = 1'b1;
    defparam \i[0]~FF .SR_SYNC = 1'b0;
    defparam \i[0]~FF .SR_VALUE = 1'b0;
    defparam \i[0]~FF .SR_SYNC_PRIORITY = 1'b1;
    EFX_FF \resetPixrxclk~FF  (.D(statePixrxclk), .CE(statePixrxclk), .CLK(pixrxclk), 
           .SR(aresetn), .Q(resetPixrxclk)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b1, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b1, SR_POLARITY=1'b0 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3744)
    defparam \resetPixrxclk~FF .CLK_POLARITY = 1'b1;
    defparam \resetPixrxclk~FF .CE_POLARITY = 1'b1;
    defparam \resetPixrxclk~FF .SR_POLARITY = 1'b0;
    defparam \resetPixrxclk~FF .D_POLARITY = 1'b1;
    defparam \resetPixrxclk~FF .SR_SYNC = 1'b0;
    defparam \resetPixrxclk~FF .SR_VALUE = 1'b1;
    defparam \resetPixrxclk~FF .SR_SYNC_PRIORITY = 1'b1;
    EFX_FF \i[1]_3~FF  (.D(n8868[1]), .CE(ceg_net8765), .CLK(memclk), 
           .SR(aresetn), .Q(i_3[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3681)
    defparam \i[1]_3~FF .CLK_POLARITY = 1'b1;
    defparam \i[1]_3~FF .CE_POLARITY = 1'b0;
    defparam \i[1]_3~FF .SR_POLARITY = 1'b0;
    defparam \i[1]_3~FF .D_POLARITY = 1'b1;
    defparam \i[1]_3~FF .SR_SYNC = 1'b0;
    defparam \i[1]_3~FF .SR_VALUE = 1'b0;
    defparam \i[1]_3~FF .SR_SYNC_PRIORITY = 1'b1;
    EFX_FF \i[2]_3~FF  (.D(n8868[2]), .CE(ceg_net8765), .CLK(memclk), 
           .SR(aresetn), .Q(i_3[2])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3681)
    defparam \i[2]_3~FF .CLK_POLARITY = 1'b1;
    defparam \i[2]_3~FF .CE_POLARITY = 1'b0;
    defparam \i[2]_3~FF .SR_POLARITY = 1'b0;
    defparam \i[2]_3~FF .D_POLARITY = 1'b1;
    defparam \i[2]_3~FF .SR_SYNC = 1'b0;
    defparam \i[2]_3~FF .SR_VALUE = 1'b0;
    defparam \i[2]_3~FF .SR_SYNC_PRIORITY = 1'b1;
    EFX_FF \i[3]_3~FF  (.D(n8868[3]), .CE(ceg_net8765), .CLK(memclk), 
           .SR(aresetn), .Q(i_3[3])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3681)
    defparam \i[3]_3~FF .CLK_POLARITY = 1'b1;
    defparam \i[3]_3~FF .CE_POLARITY = 1'b0;
    defparam \i[3]_3~FF .SR_POLARITY = 1'b0;
    defparam \i[3]_3~FF .D_POLARITY = 1'b1;
    defparam \i[3]_3~FF .SR_SYNC = 1'b0;
    defparam \i[3]_3~FF .SR_VALUE = 1'b0;
    defparam \i[3]_3~FF .SR_SYNC_PRIORITY = 1'b1;
    EFX_FF \i[4]~FF  (.D(n8868[4]), .CE(ceg_net8765), .CLK(memclk), .SR(aresetn), 
           .Q(i_3[4])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3681)
    defparam \i[4]~FF .CLK_POLARITY = 1'b1;
    defparam \i[4]~FF .CE_POLARITY = 1'b0;
    defparam \i[4]~FF .SR_POLARITY = 1'b0;
    defparam \i[4]~FF .D_POLARITY = 1'b1;
    defparam \i[4]~FF .SR_SYNC = 1'b0;
    defparam \i[4]~FF .SR_VALUE = 1'b0;
    defparam \i[4]~FF .SR_SYNC_PRIORITY = 1'b1;
    EFX_FF \i[1]~FF  (.D(n8923[1]), .CE(ceg_net10031), .CLK(pixrxclk), 
           .SR(aresetn), .Q(i[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3744)
    defparam \i[1]~FF .CLK_POLARITY = 1'b1;
    defparam \i[1]~FF .CE_POLARITY = 1'b0;
    defparam \i[1]~FF .SR_POLARITY = 1'b0;
    defparam \i[1]~FF .D_POLARITY = 1'b1;
    defparam \i[1]~FF .SR_SYNC = 1'b0;
    defparam \i[1]~FF .SR_VALUE = 1'b0;
    defparam \i[1]~FF .SR_SYNC_PRIORITY = 1'b1;
    EFX_FF \i[2]~FF  (.D(n8923[2]), .CE(ceg_net10031), .CLK(pixrxclk), 
           .SR(aresetn), .Q(i[2])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3744)
    defparam \i[2]~FF .CLK_POLARITY = 1'b1;
    defparam \i[2]~FF .CE_POLARITY = 1'b0;
    defparam \i[2]~FF .SR_POLARITY = 1'b0;
    defparam \i[2]~FF .D_POLARITY = 1'b1;
    defparam \i[2]~FF .SR_SYNC = 1'b0;
    defparam \i[2]~FF .SR_VALUE = 1'b0;
    defparam \i[2]~FF .SR_SYNC_PRIORITY = 1'b1;
    EFX_FF \i[3]~FF  (.D(n8923[3]), .CE(ceg_net10031), .CLK(pixrxclk), 
           .SR(aresetn), .Q(i[3])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_FF, CLK_POLARITY=1'b1, D_POLARITY=1'b1, CE_POLARITY=1'b0, SR_SYNC=1'b0, SR_SYNC_PRIORITY=1'b1, SR_VALUE=1'b0, SR_POLARITY=1'b0 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3744)
    defparam \i[3]~FF .CLK_POLARITY = 1'b1;
    defparam \i[3]~FF .CE_POLARITY = 1'b0;
    defparam \i[3]~FF .SR_POLARITY = 1'b0;
    defparam \i[3]~FF .D_POLARITY = 1'b1;
    defparam \i[3]~FF .SR_SYNC = 1'b0;
    defparam \i[3]~FF .SR_VALUE = 1'b0;
    defparam \i[3]~FF .SR_SYNC_PRIORITY = 1'b1;
    EFX_LUT4 LUT__3729 (.I0(stateMemclk), .I1(i_3[0]), .O(n8868[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3680)
    defparam LUT__3729.LUTMASK = 16'h1111;
    EFX_LUT4 LUT__3733 (.I0(i[1]), .I1(i[2]), .I2(i[0]), .I3(i[3]), 
            .O(n1420)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1000 */ ;
    defparam LUT__3733.LUTMASK = 16'h1000;
    EFX_LUT4 LUT__3734 (.I0(statePixrxclk), .I1(n1420), .O(ceg_net8771)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ;
    defparam LUT__3734.LUTMASK = 16'h4444;
    EFX_LUT4 LUT__3735 (.I0(n1420), .I1(statePixrxclk), .O(ceg_net10031)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h2222 */ ;
    defparam LUT__3735.LUTMASK = 16'h2222;
    EFX_LUT4 LUT__3736 (.I0(statePixrxclk), .I1(i[0]), .O(n8923[0])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1111 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3743)
    defparam LUT__3736.LUTMASK = 16'h1111;
    EFX_LUT4 LUT__3929 (.I0(stateMemclk), .I1(i_3[0]), .I2(i_3[1]), .O(n8868[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1414 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3680)
    defparam LUT__3929.LUTMASK = 16'h1414;
    EFX_LUT4 LUT__3930 (.I0(i_3[0]), .I1(i_3[1]), .I2(stateMemclk), .I3(i_3[2]), 
            .O(n8868[2])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0708 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3680)
    defparam LUT__3930.LUTMASK = 16'h0708;
    EFX_LUT4 LUT__3931 (.I0(i_3[0]), .I1(i_3[1]), .I2(i_3[2]), .O(n1526)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h8080 */ ;
    defparam LUT__3931.LUTMASK = 16'h8080;
    EFX_LUT4 LUT__3932 (.I0(stateMemclk), .I1(n1526), .I2(i_3[3]), .O(n8868[3])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1414 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3680)
    defparam LUT__3932.LUTMASK = 16'h1414;
    EFX_LUT4 LUT__3933 (.I0(n1526), .I1(i_3[3]), .I2(stateMemclk), .I3(i_3[4]), 
            .O(n8868[4])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0708 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3680)
    defparam LUT__3933.LUTMASK = 16'h0708;
    EFX_LUT4 LUT__3934 (.I0(statePixrxclk), .I1(i[0]), .I2(i[1]), .O(n8923[1])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h1414 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3743)
    defparam LUT__3934.LUTMASK = 16'h1414;
    EFX_LUT4 LUT__3935 (.I0(i[0]), .I1(i[1]), .I2(statePixrxclk), .I3(i[2]), 
            .O(n8923[2])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h0708 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3743)
    defparam LUT__3935.LUTMASK = 16'h0708;
    EFX_LUT4 LUT__3936 (.I0(i[0]), .I1(i[1]), .I2(i[2]), .I3(i[3]), 
            .O(n1527)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h7f80 */ ;
    defparam LUT__3936.LUTMASK = 16'h7f80;
    EFX_LUT4 LUT__3937 (.I0(statePixrxclk), .I1(n1527), .O(n8923[3])) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4444 */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3743)
    defparam LUT__3937.LUTMASK = 16'h4444;
    EFX_LUT4 LUT__4725 (.I0(resetMemclk), .O(resetnMemclk)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Vsp_core.vhd(3755)
    defparam LUT__4725.LUTMASK = 16'h5555;
    EFX_LUT4 LUT__4727 (.I0(resetPixrxclk), .O(mipirx_RST0_N)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h5555, EFX_ATTRIBUTE_INSTANCE__IS_LUT_SOP_INF_INV=TRUE */ ;   // /home/mpsitech/fpgacode/titdvk/vsp_core/Camif.vhd(1425)
    defparam LUT__4727.LUTMASK = 16'h5555;
    EFX_LUT4 LUT__3726 (.I0(i_3[3]), .I1(i_3[2]), .I2(i_3[0]), .I3(i_3[4]), 
            .O(n1419)) /* verific EFX_ATTRIBUTE_CELL_NAME=EFX_LUT4, LUTMASK=16'h4000 */ ;
    defparam LUT__3726.LUTMASK = 16'h4000;
    
endmodule

//
// Verific Verilog Description of module EFX_LUT4_ca1f36dd_0
// module not written out since it is a black box. 
//


//
// Verific Verilog Description of module EFX_FF_ca1f36dd_0
// module not written out since it is a black box. 
//


//
// Verific Verilog Description of module EFX_FF_ca1f36dd_1
// module not written out since it is a black box. 
//


//
// Verific Verilog Description of module EFX_LUT4_ca1f36dd_1
// module not written out since it is a black box. 
//


//
// Verific Verilog Description of module EFX_LUT4_ca1f36dd_2
// module not written out since it is a black box. 
//


//
// Verific Verilog Description of module EFX_LUT4_ca1f36dd_3
// module not written out since it is a black box. 
//


//
// Verific Verilog Description of module EFX_LUT4_ca1f36dd_4
// module not written out since it is a black box. 
//


//
// Verific Verilog Description of module EFX_LUT4_ca1f36dd_5
// module not written out since it is a black box. 
//


//
// Verific Verilog Description of module EFX_LUT4_ca1f36dd_6
// module not written out since it is a black box. 
//


//
// Verific Verilog Description of module EFX_LUT4_ca1f36dd_7
// module not written out since it is a black box. 
//


//
// Verific Verilog Description of module EFX_LUT4_ca1f36dd_8
// module not written out since it is a black box. 
//


//
// Verific Verilog Description of module EFX_LUT4_ca1f36dd_9
// module not written out since it is a black box. 
//


//
// Verific Verilog Description of module EFX_LUT4_ca1f36dd_10
// module not written out since it is a black box. 
//

