-- file Hostif.vhd
-- Hostif hostif_Easy_v1_0 easy model host interface implementation
-- copyright: (C) 2017-2024 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

-- module parameters:
-- phytype (axi/spi/uart): axi
-- wA (address width for AXI [bit]): 32
-- wD (data width 16/32/64/128 for AXI [bit]): 32
-- fSclk (baud rate for SPI/UART [bps]): 115200

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Hostif is
	generic (
		fMclk: natural := 50000
	);
	port (
		reset: in std_logic;
		mclk: in std_logic;
		tkclk: in std_logic;
		commok: out std_logic;
		reqReset: out std_logic;

		identGetUnt: in std_logic_vector(95 downto 0);
		identGetVer: in std_logic_vector(63 downto 0);
		identGetHash: in std_logic_vector(63 downto 0);
		identGetWho: in std_logic_vector(63 downto 0);

		identGetCfgFMclk: in std_logic_vector(31 downto 0);
		identGetCfgFMemclk: in std_logic_vector(31 downto 0);

		reqInvCamifConfig: out std_logic;
		ackInvCamifConfig: in std_logic;

		camifConfigHdrNotFix: out std_logic_vector(7 downto 0);
		camifConfigSynthNotLive: out std_logic_vector(7 downto 0);

		reqInvCamifConfigSynth: out std_logic;
		ackInvCamifConfigSynth: in std_logic;

		camifConfigSynthTixVSynthmode: out std_logic_vector(7 downto 0);
		camifConfigSynthTFramepad: out std_logic_vector(15 downto 0);
		camifConfigSynthTLinepad: out std_logic_vector(7 downto 0);

		reqInvCamifSetReg: out std_logic;
		ackInvCamifSetReg: in std_logic;

		camifSetRegAddr: out std_logic_vector(15 downto 0);
		camifSetRegVal: out std_logic_vector(7 downto 0);

		reqInvCamifGetReg: out std_logic;
		ackInvCamifGetReg: in std_logic;

		camifGetRegAddr: out std_logic_vector(15 downto 0);
		camifGetRegVal: in std_logic_vector(7 downto 0);

		reqInvCamifModReg: out std_logic;
		ackInvCamifModReg: in std_logic;

		camifModRegAddr: out std_logic_vector(15 downto 0);
		camifModRegMask: out std_logic_vector(7 downto 0);
		camifModRegVal: out std_logic_vector(7 downto 0);

		reqInvCamifSetCorereg: out std_logic;
		ackInvCamifSetCorereg: in std_logic;

		camifSetCoreregAddr: out std_logic_vector(7 downto 0);
		camifSetCoreregVal: out std_logic_vector(31 downto 0);

		reqInvCamifGetCorereg: out std_logic;
		ackInvCamifGetCorereg: in std_logic;

		camifGetCoreregAddr: out std_logic_vector(7 downto 0);
		camifGetCoreregVal: in std_logic_vector(31 downto 0);

		reqInvCornerAcquire: out std_logic;
		ackInvCornerAcquire: in std_logic;

		reqInvCornerConfig: out std_logic;
		ackInvCornerConfig: in std_logic;

		cornerConfigLinNotLog: out std_logic_vector(7 downto 0);
		cornerConfigThd: out std_logic_vector(7 downto 0);
		cornerConfigRow0: out std_logic_vector(15 downto 0);
		cornerConfigRow1: out std_logic_vector(15 downto 0);
		cornerConfigCol0: out std_logic_vector(15 downto 0);
		cornerConfigCol1: out std_logic_vector(15 downto 0);

		cornerGetInfoTixVState: in std_logic_vector(7 downto 0);
		cornerGetInfoTkst: in std_logic_vector(31 downto 0);
		cornerGetInfoScoreMin: in std_logic_vector(7 downto 0);
		cornerGetInfoScoreMax: in std_logic_vector(7 downto 0);

		reqInvCornerSet: out std_logic;
		ackInvCornerSet: in std_logic;

		cornerSetRng: out std_logic_vector(7 downto 0);

		reqInvCornerUnlock: out std_logic;
		ackInvCornerUnlock: in std_logic;

		ddrifGetStatsNRdA: in std_logic_vector(31 downto 0);
		ddrifGetStatsNRdB: in std_logic_vector(31 downto 0);
		ddrifGetStatsNWrA: in std_logic_vector(31 downto 0);
		ddrifGetStatsNWrB: in std_logic_vector(31 downto 0);

		reqInvDecimAcquire: out std_logic;
		ackInvDecimAcquire: in std_logic;

		decimAcquireIxTExp: out std_logic_vector(7 downto 0);

		reqInvDecimConfig: out std_logic;
		ackInvDecimConfig: in std_logic;

		decimConfigRgbNotGray: out std_logic_vector(7 downto 0);
		decimConfigEdge: out std_logic_vector(7 downto 0);
		decimConfigEdge2: out std_logic_vector(15 downto 0);
		decimConfigNDecim: out std_logic_vector(15 downto 0);

		decimGetInfoTixVState: in std_logic_vector(7 downto 0);
		decimGetInfoTkst: in std_logic_vector(31 downto 0);

		reqInvDecimSet: out std_logic;
		ackInvDecimSet: in std_logic;

		decimSetRng: out std_logic_vector(7 downto 0);

		reqInvDecimUnlock: out std_logic;
		ackInvDecimUnlock: in std_logic;

		reqInvDirectorConfig: out std_logic;
		ackInvDirectorConfig: in std_logic;

		directorConfigNRowRaw: out std_logic_vector(15 downto 0);
		directorConfigNColRaw: out std_logic_vector(15 downto 0);

		reqInvDirectorSet: out std_logic;
		ackInvDirectorSet: in std_logic;

		directorSetRng: out std_logic_vector(7 downto 0);

		reqInvHdrengAssign: out std_logic;
		ackInvHdrengAssign: in std_logic;

		hdrengAssignIxMem: out std_logic_vector(7 downto 0);

		hdrengGetInfoTixVState: in std_logic_vector(7 downto 0);
		hdrengGetInfoTkst: in std_logic_vector(31 downto 0);
		hdrengGetInfoIxMem: in std_logic_vector(7 downto 0);
		hdrengGetInfoIxMemAcq: in std_logic_vector(7 downto 0);

		reqInvHdrengSet: out std_logic;
		ackInvHdrengSet: in std_logic;

		hdrengSetRng: out std_logic_vector(7 downto 0);

		reqInvLaserSet: out std_logic;
		ackInvLaserSet: in std_logic;

		laserSetL: out std_logic_vector(15 downto 0);
		laserSetR: out std_logic_vector(15 downto 0);

		reqInvRotaryConfig: out std_logic;
		ackInvRotaryConfig: in std_logic;

		rotaryConfigTixVStepmode: out std_logic_vector(7 downto 0);
		rotaryConfigTStep: out std_logic_vector(7 downto 0);

		rotaryGetInfoTixVState: in std_logic_vector(7 downto 0);
		rotaryGetInfoAngle: in std_logic_vector(15 downto 0);

		reqInvRotaryMoveto: out std_logic;
		ackInvRotaryMoveto: in std_logic;

		rotaryMovetoAngle: out std_logic_vector(15 downto 0);

		reqInvRotarySet: out std_logic;
		ackInvRotarySet: in std_logic;

		rotarySetRng: out std_logic_vector(7 downto 0);
		rotarySetCcwNotCw: out std_logic_vector(7 downto 0);

		reqInvRotaryZero: out std_logic;
		ackInvRotaryZero: in std_logic;

		reqInvStepmuxSet: out std_logic;
		ackInvStepmuxSet: in std_logic;

		stepmuxSetLinNotRot: out std_logic_vector(7 downto 0);

		tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0);

		reqInvTkclksrcSetTkst: out std_logic;
		ackInvTkclksrcSetTkst: in std_logic;

		tkclksrcSetTkstTkst: out std_logic_vector(31 downto 0);

		reqInvTraceAcquire: out std_logic;
		ackInvTraceAcquire: in std_logic;

		reqInvTraceConfig: out std_logic;
		ackInvTraceConfig: in std_logic;

		traceConfigTixVOrient: out std_logic_vector(7 downto 0);
		traceConfigRow0: out std_logic_vector(15 downto 0);
		traceConfigCol0: out std_logic_vector(15 downto 0);

		traceGetInfoTixVState: in std_logic_vector(7 downto 0);
		traceGetInfoTkst: in std_logic_vector(31 downto 0);

		reqInvTraceUnlock: out std_logic;
		ackInvTraceUnlock: in std_logic;

		cputrackGetInfoTixVState: in std_logic_vector(7 downto 0);
		cputrackGetInfoTCapt: in std_logic_vector(31 downto 0);
		cputrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

		reqInvCputrackSelect: out std_logic;
		ackInvCputrackSelect: in std_logic;

		cputrackSelectTixVCapture: out std_logic_vector(7 downto 0);
		cputrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);
		cputrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);
		cputrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);
		cputrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

		reqInvCputrackSet: out std_logic;
		ackInvCputrackSet: in std_logic;

		cputrackSetRng: out std_logic_vector(7 downto 0);
		cputrackSetTCaptMax: out std_logic_vector(31 downto 0);

		reqInvHshktrackClearMask: out std_logic;
		ackInvHshktrackClearMask: in std_logic;

		hshktrackGetInfoTixVState: in std_logic_vector(7 downto 0);
		hshktrackGetInfoTCapt: in std_logic_vector(31 downto 0);
		hshktrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

		reqInvHshktrackSelect: out std_logic;
		ackInvHshktrackSelect: in std_logic;

		hshktrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);
		hshktrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);
		hshktrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);
		hshktrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

		reqInvHshktrackSet: out std_logic;
		ackInvHshktrackSet: in std_logic;

		hshktrackSetRng: out std_logic_vector(7 downto 0);
		hshktrackSetTCaptMax: out std_logic_vector(31 downto 0);

		reqInvHshktrackSetMask: out std_logic;
		ackInvHshktrackSetMask: in std_logic;

		hshktrackSetMaskTixVCapture: out std_logic_vector(7 downto 0);

		reqInvMemtrackClearMask: out std_logic;
		ackInvMemtrackClearMask: in std_logic;

		memtrackGetInfoTixVState: in std_logic_vector(7 downto 0);
		memtrackGetInfoTCapt: in std_logic_vector(31 downto 0);
		memtrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

		reqInvMemtrackSelect: out std_logic;
		ackInvMemtrackSelect: in std_logic;

		memtrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);
		memtrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);
		memtrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);
		memtrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

		reqInvMemtrackSet: out std_logic;
		ackInvMemtrackSet: in std_logic;

		memtrackSetRng: out std_logic_vector(7 downto 0);
		memtrackSetTCaptMax: out std_logic_vector(31 downto 0);

		reqInvMemtrackSetMask: out std_logic;
		ackInvMemtrackSetMask: in std_logic;

		memtrackSetMaskTixVCapture: out std_logic_vector(7 downto 0);

		vidtrackGetInfoTixVState: in std_logic_vector(7 downto 0);
		vidtrackGetInfoTCapt: in std_logic_vector(31 downto 0);
		vidtrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

		reqInvVidtrackSelect: out std_logic;
		ackInvVidtrackSelect: in std_logic;

		vidtrackSelectTixVCapture: out std_logic_vector(7 downto 0);
		vidtrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);
		vidtrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);
		vidtrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);
		vidtrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

		reqInvVidtrackSet: out std_logic;
		ackInvVidtrackSet: in std_logic;

		vidtrackSetRng: out std_logic_vector(7 downto 0);
		vidtrackSetTCaptMax: out std_logic_vector(31 downto 0);

		reqPvwbufFromDecim: out std_logic;
		ackPvwbufFromDecim: in std_logic;
		dnePvwbufFromDecim: out std_logic;
		avllenPvwbufFromDecim: in std_logic_vector(31 downto 0);

		pvwbufFromDecimAXIS_tready: out std_logic;
		pvwbufFromDecimAXIS_tvalid: in std_logic;
		pvwbufFromDecimAXIS_tdata: in std_logic_vector(31 downto 0);
		pvwbufFromDecimAXIS_tlast: in std_logic;

		reqCoobufFromCorner: out std_logic;
		ackCoobufFromCorner: in std_logic;
		dneCoobufFromCorner: out std_logic;
		avllenCoobufFromCorner: in std_logic_vector(31 downto 0);

		reqFlgbufFromTrace: out std_logic;
		ackFlgbufFromTrace: in std_logic;

		coobufFromCornerAXIS_tready: out std_logic;
		coobufFromCornerAXIS_tvalid: in std_logic;
		coobufFromCornerAXIS_tdata: in std_logic_vector(31 downto 0);
		coobufFromCornerAXIS_tlast: in std_logic;

		dneFlgbufFromTrace: out std_logic;
		avllenFlgbufFromTrace: in std_logic_vector(31 downto 0);

		flgbufFromTraceAXIS_tready: out std_logic;
		flgbufFromTraceAXIS_tvalid: in std_logic;
		flgbufFromTraceAXIS_tdata: in std_logic_vector(31 downto 0);
		flgbufFromTraceAXIS_tlast: in std_logic;

		reqSeqbufFromCputrack: out std_logic;
		ackSeqbufFromCputrack: in std_logic;
		dneSeqbufFromCputrack: out std_logic;
		avllenSeqbufFromCputrack: in std_logic_vector(31 downto 0);

		seqbufFromCputrackAXIS_tready: out std_logic;
		seqbufFromCputrackAXIS_tvalid: in std_logic;
		seqbufFromCputrackAXIS_tdata: in std_logic_vector(31 downto 0);
		seqbufFromCputrackAXIS_tlast: in std_logic;

		reqSeqbufFromHshktrack: out std_logic;
		ackSeqbufFromHshktrack: in std_logic;
		dneSeqbufFromHshktrack: out std_logic;
		avllenSeqbufFromHshktrack: in std_logic_vector(31 downto 0);

		reqSeqbufFromMemtrack: out std_logic;
		ackSeqbufFromMemtrack: in std_logic;
		dneSeqbufFromMemtrack: out std_logic;
		avllenSeqbufFromMemtrack: in std_logic_vector(31 downto 0);

		seqbufFromHshktrackAXIS_tready: out std_logic;
		seqbufFromHshktrackAXIS_tvalid: in std_logic;
		seqbufFromHshktrackAXIS_tdata: in std_logic_vector(31 downto 0);
		seqbufFromHshktrackAXIS_tlast: in std_logic;

		seqbufFromMemtrackAXIS_tready: out std_logic;

		reqSeqbufFromVidtrack: out std_logic;
		ackSeqbufFromVidtrack: in std_logic;
		dneSeqbufFromVidtrack: out std_logic;
		avllenSeqbufFromVidtrack: in std_logic_vector(31 downto 0);

		seqbufFromMemtrackAXIS_tvalid: in std_logic;
		seqbufFromMemtrackAXIS_tdata: in std_logic_vector(31 downto 0);
		seqbufFromMemtrackAXIS_tlast: in std_logic;

		seqbufFromVidtrackAXIS_tready: out std_logic;
		seqbufFromVidtrackAXIS_tvalid: in std_logic;
		seqbufFromVidtrackAXIS_tdata: in std_logic_vector(31 downto 0);
		seqbufFromVidtrackAXIS_tlast: in std_logic;

		AXIL_araddr: in std_logic_vector(31 downto 0);
		AXIL_arprot: in std_logic_vector(2 downto 0);
		AXIL_arready: out std_logic;
		AXIL_arvalid: in std_logic;
		AXIL_rdata: out std_logic_vector(31 downto 0);
		AXIL_rready: in std_logic;
		AXIL_rresp: out std_logic_vector(1 downto 0);
		AXIL_rvalid: out std_logic;
		AXIL_rlast: out std_logic;
		AXIL_awaddr: in std_logic_vector(31 downto 0);
		AXIL_awprot: in std_logic_vector(2 downto 0);
		AXIL_awready: out std_logic;
		AXIL_awvalid: in std_logic;
		AXIL_wdata: in std_logic_vector(31 downto 0);
		AXIL_wready: out std_logic;
		AXIL_wstrb: in std_logic_vector(3 downto 0);
		AXIL_wvalid: in std_logic;
		AXIL_bready: in std_logic;
		AXIL_bresp: out std_logic_vector(1 downto 0);
		AXIL_bvalid: out std_logic;

		stateOp_dbg: out std_logic_vector(7 downto 0)
	);
end Hostif;

architecture Rtl of Hostif is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Axislave_v1_0 is
		generic (
			fMclk: natural := 50000;

			wA: natural := 32;
			wD: natural := 32
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;

			req: in std_logic;
			ack: out std_logic;
			dne: out std_logic;

			sendNotRecv: in std_logic;
			len: in std_logic_vector(31 downto 0);

			recvAXIS_tready: in std_logic;
			recvAXIS_tvalid: out std_logic;
			recvAXIS_tdata: out std_logic_vector(wD-1 downto 0);
			recvAXIS_tlast: out std_logic;

			sendAXIS_tready: out std_logic;
			sendAXIS_tvalid: in std_logic;
			sendAXIS_tdata: in std_logic_vector(wD-1 downto 0);
			sendAXIS_tlast: in std_logic;

			AXIL_araddr: in std_logic_vector(wA-1 downto 0);
			AXIL_arprot: in std_logic_vector(2 downto 0);
			AXIL_arready: out std_logic;
			AXIL_arvalid: in std_logic;

			AXIL_rdata: out std_logic_vector(wD-1 downto 0);
			AXIL_rready: in std_logic;
			AXIL_rresp: out std_logic_vector(1 downto 0);
			AXIL_rvalid: out std_logic;
			AXIL_rlast: out std_logic;

			AXIL_awaddr: in std_logic_vector(wA-1 downto 0);
			AXIL_awprot: in std_logic_vector(2 downto 0);
			AXIL_awready: out std_logic;
			AXIL_awvalid: in std_logic;

			AXIL_wdata: in std_logic_vector(wD-1 downto 0);
			AXIL_wready: out std_logic;
			AXIL_wstrb: in std_logic_vector(wD/8-1 downto 0);
			AXIL_wvalid: in std_logic;

			AXIL_bready: in std_logic;
			AXIL_bresp: out std_logic_vector(1 downto 0);
			AXIL_bvalid: out std_logic
		);
	end component;

	component Crc8005_32 is
		generic (
			initInvert: boolean := false;
			byteFlip: boolean := false;
			outFlip: boolean := false;
			outInvert: boolean := false
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;

			AXIS_tready: out std_logic;
			AXIS_tvalid: in std_logic;
			AXIS_tdata: in std_logic_vector(31 downto 0);
			AXIS_tkeep: in std_logic_vector(3 downto 0);
			AXIS_tlast: in std_logic;

			crc: out std_logic_vector(15 downto 0);
			validCrc: out std_logic
		);
	end component;

	component Timeout_v1_0 is
		generic (
			twait: natural range 1 to 10000 := 100
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;
			tkclk: in std_logic;

			restart: in std_logic;
			timeout: out std_logic
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	constant wD: natural := 32;

	--- main operation
	type stateOp_t is (
		stateOpInit,
		stateOpIdle,
		stateOpRxopA, stateOpRxopB, stateOpRxopC, stateOpRxopD, stateOpRxopE,
		stateOpTxpollA, stateOpTxpollB, stateOpTxpollC, stateOpTxpollD, stateOpTxpollE, stateOpTxpollF, stateOpTxpollG,
		stateOpTxA, stateOpTxE, stateOpTxB, stateOpTxC, stateOpTxD, stateOpTxF, stateOpTxG,
		stateOpTxbufA, stateOpTxbufB, stateOpTxbufC, stateOpTxbufD, stateOpTxbufE, stateOpTxbufF, stateOpTxbufG, stateOpTxbufH,
		stateOpRxA, stateOpRxB, stateOpRxC, stateOpRxD,
		stateOpRxbufA, stateOpRxbufB, stateOpRxbufC, stateOpRxbufD, stateOpRxbufE, stateOpRxbufF,
		stateOpInv
	);
	signal stateOp: stateOp_t;

	constant sizeOpbuf: natural := 12;
	constant opbufLastAXIS_tkeep: std_logic_vector(wD/8-1 downto 0) := "0001";
	type opbuf_t is array (0 to sizeOpbuf-1) of std_logic_vector(7 downto 0);
	signal opbuf: opbuf_t;

	signal txNotRx: std_logic;

	signal reqRxtx: std_logic;
	signal ackRxtx: std_logic;
	signal dneRxtx: std_logic;

	signal rxtxlen: std_logic_vector(31 downto 0);

	signal tixVBuffer: std_logic_vector(7 downto 0);
	signal tixVController: std_logic_vector(7 downto 0); -- cmd
	signal tixVCommand: std_logic_vector(7 downto 0); -- cmd
	signal tixVBufxfop: std_logic_vector(7 downto 0); -- bufxf

	constant sizePollbuf: natural := 8;
	constant pollbufLastAXIS_tkeep: std_logic_vector(wD/8-1 downto 0) := "1111";
	type pollbuf_t is array (0 to sizePollbuf-1) of std_logic_vector(7 downto 0);
	signal pollbuf: pollbuf_t;

	constant sizeInvbuf: natural := 12; -- should include CRC
	type invbuf_t is array (0 to sizeInvbuf-1) of std_logic_vector(7 downto 0);
	signal invbuf: invbuf_t;

	constant sizeRetbuf: natural := 40; -- should include CRC
	type retbuf_t is array (0 to sizeRetbuf-1) of std_logic_vector(7 downto 0);
	signal retbuf: retbuf_t;

	signal commok_sig: std_logic;
	signal reqReset_sig: std_logic;

	signal cmdvalid: std_logic;

	signal lenRet: std_logic_vector(15 downto 0);

	signal lenInv: std_logic_vector(15 downto 0);

	signal reqInv: std_logic;
	signal ackInv: std_logic;

	signal txbufvalid: std_logic;

	signal reqTxbuf: std_logic;
	signal ackTxbuf: std_logic;
	signal dneTxbuf: std_logic;

	signal avllenTxbuf: std_logic_vector(31 downto 0);

	signal txbufAXIS_tready: std_logic;
	signal txbufAXIS_tvalid: std_logic;
	signal txbufAXIS_tdata: std_logic_vector(wD-1 downto 0);
	signal txbufAXIS_tlast: std_logic;

	signal rxbufvalid: std_logic;

	signal reqRxbuf: std_logic;
	signal ackRxbuf: std_logic;
	signal dneRxbuf: std_logic;

	signal avllenRxbuf: std_logic_vector(31 downto 0);

	signal rxbufAXIS_tready: std_logic;
	signal rxbufAXIS_tvalid: std_logic;
	signal rxbufAXIS_tdata: std_logic_vector(wD-1 downto 0);
	signal rxbufAXIS_tlast: std_logic;

	signal rxbuflast: std_logic;

	signal crcAXIS_tdata: std_logic_vector(wD-1 downto 0);
	signal crcAXIS_tkeep: std_logic_vector(wD/8-1 downto 0);
	signal crcAXIS_tlast: std_logic;
	signal crcAXIS_tlast_sig: std_logic;

	signal rxlen: std_logic_vector(31 downto 0);

	signal txlen: std_logic_vector(31 downto 0);

	signal txAXIS_tdata: std_logic_vector(wD-1 downto 0);
	signal txAXIS_tlast: std_logic;

	signal txlast: std_logic;

	signal restartWordto: std_logic;
	signal restartXferto: std_logic;

	---- myCrc
	signal crc: std_logic_vector(15 downto 0);
	signal validCrc: std_logic;

	---- myRx
	signal rxAXIS_tdata: std_logic_vector(wD-1 downto 0);
	signal rxAXIS_tlast: std_logic;

	---- myWordto
	signal wordto: std_logic;

	---- myXferto
	signal xferto: std_logic;

	---- handshake
	-- op to myCrc
	signal crcAXIS_tready: std_logic;
	signal crcAXIS_tvalid: std_logic;

	-- op to myRx
	signal reqRx: std_logic;
	signal ackRx: std_logic;
	signal dneRx: std_logic;

	signal rxAXIS_tready: std_logic;
	signal rxAXIS_tvalid: std_logic;

	-- op to myTx
	signal reqTx: std_logic;
	signal ackTx: std_logic;
	signal dneTx: std_logic;

	signal txAXIS_tready: std_logic;
	signal txAXIS_tvalid: std_logic;

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myCrc : Crc8005_32
		port map (
			reset => reset,
			mclk => mclk,

			AXIS_tready => crcAXIS_tready,
			AXIS_tvalid => crcAXIS_tvalid,
			AXIS_tdata => crcAXIS_tdata,
			AXIS_tkeep => crcAXIS_tkeep,
			AXIS_tlast => crcAXIS_tlast,

			crc => crc,
			validCrc => validCrc
		);

	myRxtx : Axislave_v1_0
		generic map (
			fMclk => fMclk,

			wA => 32,
			wD => 32
		)
		port map(
			reset => reset,
			mclk => mclk,

			req => reqRxtx,
			ack => ackRxtx,
			dne => dneRxtx,

			sendNotRecv => txNotRx,
			len => rxtxlen,

			recvAXIS_tready => rxAXIS_tready,
			recvAXIS_tvalid => rxAXIS_tvalid,
			recvAXIS_tdata => rxAXIS_tdata,
			recvAXIS_tlast => rxAXIS_tlast,

			sendAXIS_tready => txAXIS_tready,
			sendAXIS_tvalid => txAXIS_tvalid,
			sendAXIS_tdata => txAXIS_tdata,
			sendAXIS_tlast => txAXIS_tlast,

			AXIL_araddr => AXIL_araddr,
			AXIL_arprot => AXIL_arprot,
			AXIL_arready => AXIL_arready,
			AXIL_arvalid => AXIL_arvalid,

			AXIL_rdata => AXIL_rdata,
			AXIL_rready => AXIL_rready,
			AXIL_rresp => AXIL_rresp,
			AXIL_rvalid => AXIL_rvalid,
			AXIL_rlast => AXIL_rlast,

			AXIL_awaddr => AXIL_awaddr,
			AXIL_awprot => AXIL_awprot,
			AXIL_awready => AXIL_awready,
			AXIL_awvalid => AXIL_awvalid,

			AXIL_wdata => AXIL_wdata,
			AXIL_wready => AXIL_wready,
			AXIL_wstrb => AXIL_wstrb,
			AXIL_wvalid => AXIL_wvalid,

			AXIL_bready => AXIL_bready,
			AXIL_bresp => AXIL_bresp,
			AXIL_bvalid => AXIL_bvalid
		);

	myWordto : Timeout_v1_0
		generic map (
			twait => 100
		)
		port map (
			reset => reset,
			mclk => mclk,
			tkclk => tkclk,

			restart => restartWordto,
			timeout => wordto
		);

	myXferto : Timeout_v1_0
		generic map (
			twait => 1000
		)
		port map (
			reset => reset,
			mclk => mclk,
			tkclk => tkclk,

			restart => restartXferto,
			timeout => xferto
		);

	------------------------------------------------------------------------
	-- implementation: main operation 
	------------------------------------------------------------------------

	commok <= commok_sig;
	reqReset <= reqReset_sig;

	txNotRx <= '1' when stateOp=stateOpRxopE
				or stateOp=stateOpTxpollA or stateOp=stateOpTxpollE or stateOp=stateOpTxpollB or stateOp=stateOpTxpollC or stateOp=stateOpTxpollD or stateOp=stateOpTxpollF
				or stateOp=stateOpTxA or stateOp=stateOpTxE or stateOp=stateOpTxB or stateOp=stateOpTxC or stateOp=stateOpTxD or stateOp=stateOpTxF
				or stateOp=stateOpTxbufA or stateOp=stateOpTxbufB or stateOp=stateOpTxbufC or stateOp=stateOpTxbufD or stateOp=stateOpTxbufE or stateOp=stateOpTxbufF
				or stateOp=stateOpRxD
				or stateOp=stateOpRxbufE or stateOp=stateOpRxbufF
				else '0';

	reqRxtx <= reqRx when txNotRx='0' else reqTx;

	ackRx <= ackRxtx when txNotRx='0' else '0';
	ackTx <= ackRxtx when txNotRx='1' else '0';

	dneRx <= dneRxtx when txNotRx='0' else '0';
	dneTx <= dneRxtx when txNotRx='1' else '0';

	rxtxlen <= rxlen when txNotRx='0' else txlen;

	-- command
	cmdvalid <= '1' when ( (tixVController=tixVTivspControllerHostif and tixVCommand=x"00")
				or (tixVController=tixVTivspControllerIdent and (tixVCommand=tixVIdentCommandGet or tixVCommand=tixVIdentCommandGetCfg))
				or (tixVController=tixVTivspControllerCamif and (tixVCommand=tixVCamifCommandConfig or tixVCommand=tixVCamifCommandConfigSynth or tixVCommand=tixVCamifCommandSetReg or tixVCommand=tixVCamifCommandGetReg or tixVCommand=tixVCamifCommandModReg or tixVCommand=tixVCamifCommandSetCorereg or tixVCommand=tixVCamifCommandGetCorereg))
				or (tixVController=tixVTivspControllerCorner and (tixVCommand=tixVCornerCommandAcquire or tixVCommand=tixVCornerCommandConfig or tixVCommand=tixVCornerCommandGetInfo or tixVCommand=tixVCornerCommandSet or tixVCommand=tixVCornerCommandUnlock))
				or (tixVController=tixVTivspControllerDdrif and tixVCommand=tixVDdrifCommandGetStats)
				or (tixVController=tixVTivspControllerDecim and (tixVCommand=tixVDecimCommandAcquire or tixVCommand=tixVDecimCommandConfig or tixVCommand=tixVDecimCommandGetInfo or tixVCommand=tixVDecimCommandSet or tixVCommand=tixVDecimCommandUnlock))
				or (tixVController=tixVTivspControllerDirector and (tixVCommand=tixVDirectorCommandConfig or tixVCommand=tixVDirectorCommandSet))
				or (tixVController=tixVTivspControllerHdreng and (tixVCommand=tixVHdrengCommandAssign or tixVCommand=tixVHdrengCommandGetInfo or tixVCommand=tixVHdrengCommandSet))
				or (tixVController=tixVTivspControllerLaser and tixVCommand=tixVLaserCommandSet)
				or (tixVController=tixVTivspControllerRotary and (tixVCommand=tixVRotaryCommandConfig or tixVCommand=tixVRotaryCommandGetInfo or tixVCommand=tixVRotaryCommandMoveto or tixVCommand=tixVRotaryCommandSet or tixVCommand=tixVRotaryCommandZero))
				or (tixVController=tixVTivspControllerStepmux and tixVCommand=tixVStepmuxCommandSet)
				or (tixVController=tixVTivspControllerTkclksrc and (tixVCommand=tixVTkclksrcCommandGetTkst or tixVCommand=tixVTkclksrcCommandSetTkst))
				or (tixVController=tixVTivspControllerTrace and (tixVCommand=tixVTraceCommandAcquire or tixVCommand=tixVTraceCommandConfig or tixVCommand=tixVTraceCommandGetInfo or tixVCommand=tixVTraceCommandUnlock))
				or (tixVController=tixVTivspControllerCputrack and (tixVCommand=tixVCputrackCommandGetInfo or tixVCommand=tixVCputrackCommandSelect or tixVCommand=tixVCputrackCommandSet))
				or (tixVController=tixVTivspControllerHshktrack and (tixVCommand=tixVHshktrackCommandClearMask or tixVCommand=tixVHshktrackCommandGetInfo or tixVCommand=tixVHshktrackCommandSelect or tixVCommand=tixVHshktrackCommandSet or tixVCommand=tixVHshktrackCommandSetMask))
				or (tixVController=tixVTivspControllerMemtrack and (tixVCommand=tixVMemtrackCommandClearMask or tixVCommand=tixVMemtrackCommandGetInfo or tixVCommand=tixVMemtrackCommandSelect or tixVCommand=tixVMemtrackCommandSet or tixVCommand=tixVMemtrackCommandSetMask))
				or (tixVController=tixVTivspControllerVidtrack and (tixVCommand=tixVVidtrackCommandGetInfo or tixVCommand=tixVVidtrackCommandSelect or tixVCommand=tixVVidtrackCommandSet))
				) else '0';

	-- tx/ret command
	lenRet <= x"0024" when (tixVController=tixVTivspControllerIdent and tixVCommand=tixVIdentCommandGet)
				else x"0008" when (tixVController=tixVTivspControllerIdent and tixVCommand=tixVIdentCommandGetCfg)
				else x"0001" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetReg)
				else x"0004" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetCorereg)
				else x"0007" when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandGetInfo)
				else x"0010" when (tixVController=tixVTivspControllerDdrif and tixVCommand=tixVDdrifCommandGetStats)
				else x"0005" when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandGetInfo)
				else x"0007" when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandGetInfo)
				else x"0003" when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandGetInfo)
				else x"0004" when (tixVController=tixVTivspControllerTkclksrc and tixVCommand=tixVTkclksrcCommandGetTkst)
				else x"0005" when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandGetInfo)
				else x"0007" when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandGetInfo)
				else x"0007" when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandGetInfo)
				else x"0007" when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandGetInfo)
				else x"0007" when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandGetInfo)
				else (others => '0');

	-- rx/inv command
	lenInv <= x"0002" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandConfig)
				else x"0004" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandConfigSynth)
				else x"0003" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandSetReg)
				else x"0002" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetReg)
				else x"0004" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandModReg)
				else x"0005" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandSetCorereg)
				else x"0001" when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetCorereg)
				else x"000A" when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandConfig)
				else x"0001" when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandSet)
				else x"0001" when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandAcquire)
				else x"0006" when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandConfig)
				else x"0001" when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandSet)
				else x"0004" when (tixVController=tixVTivspControllerDirector and tixVCommand=tixVDirectorCommandConfig)
				else x"0001" when (tixVController=tixVTivspControllerDirector and tixVCommand=tixVDirectorCommandSet)
				else x"0001" when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandAssign)
				else x"0001" when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandSet)
				else x"0004" when (tixVController=tixVTivspControllerLaser and tixVCommand=tixVLaserCommandSet)
				else x"0002" when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandConfig)
				else x"0002" when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandMoveto)
				else x"0002" when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandSet)
				else x"0001" when (tixVController=tixVTivspControllerStepmux and tixVCommand=tixVStepmuxCommandSet)
				else x"0004" when (tixVController=tixVTivspControllerTkclksrc and tixVCommand=tixVTkclksrcCommandSetTkst)
				else x"0005" when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandConfig)
				else x"0005" when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandSelect)
				else x"0005" when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandSet)
				else x"0004" when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSelect)
				else x"0005" when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSet)
				else x"0001" when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSetMask)
				else x"0004" when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSelect)
				else x"0005" when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSet)
				else x"0001" when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSetMask)
				else x"0005" when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandSelect)
				else x"0005" when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandSet)
				else (others => '0');

	reqInv <= '1' when stateOp=stateOpInv else '0';

	reqInvCamifConfig <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandConfig) else '0';
	camifConfigHdrNotFix <= invbuf(0);
	camifConfigSynthNotLive <= invbuf(1);

	reqInvCamifConfigSynth <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandConfigSynth) else '0';
	camifConfigSynthTixVSynthmode <= invbuf(0);
	camifConfigSynthTFramepad <= invbuf(1) & invbuf(2);
	camifConfigSynthTLinepad <= invbuf(3);

	reqInvCamifSetReg <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandSetReg) else '0';
	camifSetRegAddr <= invbuf(0) & invbuf(1);
	camifSetRegVal <= invbuf(2);

	reqInvCamifGetReg <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetReg) else '0';
	camifGetRegAddr <= invbuf(0) & invbuf(1);

	reqInvCamifModReg <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandModReg) else '0';
	camifModRegAddr <= invbuf(0) & invbuf(1);
	camifModRegMask <= invbuf(2);
	camifModRegVal <= invbuf(3);

	reqInvCamifSetCorereg <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandSetCorereg) else '0';
	camifSetCoreregAddr <= invbuf(0);
	camifSetCoreregVal <= invbuf(1) & invbuf(2) & invbuf(3) & invbuf(4);

	reqInvCamifGetCorereg <= reqInv when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetCorereg) else '0';
	camifGetCoreregAddr <= invbuf(0);

	reqInvCornerAcquire <= reqInv when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandAcquire) else '0';

	reqInvCornerConfig <= reqInv when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandConfig) else '0';
	cornerConfigLinNotLog <= invbuf(0);
	cornerConfigThd <= invbuf(1);
	cornerConfigRow0 <= invbuf(2) & invbuf(3);
	cornerConfigRow1 <= invbuf(4) & invbuf(5);
	cornerConfigCol0 <= invbuf(6) & invbuf(7);
	cornerConfigCol1 <= invbuf(8) & invbuf(9);

	reqInvCornerSet <= reqInv when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandSet) else '0';
	cornerSetRng <= invbuf(0);

	reqInvCornerUnlock <= reqInv when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandUnlock) else '0';

	reqInvDecimAcquire <= reqInv when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandAcquire) else '0';
	decimAcquireIxTExp <= invbuf(0);

	reqInvDecimConfig <= reqInv when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandConfig) else '0';
	decimConfigRgbNotGray <= invbuf(0);
	decimConfigEdge <= invbuf(1);
	decimConfigEdge2 <= invbuf(2) & invbuf(3);
	decimConfigNDecim <= invbuf(4) & invbuf(5);

	reqInvDecimSet <= reqInv when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandSet) else '0';
	decimSetRng <= invbuf(0);

	reqInvDecimUnlock <= reqInv when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandUnlock) else '0';

	reqInvDirectorConfig <= reqInv when (tixVController=tixVTivspControllerDirector and tixVCommand=tixVDirectorCommandConfig) else '0';
	directorConfigNRowRaw <= invbuf(0) & invbuf(1);
	directorConfigNColRaw <= invbuf(2) & invbuf(3);

	reqInvDirectorSet <= reqInv when (tixVController=tixVTivspControllerDirector and tixVCommand=tixVDirectorCommandSet) else '0';
	directorSetRng <= invbuf(0);

	reqInvHdrengAssign <= reqInv when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandAssign) else '0';
	hdrengAssignIxMem <= invbuf(0);

	reqInvHdrengSet <= reqInv when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandSet) else '0';
	hdrengSetRng <= invbuf(0);

	reqInvLaserSet <= reqInv when (tixVController=tixVTivspControllerLaser and tixVCommand=tixVLaserCommandSet) else '0';
	laserSetL <= invbuf(0) & invbuf(1);
	laserSetR <= invbuf(2) & invbuf(3);

	reqInvRotaryConfig <= reqInv when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandConfig) else '0';
	rotaryConfigTixVStepmode <= invbuf(0);
	rotaryConfigTStep <= invbuf(1);

	reqInvRotaryMoveto <= reqInv when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandMoveto) else '0';
	rotaryMovetoAngle <= invbuf(0) & invbuf(1);

	reqInvRotarySet <= reqInv when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandSet) else '0';
	rotarySetRng <= invbuf(0);
	rotarySetCcwNotCw <= invbuf(1);

	reqInvRotaryZero <= reqInv when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandZero) else '0';

	reqInvStepmuxSet <= reqInv when (tixVController=tixVTivspControllerStepmux and tixVCommand=tixVStepmuxCommandSet) else '0';
	stepmuxSetLinNotRot <= invbuf(0);

	reqInvTkclksrcSetTkst <= reqInv when (tixVController=tixVTivspControllerTkclksrc and tixVCommand=tixVTkclksrcCommandSetTkst) else '0';
	tkclksrcSetTkstTkst <= invbuf(0) & invbuf(1) & invbuf(2) & invbuf(3);

	reqInvTraceAcquire <= reqInv when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandAcquire) else '0';

	reqInvTraceConfig <= reqInv when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandConfig) else '0';
	traceConfigTixVOrient <= invbuf(0);
	traceConfigRow0 <= invbuf(1) & invbuf(2);
	traceConfigCol0 <= invbuf(3) & invbuf(4);

	reqInvTraceUnlock <= reqInv when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandUnlock) else '0';

	reqInvCputrackSelect <= reqInv when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandSelect) else '0';
	cputrackSelectTixVCapture <= invbuf(0);
	cputrackSelectStaTixVTrigger <= invbuf(1);
	cputrackSelectStaFallingNotRising <= invbuf(2);
	cputrackSelectStoTixVTrigger <= invbuf(3);
	cputrackSelectStoFallingNotRising <= invbuf(4);

	reqInvCputrackSet <= reqInv when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandSet) else '0';
	cputrackSetRng <= invbuf(0);
	cputrackSetTCaptMax <= invbuf(1) & invbuf(2) & invbuf(3) & invbuf(4);

	reqInvHshktrackClearMask <= reqInv when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandClearMask) else '0';

	reqInvHshktrackSelect <= reqInv when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSelect) else '0';
	hshktrackSelectStaTixVTrigger <= invbuf(0);
	hshktrackSelectStaFallingNotRising <= invbuf(1);
	hshktrackSelectStoTixVTrigger <= invbuf(2);
	hshktrackSelectStoFallingNotRising <= invbuf(3);

	reqInvHshktrackSet <= reqInv when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSet) else '0';
	hshktrackSetRng <= invbuf(0);
	hshktrackSetTCaptMax <= invbuf(1) & invbuf(2) & invbuf(3) & invbuf(4);

	reqInvHshktrackSetMask <= reqInv when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSetMask) else '0';
	hshktrackSetMaskTixVCapture <= invbuf(0);

	reqInvMemtrackClearMask <= reqInv when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandClearMask) else '0';

	reqInvMemtrackSelect <= reqInv when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSelect) else '0';
	memtrackSelectStaTixVTrigger <= invbuf(0);
	memtrackSelectStaFallingNotRising <= invbuf(1);
	memtrackSelectStoTixVTrigger <= invbuf(2);
	memtrackSelectStoFallingNotRising <= invbuf(3);

	reqInvMemtrackSet <= reqInv when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSet) else '0';
	memtrackSetRng <= invbuf(0);
	memtrackSetTCaptMax <= invbuf(1) & invbuf(2) & invbuf(3) & invbuf(4);

	reqInvMemtrackSetMask <= reqInv when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSetMask) else '0';
	memtrackSetMaskTixVCapture <= invbuf(0);

	reqInvVidtrackSelect <= reqInv when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandSelect) else '0';
	vidtrackSelectTixVCapture <= invbuf(0);
	vidtrackSelectStaTixVTrigger <= invbuf(1);
	vidtrackSelectStaFallingNotRising <= invbuf(2);
	vidtrackSelectStoTixVTrigger <= invbuf(3);
	vidtrackSelectStoFallingNotRising <= invbuf(4);

	reqInvVidtrackSet <= reqInv when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandSet) else '0';
	vidtrackSetRng <= invbuf(0);
	vidtrackSetTCaptMax <= invbuf(1) & invbuf(2) & invbuf(3) & invbuf(4);

	ackInv <= ackInvCamifConfig when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandConfig)
				else ackInvCamifConfigSynth when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandConfigSynth)
				else ackInvCamifSetReg when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandSetReg)
				else ackInvCamifGetReg when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetReg)
				else ackInvCamifModReg when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandModReg)
				else ackInvCamifSetCorereg when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandSetCorereg)
				else ackInvCamifGetCorereg when (tixVController=tixVTivspControllerCamif and tixVCommand=tixVCamifCommandGetCorereg)
				else ackInvCornerAcquire when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandAcquire)
				else ackInvCornerConfig when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandConfig)
				else ackInvCornerSet when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandSet)
				else ackInvCornerUnlock when (tixVController=tixVTivspControllerCorner and tixVCommand=tixVCornerCommandUnlock)
				else ackInvDecimAcquire when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandAcquire)
				else ackInvDecimConfig when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandConfig)
				else ackInvDecimSet when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandSet)
				else ackInvDecimUnlock when (tixVController=tixVTivspControllerDecim and tixVCommand=tixVDecimCommandUnlock)
				else ackInvDirectorConfig when (tixVController=tixVTivspControllerDirector and tixVCommand=tixVDirectorCommandConfig)
				else ackInvDirectorSet when (tixVController=tixVTivspControllerDirector and tixVCommand=tixVDirectorCommandSet)
				else ackInvHdrengAssign when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandAssign)
				else ackInvHdrengSet when (tixVController=tixVTivspControllerHdreng and tixVCommand=tixVHdrengCommandSet)
				else ackInvLaserSet when (tixVController=tixVTivspControllerLaser and tixVCommand=tixVLaserCommandSet)
				else ackInvRotaryConfig when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandConfig)
				else ackInvRotaryMoveto when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandMoveto)
				else ackInvRotarySet when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandSet)
				else ackInvRotaryZero when (tixVController=tixVTivspControllerRotary and tixVCommand=tixVRotaryCommandZero)
				else ackInvStepmuxSet when (tixVController=tixVTivspControllerStepmux and tixVCommand=tixVStepmuxCommandSet)
				else ackInvTkclksrcSetTkst when (tixVController=tixVTivspControllerTkclksrc and tixVCommand=tixVTkclksrcCommandSetTkst)
				else ackInvTraceAcquire when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandAcquire)
				else ackInvTraceConfig when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandConfig)
				else ackInvTraceUnlock when (tixVController=tixVTivspControllerTrace and tixVCommand=tixVTraceCommandUnlock)
				else ackInvCputrackSelect when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandSelect)
				else ackInvCputrackSet when (tixVController=tixVTivspControllerCputrack and tixVCommand=tixVCputrackCommandSet)
				else ackInvHshktrackClearMask when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandClearMask)
				else ackInvHshktrackSelect when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSelect)
				else ackInvHshktrackSet when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSet)
				else ackInvHshktrackSetMask when (tixVController=tixVTivspControllerHshktrack and tixVCommand=tixVHshktrackCommandSetMask)
				else ackInvMemtrackClearMask when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandClearMask)
				else ackInvMemtrackSelect when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSelect)
				else ackInvMemtrackSet when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSet)
				else ackInvMemtrackSetMask when (tixVController=tixVTivspControllerMemtrack and tixVCommand=tixVMemtrackCommandSetMask)
				else ackInvVidtrackSelect when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandSelect)
				else ackInvVidtrackSet when (tixVController=tixVTivspControllerVidtrack and tixVCommand=tixVVidtrackCommandSet)
				else '1';

	-- tx buffer
	txbufvalid <= '1' when tixVBuffer=tixVTivspBufferCoobufCornerToHostif or tixVBuffer=tixVTivspBufferFlgbufTraceToHostif or tixVBuffer=tixVTivspBufferPvwbufDecimToHostif or tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif or tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif or tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif or tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif else '0';

	reqTxbuf <= '1' when stateOp=stateOpTxbufA or stateOp=stateOpTxbufB or stateOp=stateOpTxbufC or stateOp=stateOpTxbufD or stateOp=stateOpTxbufE or stateOp=stateOpTxbufF or stateOp=stateOpTxbufG or stateOp=stateOpTxbufH else '0';

	reqCoobufFromCorner <= reqTxbuf when tixVBuffer=tixVTivspBufferCoobufCornerToHostif else '0';
	reqFlgbufFromTrace <= reqTxbuf when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif else '0';
	reqPvwbufFromDecim <= reqTxbuf when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif else '0';
	reqSeqbufFromMemtrack <= reqTxbuf when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif else '0';
	reqSeqbufFromCputrack <= reqTxbuf when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif else '0';
	reqSeqbufFromVidtrack <= reqTxbuf when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif else '0';
	reqSeqbufFromHshktrack <= reqTxbuf when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif else '0';

	ackTxbuf <= ackCoobufFromCorner when tixVBuffer=tixVTivspBufferCoobufCornerToHostif
				else ackFlgbufFromTrace when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif
				else ackPvwbufFromDecim when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif
				else ackSeqbufFromMemtrack when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif
				else ackSeqbufFromCputrack when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif
				else ackSeqbufFromVidtrack when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif
				else ackSeqbufFromHshktrack when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif
				else '0';

	dneTxbuf <= '1' when stateOp=stateOpTxbufE else '0';

	dneCoobufFromCorner <= dneTxbuf when tixVBuffer=tixVTivspBufferCoobufCornerToHostif else '0';
	dneFlgbufFromTrace <= dneTxbuf when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif else '0';
	dnePvwbufFromDecim <= dneTxbuf when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif else '0';
	dneSeqbufFromMemtrack <= dneTxbuf when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif else '0';
	dneSeqbufFromCputrack <= dneTxbuf when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif else '0';
	dneSeqbufFromVidtrack <= dneTxbuf when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif else '0';
	dneSeqbufFromHshktrack <= dneTxbuf when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif else '0';

	avllenTxbuf <= avllenCoobufFromCorner when tixVBuffer=tixVTivspBufferCoobufCornerToHostif
				else avllenFlgbufFromTrace when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif
				else avllenPvwbufFromDecim when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif
				else avllenSeqbufFromMemtrack when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif
				else avllenSeqbufFromCputrack when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif
				else avllenSeqbufFromVidtrack when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif
				else avllenSeqbufFromHshktrack when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif
				else (others => '0');

	txbufAXIS_tready <= '1' when stateOp=stateOpTxbufB else '0';

	coobufFromCornerAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferCoobufCornerToHostif else '0';
	flgbufFromTraceAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif else '0';
	pvwbufFromDecimAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif else '0';
	seqbufFromMemtrackAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif else '0';
	seqbufFromCputrackAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif else '0';
	seqbufFromVidtrackAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif else '0';
	seqbufFromHshktrackAXIS_tready <= txbufAXIS_tready when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif else '0';

	txbufAXIS_tvalid <= coobufFromCornerAXIS_tvalid when tixVBuffer=tixVTivspBufferCoobufCornerToHostif
				else flgbufFromTraceAXIS_tvalid when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif
				else pvwbufFromDecimAXIS_tvalid when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif
				else seqbufFromMemtrackAXIS_tvalid when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif
				else seqbufFromCputrackAXIS_tvalid when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif
				else seqbufFromVidtrackAXIS_tvalid when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif
				else seqbufFromHshktrackAXIS_tvalid when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif
				else '0';

	txbufAXIS_tdata <= coobufFromCornerAXIS_tdata when tixVBuffer=tixVTivspBufferCoobufCornerToHostif
				else flgbufFromTraceAXIS_tdata when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif
				else pvwbufFromDecimAXIS_tdata when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif
				else seqbufFromMemtrackAXIS_tdata when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif
				else seqbufFromCputrackAXIS_tdata when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif
				else seqbufFromVidtrackAXIS_tdata when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif
				else seqbufFromHshktrackAXIS_tdata when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif
				else (others => '0');

	txbufAXIS_tlast <= coobufFromCornerAXIS_tlast when tixVBuffer=tixVTivspBufferCoobufCornerToHostif
				else flgbufFromTraceAXIS_tlast when tixVBuffer=tixVTivspBufferFlgbufTraceToHostif
				else pvwbufFromDecimAXIS_tlast when tixVBuffer=tixVTivspBufferPvwbufDecimToHostif
				else seqbufFromMemtrackAXIS_tlast when tixVBuffer=tixVTivspBufferSeqbufMemtrackToHostif
				else seqbufFromCputrackAXIS_tlast when tixVBuffer=tixVTivspBufferSeqbufCputrackToHostif
				else seqbufFromVidtrackAXIS_tlast when tixVBuffer=tixVTivspBufferSeqbufVidtrackToHostif
				else seqbufFromHshktrackAXIS_tlast when tixVBuffer=tixVTivspBufferSeqbufHshktrackToHostif
				else '1';

	-- rx buffer
	rxbufvalid <=  '0';

	reqRxbuf <= '1' when stateOp=stateOpRxbufA or stateOp=stateOpRxbufB or stateOp=stateOpRxbufC or stateOp=stateOpRxbufD or stateOp=stateOpRxbufE or stateOp=stateOpRxbufF else '0';

	ackRxbuf <= '0';

	dneRxbuf <= '1' when stateOp=stateOpRxbufF else '0';

	avllenRxbuf <= (others => '0');

	rxbufAXIS_tvalid <= '1' when stateOp=stateOpRxbufC else '0';

	rxbufAXIS_tlast <= '1' when (stateOp=stateOpRxbufC and rxbuflast='1') else '0';

	rxbufAXIS_tready <= '0';

	crcAXIS_tvalid <= '1' when (stateOp=stateOpRxopB or stateOp=stateOpRxB or stateOp=stateOpRxbufB) and rxAXIS_tvalid='1' -- validate
				else '1' when (stateOp=stateOpTxpollC or stateOp=stateOpTxC or stateOp=stateOpTxbufC) -- calculate
				else '0';

	crcAXIS_tdata <= rxAXIS_tdata when (stateOp=stateOpRxopB or stateOp=stateOpRxB or stateOp=stateOpRxbufB)
				else txAXIS_tdata when (stateOp=stateOpTxpollC or stateOp=stateOpTxC or stateOp=stateOpTxbufC)
				else (others => '0');

	crcAXIS_tlast <= '1' when (stateOp=stateOpRxopB or stateOp=stateOpRxB or stateOp=stateOpRxbufB) and (crcAXIS_tlast_sig='0' and rxAXIS_tvalid='1' and rxAXIS_tlast='1')
				else crcAXIS_tlast_sig;

	reqRx <= '1' when stateOp=stateOpRxopB
				or stateOp=stateOpTxpollG
				or stateOp=stateOpTxG
				or stateOp=stateOpTxbufG
				or stateOp=stateOpRxB
				or stateOp=stateOpRxbufB or stateOp=stateOpRxbufC
				else '0';

	rxAXIS_tready <= '1' when stateOp=stateOpRxopB
				or stateOp=stateOpTxpollG
				or stateOp=stateOpTxG
				or stateOp=stateOpTxbufG
				or stateOp=stateOpRxB
				or stateOp=stateOpRxbufB
				else '0';

	restartWordto <= '0' when ((ackRx='1' and rxAXIS_tvalid='0' and (stateOp=stateOpRxopB or stateOp=stateOpRxB or stateOp=stateOpRxbufB))
				or (ackTx='1' and txAXIS_tready='0' and (stateOp=stateOpTxpollE or stateOp=stateOpTxE or stateOp=stateOpTxbufE)))
				else '1';

	restartXferto <= '0' when ((ackRx='0' and (stateOp=stateOpRxB or stateOp=stateOpRxbufB))
					or ((ackTx='0' and (stateOp=stateOpTxpollE or stateOp=stateOpTxE or stateOp=stateOpTxbufE)))
					or stateOp=stateOpRxopE or stateOp=stateOpTxpollG or stateOp=stateOpTxG or stateOp=stateOpTxbufG or stateOp=stateOpRxD or stateOp=stateOpRxbufE)
					else '1';

	reqTx <= '1' when stateOp=stateOpRxopE
				or stateOp=stateOpTxpollB or stateOp=stateOpTxpollC or stateOp=stateOpTxpollD or stateOp=stateOpTxpollE or stateOp=stateOpTxpollF
				or stateOp=stateOpTxE or stateOp=stateOpTxB or stateOp=stateOpTxC or stateOp=stateOpTxD or stateOp=stateOpTxF
				or stateOp=stateOpTxbufB or stateOp=stateOpTxbufC or stateOp=stateOpTxbufD or stateOp=stateOpTxbufE or stateOp=stateOpTxbufF
				or stateOp=stateOpRxD
				or stateOp=stateOpRxbufE
				else '0';

	txAXIS_tvalid <= '1' when stateOp=stateOpRxopE
				or stateOp=stateOpTxpollE
				or stateOp=stateOpTxE
				or stateOp=stateOpTxbufE
				or stateOp=stateOpRxD
				or stateOp=stateOpRxbufE
				else '0';
	
	txAXIS_tlast <= '1' when stateOp=stateOpRxopE
				or (stateOp=stateOpTxpollE and txlast='1')
				or (stateOp=stateOpTxE and txlast='1')
				or (stateOp=stateOpTxbufE and txlast='1')
				or stateOp=stateOpRxD
				or stateOp=stateOpRxbufE
				else '0';

	-- IP cust --- RBEGIN
	 stateOp_dbg <= x"00" when stateOp=stateOpInit
	 			else x"10" when stateOp=stateOpIdle
	 			else x"20" when stateOp=stateOpRxopA
	 			else x"21" when stateOp=stateOpRxopB
	 			else x"22" when stateOp=stateOpRxopC
	 			else x"23" when stateOp=stateOpRxopD
	 			else x"24" when stateOp=stateOpRxopE
	 			else x"30" when stateOp=stateOpTxpollA
	 			else x"31" when stateOp=stateOpTxpollB
	 			else x"32" when stateOp=stateOpTxpollC
	 			else x"33" when stateOp=stateOpTxpollD
	 			else x"34" when stateOp=stateOpTxpollE
	 			else x"35" when stateOp=stateOpTxpollF
	 			else x"36" when stateOp=stateOpTxpollG
	 			else x"40" when stateOp=stateOpTxA
	 			else x"41" when stateOp=stateOpTxB
	 			else x"42" when stateOp=stateOpTxC
	 			else x"43" when stateOp=stateOpTxD
	 			else x"44" when stateOp=stateOpTxE
	 			else x"45" when stateOp=stateOpTxF
	 			else x"46" when stateOp=stateOpTxG
	 			else x"50" when stateOp=stateOpTxbufA
	 			else x"51" when stateOp=stateOpTxbufB
	 			else x"52" when stateOp=stateOpTxbufC
	 			else x"53" when stateOp=stateOpTxbufD
	 			else x"54" when stateOp=stateOpTxbufE
	 			else x"55" when stateOp=stateOpTxbufF
	 			else x"56" when stateOp=stateOpTxbufG
	 			else x"57" when stateOp=stateOpTxbufH
	 			else x"60" when stateOp=stateOpRxA
	 			else x"61" when stateOp=stateOpRxB
	 			else x"62" when stateOp=stateOpRxC
	 			else x"63" when stateOp=stateOpRxD
	 			else x"70" when stateOp=stateOpRxbufA
	 			else x"71" when stateOp=stateOpRxbufB
	 			else x"72" when stateOp=stateOpRxbufC
	 			else x"73" when stateOp=stateOpRxbufD
	 			else x"74" when stateOp=stateOpRxbufE
	 			else x"75" when stateOp=stateOpRxbufF
	 			else x"80" when stateOp=stateOpInv
	 			else (others => '1');
	-- IP cust --- REND

	process (reset, mclk, stateOp)
		variable len: std_logic_vector(31 downto 0);

		variable full_vec: unsigned(31 downto 0);
		variable quot: natural;

		variable resid: natural range 0 to wD/8-1;
		variable residCrc: natural range 0 to wD/8-1;

		variable lastAXIS_tkeep: std_logic_vector(wD/8-1 downto 0);

		variable txAXIS_tdata_lcl: std_logic_vector(wD-1 downto 0);

		variable stateOp_next: stateOp_t;

		variable wordcnt: natural;
		variable wordcntLast: natural;
		variable wordcntCrcLast: natural range 0 to 16777216;

		variable ixRetbufCrc: natural range 0 to sizeRetbuf-2;

	begin
		if reset='1' then
			stateOp <= stateOpInit;
			opbuf <= (others => (others => '0'));
			tixVBuffer <= (others => '0');
			tixVController <= (others => '0');
			tixVCommand <= (others => '0');
			tixVBufxfop <= (others => '0');
			pollbuf <= (others => (others => '0'));
			invbuf <= (others => (others => '0'));
			retbuf <= (others => (others => '0'));
			commok_sig <= '1';
			reqReset_sig <= '0';
			rxbuflast <= '0';
			crcAXIS_tlast_sig <= '1';
			crcAXIS_tkeep <= (others => '1');
			rxlen <= (others => '0');
			txlen <= (others => '0');
			txAXIS_tdata <= (others => '0');
			txlast <= '0';

			len := (others => '0');
			full_vec := (others => '0');
			quot := 0;
			resid := 0;
			residCrc := 0;
			lastAXIS_tkeep := (others => '1');
			txAXIS_tdata_lcl := (others => '0');
			stateOp_next := stateOpInit;
			wordcnt := 0;
			wordcntLast := 0;
			wordcntCrcLast := 0;
			ixRetbufCrc := 0;

		elsif rising_edge(mclk) then
			if stateOp=stateOpInit or wordto='1' or xferto='1' then
				opbuf <= (others => (others => '0'));
				tixVBuffer <= (others => '0');
				tixVController <= (others => '0');
				tixVCommand <= (others => '0');
				tixVBufxfop <= (others => '0');
				pollbuf <= (others => (others => '0'));
				invbuf <= (others => (others => '0'));
				retbuf <= (others => (others => '0'));
				reqReset_sig <= '0';
				rxbuflast <= '0';
				crcAXIS_tlast_sig <= '1';
				crcAXIS_tkeep <= (others => '1');
				rxlen <= (others => '0');
				txlen <= (others => '0');
				txAXIS_tdata <= (others => '0');
				txlast <= '0';

				len := (others => '0');
				full_vec := (others => '0');
				quot := 0;
				resid := 0;
				residCrc := 0;
				lastAXIS_tkeep := (others => '1');
				txAXIS_tdata_lcl := (others => '0');
				stateOp_next := stateOpInit;
				wordcnt := 0;
				wordcntLast := 0;
				wordcntCrcLast := 0;
				ixRetbufCrc := 0;

				if wordto='1' or xferto='1' then
					commok_sig <= '0';

					stateOp <= stateOpInit;

				else
					stateOp <= stateOpIdle;
				end if;

			elsif stateOp=stateOpIdle then
				crcAXIS_tlast_sig <= '0';

				stateOp <= stateOpRxopA;

-- RX OP BEGIN
			elsif stateOp=stateOpRxopA then
				if wD=128 then
					rxlen <= (others => '0');

					crcAXIS_tlast_sig <= '1';
					crcAXIS_tkeep <= opbufLastAXIS_tkeep;
	
					wordcntLast := 0;

				else
					rxlen <= std_logic_vector(to_unsigned(sizeOpbuf/(wD/8)-1, 32));
					wordcntLast := sizeOpbuf/(wD/8) - 1;
				end if;

				wordcnt := 0;

				stateOp <= stateOpRxopB;

			elsif stateOp=stateOpRxopB then -- reqRx='1', rxAXIS_tready='1'
				if rxAXIS_tvalid='1' then
					commok_sig <= '1';

					for i in 0 to wD/8-1 loop
						opbuf(wordcnt*wD/8+i) <= rxAXIS_tdata(8*(i+1)-1 downto 8*i);
					end loop;

					if wordcnt=wordcntLast then
						crcAXIS_tlast_sig <= '1';

						stateOp <= stateOpRxopC;

					else
						if wordcnt=wordcntLast-1 then
							crcAXIS_tkeep <= opbufLastAXIS_tkeep;
						end if;
						
						wordcnt := wordcnt + 1;
					end if;
				end if;

			elsif stateOp=stateOpRxopC then
				crcAXIS_tkeep <= (others => '1');

				if crc=x"0000" then
					tixVBuffer <= opbuf(ixOpbufBuffer);
					if opbuf(ixOpbufBuffer)/=tixVTivspBufferCmdretToHostif or opbuf(ixOpbufBufxfBufxfop)/=tixVBufxfopPoll then
						tixVController <= opbuf(ixOpbufController);
						tixVCommand <= opbuf(ixOpbufCmdCommand);
					end if;
					tixVBufxfop <= opbuf(ixOpbufBufxfBufxfop);

					len := opbuf(ixOpbufLen) & opbuf(ixOpbufLen+1) & opbuf(ixOpbufLen+2) & opbuf(ixOpbufLen+3);

					stateOp <= stateOpRxopD;
				
				else
					commok_sig <= '0';

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpRxopD then
				stateOp_next := stateOpInit;

				if tixVBuffer=tixVTivspBufferCmdretToHostif and tixVBufxfop=tixVBufxfopPoll and len(7 downto 0)=x"04" then
					stateOp_next := stateOpTxpollA;

				elsif tixVBuffer=tixVTivspBufferHostifToCmdinv and cmdvalid='1' and len(15 downto 0)=lenInv then
					if unsigned(lenInv)=0 then
						stateOp_next := stateOpInv;
					else
						stateOp_next := stateOpRxA;
					end if;

				elsif (txbufvalid='1' or rxbufvalid='1') and tixVBufxfop=tixVBufxfopPoll then
					stateOp_next := stateOpTxpollA;

				elsif txbufvalid='1' and tixVBufxfop=tixVBufxfopXfer and len=avllenTxbuf and unsigned(len)/=0 then
					if wD=8 or (wD=16 and len(0)='0') or (wD=32 and len(1 downto 0)="00") or (wD=64 and len(2 downto 0)="000") or (wD=128 and len(3 downto 0)="0000") then
						stateOp_next := stateOpTxbufA;
					end if;

				elsif rxbufvalid='1' and tixVBufxfop=tixVBufxfopXfer and unsigned(len)<=unsigned(avllenRxbuf) and unsigned(len)/=0 then
					if wD=8 or (wD=16 and len(0)='0') or (wD=32 and len(1 downto 0)="00") or (wD=64 and len(2 downto 0)="000") or (wD=128 and len(3 downto 0)="0000") then
						stateOp_next := stateOpRxbufA;
					end if;
				end if;

				txlen <= (others => '0');
				txlast <= '1';

				if stateOp_next=stateOpInit then
					txAXIS_tdata(7 downto 0) <= fls8;
				else
					txAXIS_tdata(7 downto 0) <= tru8;
				end if;

				stateOp <= stateOpRxopE;

			elsif stateOp=stateOpRxopE then -- reqTx='1', txAXIS_tvalid='1', txAXIS_tlast='1'
				if dneTx='1' then
					if stateOp_next/=stateOpInit then
						crcAXIS_tlast_sig <= '0';
					end if;

					stateOp <= stateOp_next;
				end if;

-- RX OP END, TX POLL BEGIN
			elsif stateOp=stateOpTxpollA then
				if tixVBuffer=tixVTivspBufferCmdretToHostif then
					pollbuf(ixPollbufCmdController) <= tixVController;
					pollbuf(ixPollbufCmdCommand) <= tixVCommand;
					pollbuf(ixPollbufCmdLen) <= lenRet(15 downto 8);
					pollbuf(ixPollbufCmdLen+1) <= lenRet(7 downto 0);
				elsif txbufvalid='1' then
					pollbuf(ixPollbufBufxfAvllen) <= avllenTxbuf(31 downto 24);
					pollbuf(ixPollbufBufxfAvllen+1) <= avllenTxbuf(23 downto 16);
					pollbuf(ixPollbufBufxfAvllen+2) <= avllenTxbuf(15 downto 8);
					pollbuf(ixPollbufBufxfAvllen+3) <= avllenTxbuf(7 downto 0);
				elsif rxbufvalid='1' then
					pollbuf(ixPollbufBufxfAvllen) <= avllenRxbuf(31 downto 24);
					pollbuf(ixPollbufBufxfAvllen+1) <= avllenRxbuf(23 downto 16);
					pollbuf(ixPollbufBufxfAvllen+2) <= avllenRxbuf(15 downto 8);
					pollbuf(ixPollbufBufxfAvllen+3) <= avllenRxbuf(7 downto 0);
				end if;

				if wD=64 or wD=128 then
					txlen <= (others => '0');
					txlast <= '1';

					wordcntLast := 0;

				else
					txlen <= std_logic_vector(to_unsigned(sizePollbuf/(wD/8)-1, 32));
					txlast <= '0';

					wordcntLast := sizePollbuf/(wD/8)-1;
				end if;

				wordcnt := 0;

				stateOp <= stateOpTxpollB;

			elsif stateOp=stateOpTxpollB then -- load into txAXIS_tdata
				for i in 0 to wD/8-1 loop
					txAXIS_tdata(8*(i+1)-1 downto 8*i) <= pollbuf(wordcnt*wD/8+i);
				end loop;

				if (wD=64 or wD=128) or ((wD=8 or wD=16 or wD=32) and wordcnt=ixPollbufCrc/(wD/8)-1) then
					crcAXIS_tlast_sig <= '1';
					crcAXIS_tkeep <= pollbufLastAXIS_tkeep;
				end if;

				stateOp <= stateOpTxpollC;

			elsif stateOp=stateOpTxpollC then -- calc CRC on txAXIS_tdata
				if crcAXIS_tlast_sig='1' then
					stateOp <= stateOpTxpollD;
				else
					stateOp <= stateOpTxpollE;
				end if;

			elsif stateOp=stateOpTxpollD then -- update pollbuf or txAXIS_tdata
				if wD=64 or wD=128 then
					txAXIS_tdata(5*8-1 downto 4*8) <= crc(15 downto 8);
					txAXIS_tdata(6*8-1 downto 5*8) <= crc(7 downto 0);

				else
					pollbuf(ixPollbufCrc) <= crc(15 downto 8);
					pollbuf(ixPollbufCrc + 1) <= crc(7 downto 0);
				end if;

				stateOp <= stateOpTxpollE;

			elsif stateOp=stateOpTxpollE then
				if txAXIS_tready='1' then
					if wordcnt=wordcntLast then
						crcAXIS_tkeep <= (others => '1');

						stateOp <= stateOpTxpollF;
					
					else
						wordcnt := wordcnt + 1;

						if wordcnt=wordcntLast then
							txlast <= '1';
						end if;

						stateOp <= stateOpTxpollB;
					end if;
				end if;

			elsif stateOp=stateOpTxpollF then
				if dneTx='1' then
					rxlen <= (others => '0');

					stateOp <= stateOpTxpollG;
				end if;

			elsif stateOp=stateOpTxpollG then -- reqRx='1', rxAXIS_tready'1'
				if rxAXIS_tvalid='1' then
					if rxAXIS_tdata(7 downto 0)/=tru8 then
						stateOp <= stateOpInit;

					else
						if tixVBuffer=tixVTivspBufferCmdretToHostif then
							crcAXIS_tlast_sig <= '0';

							stateOp <= stateOpTxA;

						else
							stateOp <= stateOpInit;
						end if;
					end if;
				end if;

-- TX POLL END, TX BEGIN
			elsif stateOp=stateOpTxA then
				ixRetbufCrc := to_integer(unsigned(lenRet));

				full_vec := resize(unsigned(lenRet), 32) + 1; -- +2 (for CRC) -1

				if wD=8 then
					resid := 1;

					txlen <= std_logic_vector(full_vec);
					wordcntLast := to_integer(full_vec);

					wordcntCrcLast := to_integer(unsigned(lenRet) - 1);
					lastAXIS_tkeep := (others => '1');

				else
					if wD=16 then
						quot := to_integer(full_vec(31 downto 1));
						resid := to_integer(unsigned(full_vec(0 downto 0)));
					elsif wD=32 then
						quot := to_integer(full_vec(31 downto 2));
						resid := to_integer(unsigned(full_vec(1 downto 0)));
					elsif wD=64 then
						quot := to_integer(full_vec(31 downto 3));
						resid := to_integer(unsigned(full_vec(2 downto 0)));
					elsif wD=128 then
						quot := to_integer(full_vec(31 downto 4));
						resid := to_integer(unsigned(full_vec(3 downto 0)));
					end if;

					txlen <= std_logic_vector(to_unsigned(quot, 32));
					wordcntLast := quot;

					if resid=0 then
						wordcntCrcLast := quot - 1;
						residCrc := wD/8 - 2;
					elsif resid=1 then
						wordcntCrcLast := quot - 1;
						residCrc := wD/8 - 1;
					else
						wordcntCrcLast := quot;
						residCrc := resid - 2;
					end if;

					for i in 0 to wD/8-1 loop
						if residCrc>=i then
							lastAXIS_tkeep(i) := '1';
						else
							lastAXIS_tkeep(i) := '0';
						end if;
					end loop;
				end if;

				if wordcntLast=0 then
					txlast <= '1';
				else
					txlast <= '0';
				end if;

				wordcnt := 0;
				
				stateOp <= stateOpTxB;

			elsif stateOp=stateOpTxB then -- load into txAXIS_tdata
				for i in 0 to wD/8-1 loop
					txAXIS_tdata(8*(i+1)-1 downto 8*i) <= retbuf(wordcnt*wD/8+i);
				end loop;

				if wordcnt=wordcntCrcLast then
					crcAXIS_tlast_sig <= '1';
					crcAXIS_tkeep <= lastAXIS_tkeep;
				end if;

				stateOp <= stateOpTxC;

			elsif stateOp=stateOpTxC then
				if crcAXIS_tlast_sig='1' then
					stateOp <= stateOpTxD;
				
				else
					stateOp <= stateOpTxE;
				end if;

			elsif stateOp=stateOpTxD then
				if resid=0 then
					txAXIS_tdata(wD-1 downto wD-8) <= crc(15 downto 8);
					retbuf(ixRetbufCrc + 1) <= crc(7 downto 0);

				elsif resid=1 then
					retbuf(ixRetbufCrc) <= crc(15 downto 8);
					retbuf(ixRetbufCrc + 1) <= crc(7 downto 0);

				else
					-- ex. wD = 32, resid = 2, i.e. -CCX => crc(15..8) into 15..8; crc(7..0) into 23..16
					txAXIS_tdata(resid*8-1 downto (resid-1)*8) <= crc(15 downto 8);
					txAXIS_tdata((resid+1)*8-1 downto resid*8) <= crc(7 downto 0);
				end if;

				stateOp <= stateOpTxE;

			elsif stateOp=stateOpTxE then
				if txAXIS_tready='1' then
					if wordcnt=wordcntLast then
						crcAXIS_tkeep <= (others => '1');
						txlast <= '0';

						stateOp <= stateOpTxF;
					
					else
						wordcnt := wordcnt + 1;

						if wordcnt=wordcntLast then
							txlast <= '1';
						end if;

						stateOp <= stateOpTxB;
					end if;
				end if;

			elsif stateOp=stateOpTxF then
				if dneTx='1' then
					rxlen <= (others => '0');

					stateOp <= stateOpTxG;
				end if;

			elsif stateOp=stateOpTxG then -- reqRx='1', rxAXIS_tready'1'
				if rxAXIS_tvalid='1' then
					if rxAXIS_tdata(7 downto 0)/=tru8 then
						stateOp <= stateOpIdle; -- offer chance to re-retrieve the return of a command
					else
						stateOp <= stateOpInit;
					end if;
				end if;

-- TX END, TX BUF BEGIN
			elsif stateOp=stateOpTxbufA then -- reqTxbuf='1'
				if ackTxbuf='1' then
					full_vec := resize(unsigned(len), 32) + 1; -- +2 (for CRC) -1

					if wD=8 then
						txlen <= std_logic_vector(full_vec);
						wordcntLast := to_integer(full_vec);
						wordcntCrcLast := to_integer(unsigned(len) - 1);
					elsif wD=16 then
						txlen <= "0" & std_logic_vector(full_vec(31 downto 1));
						wordcntLast := to_integer(full_vec(31 downto 1));
						wordcntCrcLast := to_integer(full_vec(31 downto 1) - 1);
					elsif wD=32 then
						txlen <= "00" & std_logic_vector(full_vec(31 downto 2));
						wordcntLast := to_integer(full_vec(31 downto 2));
						wordcntCrcLast := to_integer(full_vec(31 downto 2) - 1);
					elsif wD=64 then
						txlen <= "000" & std_logic_vector(full_vec(31 downto 3));
						wordcntLast := to_integer(full_vec(31 downto 3));
						wordcntCrcLast := to_integer(full_vec(31 downto 3) - 1);
					elsif wD=128 then
						txlen <= "0000" & std_logic_vector(full_vec(31 downto 4));
						wordcntLast := to_integer(full_vec(31 downto 4));
						wordcntCrcLast := to_integer(full_vec(31 downto 4) - 1);
					end if;

					txlast <= '0';

					wordcnt := 0;

					stateOp <= stateOpTxbufB;
				end if;

			elsif stateOp=stateOpTxbufB then -- load into txAXIS_tdata
				if txbufAXIS_tvalid='1' then
					txAXIS_tdata <= txbufAXIS_tdata;

					if wordcnt=wordcntCrcLast then
						crcAXIS_tlast_sig <= '1';
					end if;

					stateOp <= stateOpTxbufC;
				end if;

			elsif stateOp=stateOpTxbufC then -- calc CRC on txAXIS_tdata
				stateOp <= stateOpTxbufE;

			elsif stateOp=stateOpTxbufD then
				if wD=8 and wordcnt=wordcntLast-1 then
					txAXIS_tdata <= crc(15 downto 8);
				elsif wD=8 and wordcnt=wordcntLast then
					txAXIS_tdata <= crc(7 downto 0);
				else
					txAXIS_tdata(7 downto 0) <= crc(15 downto 8);
					txAXIS_tdata(15 downto 8) <= crc(7 downto 0);
				end if;

				stateOp <= stateOpTxbufE;

			elsif stateOp=stateOpTxbufE then
				if txAXIS_tready='1' then
					if wordcnt=wordcntLast then
						txlast <= '0';

						stateOp <= stateOpTxbufF;
					
					else
						wordcnt := wordcnt + 1;

						if wordcnt=wordcntLast then
							txlast <= '1';
						end if;

						if wordcnt>wordcntCrcLast then
							stateOp <= stateOpTxbufD;
						else
							stateOp <= stateOpTxbufB;
						end if;
					end if;
				end if;

			elsif stateOp=stateOpTxbufF then
				if dneTx='1' then
					rxlen <= (others => '0');

					stateOp <= stateOpTxbufG;
				end if;

			elsif stateOp=stateOpTxbufG then -- reqRx='1', rxAXIS_tready'1'
				if rxAXIS_tvalid='1' then
					if rxAXIS_tdata(7 downto 0)/=tru8 then
						stateOp <= stateOpInit;
					else
						stateOp <= stateOpTxbufH;
					end if;
				end if;

			elsif stateOp=stateOpTxbufH then -- dneTxbuf='1'
				if ackTxbuf='0' then
					stateOp <= stateOpInit;
				end if;

-- TX BUF END, RX BEGIN
			elsif stateOp=stateOpRxA then
				full_vec := resize(unsigned(lenInv), 32) + 1; -- +2 (for CRC) -1
				if wD=8 then
					rxlen <= std_logic_vector(full_vec);
					wordcntLast := to_integer(full_vec);

				else
					if wD=16 then
						quot := to_integer(full_vec(31 downto 1));
						resid := to_integer(unsigned(full_vec(0 downto 0)));
					elsif wD=32 then
						quot := to_integer(full_vec(31 downto 2));
						resid := to_integer(unsigned(full_vec(1 downto 0)));
					elsif wD=64 then
						quot := to_integer(full_vec(31 downto 3));
						resid := to_integer(unsigned(full_vec(2 downto 0)));
					elsif wD=128 then
						quot := to_integer(full_vec(31 downto 4));
						resid := to_integer(unsigned(full_vec(3 downto 0)));
					end if;

					rxlen <= std_logic_vector(to_unsigned(quot, 32));

					for i in 0 to wD/8-1 loop
						if resid>=i then
							lastAXIS_tkeep(i) := '1';
						else
							lastAXIS_tkeep(i) := '0';
						end if;
					end loop;

					wordcntLast := quot;

					if wordcntLast=0 then
						crcAXIS_tlast_sig <= '1';
						crcAXIS_tkeep <= lastAXIS_tkeep;
					end if;
				end if;

				wordcnt := 0;

				stateOp <= stateOpRxB;

			elsif stateOp=stateOpRxB then -- reqRx='1', rxAXIS_tready='1'
				if rxAXIS_tvalid='1' then
					for i in 0 to wD/8-1 loop
						invbuf(wordcnt*wD/8+i) <= rxAXIS_tdata(8*(i+1)-1 downto 8*i);
					end loop;

					if wordcnt=wordcntLast then
						crcAXIS_tlast_sig <= '1';

						stateOp <= stateOpRxC;

					else
						if wordcnt=wordcntLast-1 then
							crcAXIS_tkeep <= lastAXIS_tkeep;
						end if;

						wordcnt := wordcnt + 1;
					end if;
				end if;

			elsif stateOp=stateOpRxC then
				crcAXIS_tkeep <= (others => '1');

				if crc=x"0000" then
					txlen <= (others => '0');
					txlast <= '1';

					txAXIS_tdata(7 downto 0) <= tru8;

					stateOp <= stateOpRxD;
				
				else
					commok_sig <= '0';

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpRxD then -- reqTx='1', txAXIS_tvalid='1', txAXIS_tlast='1'
				if dneTx='1' then
					stateOp <= stateOpInv;
				end if;

-- RX END, RX BUF BEGIN
			elsif stateOp=stateOpRxbufA then -- reqRxbuf='1'
				if ackRxbuf='1' then
					full_vec := resize(unsigned(len), 32) + 1; -- +2 (for CRC) -1
					if wD=8 then
						rxlen <= std_logic_vector(full_vec);
						wordcntLast := to_integer(full_vec);

					else
						if wD=16 then
							quot := to_integer(full_vec(31 downto 1));
							resid := to_integer(unsigned(full_vec(0 downto 0)));
						elsif wD=32 then
							quot := to_integer(full_vec(31 downto 2));
							resid := to_integer(unsigned(full_vec(1 downto 0)));
						elsif wD=64 then
							quot := to_integer(full_vec(31 downto 3));
							resid := to_integer(unsigned(full_vec(2 downto 0)));
						elsif wD=128 then
							quot := to_integer(full_vec(31 downto 4));
							resid := to_integer(unsigned(full_vec(3 downto 0)));
						end if;

						rxlen <= std_logic_vector(to_unsigned(quot, 32));

						for i in 0 to wD/8-1 loop
							if resid>=i then
								lastAXIS_tkeep(i) := '1';
							else
								lastAXIS_tkeep(i) := '0';
							end if;
						end loop;

						wordcntLast := quot;
					end if;

					wordcnt := 0;

					stateOp <= stateOpRxbufB;
				end if;

			elsif stateOp=stateOpRxbufB then -- reqRx='1', rxAXIS_tready='1'
				if rxAXIS_tvalid='1' then
					rxbufAXIS_tdata <= rxAXIS_tdata;

					if wordcnt=wordcntLast-2 and wD=8 then
						rxbuflast <= '1';

						wordcnt := wordcnt + 1;

						stateOp <= stateOpRxbufC;

					elsif wordcnt=wordcntLast-1 then
						rxbuflast <= '1';

						crcAXIS_tkeep <= lastAXIS_tkeep;

						wordcnt := wordcnt + 1;

						if wD=8 then
							stateOp <= stateOpRxbufB;
						else
							stateOp <= stateOpRxbufC;
						end if;

					elsif wordcnt=wordcntLast then
						crcAXIS_tlast_sig <= '1';

						stateOp <= stateOpRxbufD;

					else
						wordcnt := wordcnt + 1;

						stateOp <= stateOpRxbufC;
					end if;
				end if;

			elsif stateOp=stateOpRxbufC then -- rxbufAXIS_tvalid='1'
				if rxbufAXIS_tready='1' then
					stateOp <= stateOpRxbufB;
				end if;

			elsif stateOp=stateOpRxbufD then
				crcAXIS_tkeep <= (others => '1');

				if crc=x"0000" then
					txlen <= (others => '0');
					txlast <= '1';

					txAXIS_tdata(7 downto 0) <= tru8;

					stateOp <= stateOpRxbufE;
				
				else
					commok_sig <= '0';

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpRxbufE then -- reqTx='1', txAXIS_tvalid='1', txAXIS_tlast='1'
				if dneTx='1' then
					stateOp <= stateOpRxbufF;
				end if;

			elsif stateOp=stateOpRxbufF then -- reqRxbuf='1', dneRxbuf='1'
				if ackRxbuf='0' then
					stateOp <= stateOpInit;
				end if;
-- RX BUF END

			elsif stateOp=stateOpInv then -- reqInv='1
				if tixVController=tixVTivspControllerHostif and tixVCommand=x"00" then
					reqReset_sig <= '1';

				elsif ackInv='1' then
					if tixVController=tixVTivspControllerIdent then
						if tixVCommand=tixVIdentCommandGet then
							for i in 0 to 11 loop
								retbuf(11-i) <= identGetUnt((12-i)*8-1 downto (11-i)*8);
							end loop;
							for i in 0 to 7 loop
								retbuf(12+7-i) <= identGetVer((8-i)*8-1 downto (7-i)*8);
							end loop;
							for i in 0 to 7 loop
								retbuf(20+7-i) <= identGetHash((8-i)*8-1 downto (7-i)*8);
							end loop;
							for i in 0 to 7 loop
								retbuf(28+7-i) <= identGetWho((8-i)*8-1 downto (7-i)*8);
							end loop;
						elsif tixVCommand=tixVIdentCommandGetCfg then
							for i in 0 to 3 loop
								retbuf(i) <= identGetCfgFMclk((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 3 loop
								retbuf(4+i) <= identGetCfgFMemclk((4-i)*8-1 downto (3-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerCamif then
						if tixVCommand=tixVCamifCommandGetReg then
							retbuf(0) <= camifGetRegVal;
						elsif tixVCommand=tixVCamifCommandGetCorereg then
							for i in 0 to 3 loop
								retbuf(i) <= camifGetCoreregVal((4-i)*8-1 downto (3-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerCorner then
						if tixVCommand=tixVCornerCommandGetInfo then
							retbuf(0) <= cornerGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= cornerGetInfoTkst((4-i)*8-1 downto (3-i)*8);
							end loop;
							retbuf(5) <= cornerGetInfoScoreMin;
							retbuf(6) <= cornerGetInfoScoreMax;
						end if;

					elsif tixVController=tixVTivspControllerDdrif then
						if tixVCommand=tixVDdrifCommandGetStats then
							for i in 0 to 3 loop
								retbuf(i) <= ddrifGetStatsNRdA((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 3 loop
								retbuf(4+i) <= ddrifGetStatsNRdB((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 3 loop
								retbuf(8+i) <= ddrifGetStatsNWrA((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 3 loop
								retbuf(12+i) <= ddrifGetStatsNWrB((4-i)*8-1 downto (3-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerDecim then
						if tixVCommand=tixVDecimCommandGetInfo then
							retbuf(0) <= decimGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= decimGetInfoTkst((4-i)*8-1 downto (3-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerHdreng then
						if tixVCommand=tixVHdrengCommandGetInfo then
							retbuf(0) <= hdrengGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= hdrengGetInfoTkst((4-i)*8-1 downto (3-i)*8);
							end loop;
							retbuf(5) <= hdrengGetInfoIxMem;
							retbuf(6) <= hdrengGetInfoIxMemAcq;
						end if;

					elsif tixVController=tixVTivspControllerRotary then
						if tixVCommand=tixVRotaryCommandGetInfo then
							retbuf(0) <= rotaryGetInfoTixVState;
							for i in 0 to 1 loop
								retbuf(1+i) <= rotaryGetInfoAngle((2-i)*8-1 downto (1-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerTkclksrc then
						if tixVCommand=tixVTkclksrcCommandGetTkst then
							for i in 0 to 3 loop
								retbuf(i) <= tkclksrcGetTkstTkst((4-i)*8-1 downto (3-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerTrace then
						if tixVCommand=tixVTraceCommandGetInfo then
							retbuf(0) <= traceGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= traceGetInfoTkst((4-i)*8-1 downto (3-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerCputrack then
						if tixVCommand=tixVCputrackCommandGetInfo then
							retbuf(0) <= cputrackGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= cputrackGetInfoTCapt((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 1 loop
								retbuf(5+i) <= cputrackGetInfoPtr0Seqbuf((2-i)*8-1 downto (1-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerHshktrack then
						if tixVCommand=tixVHshktrackCommandGetInfo then
							retbuf(0) <= hshktrackGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= hshktrackGetInfoTCapt((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 1 loop
								retbuf(5+i) <= hshktrackGetInfoPtr0Seqbuf((2-i)*8-1 downto (1-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerMemtrack then
						if tixVCommand=tixVMemtrackCommandGetInfo then
							retbuf(0) <= memtrackGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= memtrackGetInfoTCapt((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 1 loop
								retbuf(5+i) <= memtrackGetInfoPtr0Seqbuf((2-i)*8-1 downto (1-i)*8);
							end loop;
						end if;

					elsif tixVController=tixVTivspControllerVidtrack then
						if tixVCommand=tixVVidtrackCommandGetInfo then
							retbuf(0) <= vidtrackGetInfoTixVState;
							for i in 0 to 3 loop
								retbuf(1+i) <= vidtrackGetInfoTCapt((4-i)*8-1 downto (3-i)*8);
							end loop;
							for i in 0 to 1 loop
								retbuf(5+i) <= vidtrackGetInfoPtr0Seqbuf((2-i)*8-1 downto (1-i)*8);
							end loop;
						end if;

					end if;

					stateOp <= stateOpIdle; -- not init, so cmdretToHostif (maintaining tixVController/tixVCommand) can be run
				end if;
			end if;
		end if;
	end process;

end Rtl;
