-- file Render.vhd
-- Render easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Render is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		resetMemclk: in std_logic;
		memclk: in std_logic;

		rndmemAXI_awaddr: out std_logic_vector(17 downto 0);
		rndmemAXI_awready: in std_logic;
		rndmemAXI_awvalid: out std_logic;
		rndmemAXI_wdata: out std_logic_vector(127 downto 0);
		rndmemAXI_wlast: out std_logic;
		rndmemAXI_wready: in std_logic;
		rndmemAXI_wvalid: out std_logic;

		reqToDdrifWr: out std_logic;
		ackToDdrifWr: in std_logic;

		rndmemAXI_araddr: out std_logic_vector(17 downto 0);
		rndmemAXI_arready: in std_logic;
		rndmemAXI_arvalid: out std_logic;
		rndmemAXI_rdata: in std_logic_vector(127 downto 0);
		rndmemAXI_rlast: in std_logic;
		rndmemAXI_rready: out std_logic;
		rndmemAXI_rresp: in std_logic_vector(1 downto 0);
		rndmemAXI_rvalid: in std_logic;

		reqToDdrifRd: out std_logic;
		ackToDdrifRd: in std_logic
	);
end Render;

architecture Rtl of Render is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_size16kB_a32b128 is
		port (
			rstA: in std_logic;
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic;

			aA: in std_logic_vector(11 downto 0);
			drdA: out std_logic_vector(31 downto 0);
			dwrA: in std_logic_vector(31 downto 0);

			rstB: in std_logic;
			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic;

			aB: in std_logic_vector(9 downto 0);
			drdB: out std_logic_vector(127 downto 0);
			dwrB: in std_logic_vector(127 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- DDR memory egress (egr)
	type stateEgr_t is (
		stateEgrInit,
		stateEgrCopyA, stateEgrCopyB, stateEgrCopyC
	);
	signal stateEgr: stateEgr_t;

	signal rndmemAXI_awaddr_sig: std_logic_vector(17 downto 0);

	-- IP sigs.egr.cust --- INSERT

	---- DDR memory ingress (igr)
	type stateIgr_t is (
		stateIgrInit,
		stateIgrCopyA, stateIgrCopyB
	);
	signal stateIgr: stateIgr_t;

	signal rndmemAXI_araddr_sig: std_logic_vector(17 downto 0);

	-- IP sigs.igr.cust --- INSERT

	---- main operation (op)
	type stateOp_t is (
		stateOpInit
	);
	signal stateOp: stateOp_t;

	signal enRowAbuf: std_logic;
	signal enRowBbuf: std_logic;
	signal weRowbuf: std_logic;
	signal aRowbuf: natural;
	signal aRowbuf_vec: std_logic_vector(11 downto 0);
	signal dwrRowbuf: std_logic_vector(31 downto 0);

	signal enRowAbufB: std_logic;
	signal enRowBbufB: std_logic;
	signal weRowbufB: std_logic;
	signal aRowbufB: natural;
	signal aRowbufB_vec: std_logic_vector(9 downto 0);
	signal dwrRowbufB: std_logic_vector(127 downto 0);

	-- IP sigs.op.cust --- INSERT

	---- myRowAbuf
	signal drdRowAbuf: std_logic_vector(31 downto 0);

	signal drdRowAbufB: std_logic_vector(127 downto 0);

	---- myRowBbuf
	signal drdRowBbuf: std_logic_vector(31 downto 0);

	signal drdRowBbufB: std_logic_vector(127 downto 0);

	---- other
	-- IP sigs.oth.cust --- IBEGIN
	signal egrAXIS_tdata: std_logic_vector(127 downto 0);
	signal egrAXIS_tvalid: std_logic;

	signal reqEgrToEgrstr: std_logic;
	signal ackEgrToEgrstr: std_logic;
	-- IP sigs.oth.cust --- IEND

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myRowAbuf : Dpbram_size16kB_a32b128
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enRowAbuf,
			weA => weRowbuf,

			aA => aRowbuf_vec,
			drdA => drdRowAbuf,
			dwrA => dwrRowbuf,

			rstB => resetMemclk,
			clkB => memclk,

			enB => enRowAbufB,
			weB => weRowbufB,

			aB => aRowbufB_vec,
			drdB => drdRowAbufB,
			dwrB => dwrRowbufB
		);

	myRowBbuf : Dpbram_size16kB_a32b128
		port map (
			rstA => reset,
			clkA => mclk,

			enA => enRowBbuf,
			weA => weRowbuf,

			aA => aRowbuf_vec,
			drdA => drdRowBbuf,
			dwrA => dwrRowbuf,

			rstB => resetMemclk,
			clkB => memclk,

			enB => enRowBbufB,
			weB => weRowbufB,

			aB => aRowbufB_vec,
			drdB => drdRowBbufB,
			dwrB => dwrRowbufB
		);

	------------------------------------------------------------------------
	-- implementation: DDR memory egress (egr)
	------------------------------------------------------------------------

	-- IP impl.egr.wiring --- BEGIN
	rndmemAXI_awaddr <= rndmemAXI_awaddr_sig;
	rndmemAXI_awvalid <= '1' when stateEgr=stateEgrCopyB else '0';

	rndmemAXI_wdata <= egrAXIS_tdata;
	rndmemAXI_wlast <= '0' when ((reqEgrToEgrstr='1' and ackEgrToEgrstr='0') or stateEgr=stateEgrCopyC) else '1';
	rndmemAXI_wvalid <= egrAXIS_tvalid;

	reqToDdrifWr <= '1' when stateEgr=stateEgrCopyB else '0';
	-- IP impl.egr.wiring --- END

	-- IP impl.egr.wiring.cust --- LINE

	-- IP impl.egr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.egr.vars --- BEGIN
		-- IP impl.egr.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.egr.asyncrst --- BEGIN
			stateEgr <= stateEgrInit;
			rndmemAXI_awaddr_sig <= (others => '0');

			-- IP impl.egr.asyncrst --- END
			-- IP impl.egr.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if stateEgr=stateEgrInit then
				-- IP impl.egr.syncrst --- BEGIN
				rndmemAXI_awaddr_sig <= (others => '0');

				stateEgr <= stateEgrCopyA;
				-- IP impl.egr.syncrst --- END
				-- IP impl.egr.syncrst.cust --- INSERT

			elsif stateEgr=stateEgrCopyA then
				-- IP impl.egr.copyA --- INSERT

			elsif stateEgr=stateEgrCopyB then
				-- IP impl.egr.copyB --- INSERT

			elsif stateEgr=stateEgrCopyC then
				-- IP impl.egr.copyC --- INSERT
			end if;
		end if;
	end process;
	-- IP impl.egr.rising --- END

	------------------------------------------------------------------------
	-- implementation: DDR memory ingress (igr)
	------------------------------------------------------------------------

	-- IP impl.igr.wiring --- BEGIN
	rndmemAXI_araddr <= rndmemAXI_araddr_sig;
	rndmemAXI_arvalid <= '1' when stateIgr=stateIgrCopyB else '0';

	reqToDdrifRd <= '1' when stateIgr=stateIgrCopyB else '0';
	-- IP impl.igr.wiring --- END

	-- IP impl.igr.wiring.cust --- LINE

	-- IP impl.igr.rising --- BEGIN
	process (resetMemclk, memclk)
		-- IP impl.igr.vars --- BEGIN
		-- IP impl.igr.vars --- END

	begin
		if resetMemclk='1' then
			-- IP impl.igr.asyncrst --- BEGIN
			stateIgr <= stateIgrInit;
			rndmemAXI_araddr_sig <= (others => '0');

			-- IP impl.igr.asyncrst --- END
			-- IP impl.igr.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if stateIgr=stateIgrInit then
				-- IP impl.igr.syncrst --- BEGIN
				rndmemAXI_araddr_sig <= (others => '0');

				stateIgr <= stateIgrCopyA;
				-- IP impl.igr.syncrst --- END
				-- IP impl.igr.syncrst.cust --- INSERT

			elsif stateIgr=stateIgrCopyA then
				-- IP impl.igr.copyA --- INSERT

			elsif stateIgr=stateIgrCopyB then
				-- IP impl.igr.copyB --- INSERT
			end if;
		end if;
	end process;
	-- IP impl.igr.rising --- END

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- LINE

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- BEGIN
		-- IP impl.op.vars --- END

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- BEGIN
			stateOp <= stateOpInit;
			enRowAbuf <= '0';
			enRowBbuf <= '0';
			weRowbuf <= '0';
			aRowbuf <= 0;
			aRowbuf_vec <= (others => '0');
			dwrRowbuf <= (others => '0');
			enRowAbufB <= '0';
			enRowBbufB <= '0';
			weRowbufB <= '0';
			aRowbufB <= 0;
			aRowbufB_vec <= (others => '0');
			dwrRowbufB <= (others => '0');

			-- IP impl.op.asyncrst --- END
			-- IP impl.op.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if stateOp=stateOpInit then
				-- IP impl.op.syncrst --- BEGIN
				enRowAbuf <= '0';
				enRowBbuf <= '0';
				weRowbuf <= '0';
				aRowbuf <= 0;
				aRowbuf_vec <= (others => '0');
				dwrRowbuf <= (others => '0');
				enRowAbufB <= '0';
				enRowBbufB <= '0';
				weRowbufB <= '0';
				aRowbufB <= 0;
				aRowbufB_vec <= (others => '0');
				dwrRowbufB <= (others => '0');

				-- IP impl.op.syncrst --- END
				-- IP impl.op.syncrst.cust --- INSERT

			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;
