-- file Vsp_core.vhd
-- Vsp_core top_v1_0 top implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

-- module parameters:
-- aresetNNotP (external reset polarity): true
-- fAclk (root clock frequency [kHz]): 200000
-- aclkDiffNotSng (root clock endedness): false
-- clks (design clocks): mclk;pixrxclk;memclk
-- fClks (design clock frequencies [kHz]): 200000;100000;250000
-- clkIntNotExts (design clock origins): true;false;false
-- clkDiffNotSngs (design clock endednesses): false;false;false
-- aclkIntNotExt (root clock origin): false

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library efxphysicallib;
use efxphysicallib.efxcomponents.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Vsp_core is
	generic (
		fAclk: natural := 200000;
		fMclk: natural := 200000;
		fPixrxclk: natural := 100000;
		fMemclk: natural := 250000
	);
	port (
		aresetn: in std_logic;
		aclk: in std_logic;
		pixrxclk: in std_logic;
		memclk: in std_logic;
		resetnMemclk: out std_logic;
		probe: out std_logic_vector(5 downto 0);
		clk_byte_HS: in std_logic;
		cs: out std_logic;
		sclk: out std_logic;
		mosi: out std_logic;
		rgb0_r: out std_logic;
		rgb0_g: out std_logic;
		rgb0_b: out std_logic;
		rgb1_r: out std_logic;
		rgb1_g: out std_logic;
		rgb1_b: out std_logic;
		nslp: out std_logic;
		m0: out std_logic;
		m0z: out std_logic;
		m1: out std_logic;
		m1z: out std_logic;
		dir: out std_logic;
		step: out std_logic;

		apuAXIL_araddr: in std_logic_vector(31 downto 0);
		apuAXIL_arprot: in std_logic_vector(2 downto 0);
		apuAXIL_arready: out std_logic;
		apuAXIL_arvalid: in std_logic;

		apuAXIL_rdata: out std_logic_vector(31 downto 0);
		apuAXIL_rready: in std_logic;
		apuAXIL_rresp: out std_logic_vector(1 downto 0);
		apuAXIL_rvalid: out std_logic;
		apuAXIL_rlast: out std_logic;

		apuAXIL_awaddr: in std_logic_vector(31 downto 0);
		apuAXIL_awprot: in std_logic_vector(2 downto 0);
		apuAXIL_awready: out std_logic;
		apuAXIL_awvalid: in std_logic;

		apuAXIL_wdata: in std_logic_vector(31 downto 0);
		apuAXIL_wready: out std_logic;
		apuAXIL_wstrb: in std_logic_vector(3 downto 0);
		apuAXIL_wvalid: in std_logic;

		apuAXIL_bready: in std_logic;
		apuAXIL_bresp: out std_logic_vector(1 downto 0);
		apuAXIL_bvalid: out std_logic;

		ddrAXI_rready: out std_logic;
		ddrAXI_wvalid: out std_logic;

		mipirx_RESET_N: out std_logic;
		mipirx_RST0_N: out std_logic;
		mipirx_ERR_CONTROL_LAN0: in std_logic;
		mipirx_ERR_CONTROL_LAN1: in std_logic;
		mipirx_ERR_CONTROL_LAN2: in std_logic;
		mipirx_ERR_CONTROL_LAN3: in std_logic;
		mipirx_ERR_ESC_LAN0: in std_logic;
		mipirx_ERR_ESC_LAN1: in std_logic;
		mipirx_ERR_ESC_LAN2: in std_logic;
		mipirx_ERR_ESC_LAN3: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN0: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN1: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN2: in std_logic;
		mipirx_ERR_SOT_SYNC_HS_LAN3: in std_logic;
		mipirx_ESC_CLK_LAN0: in std_logic;
		mipirx_ESC_CLK_LAN1: in std_logic;
		mipirx_ESC_CLK_LAN2: in std_logic;
		mipirx_ESC_CLK_LAN3: in std_logic;
		mipirx_RX_DATA_HS_LAN0: in std_logic_vector(15 downto 0);
		mipirx_RX_DATA_HS_LAN1: in std_logic_vector(15 downto 0);
		mipirx_RX_DATA_HS_LAN2: in std_logic_vector(15 downto 0);
		mipirx_RX_DATA_HS_LAN3: in std_logic_vector(15 downto 0);
		mipirx_RX_SKEW_CAL_HS_LAN0: in std_logic;
		mipirx_RX_SKEW_CAL_HS_LAN1: in std_logic;
		mipirx_RX_SKEW_CAL_HS_LAN2: in std_logic;
		mipirx_RX_SKEW_CAL_HS_LAN3: in std_logic;
		mipirx_RX_SYNC_HS_LAN0: in std_logic;
		mipirx_RX_SYNC_HS_LAN1: in std_logic;
		mipirx_RX_SYNC_HS_LAN2: in std_logic;
		mipirx_RX_SYNC_HS_LAN3: in std_logic;
		mipirx_RX_ULPS_ACTIVE_CLK_NOT: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN0: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN1: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN2: in std_logic;
		mipirx_RX_ULPS_ACTIVE_NOT_LAN3: in std_logic;
		mipirx_RX_ULPS_CLK_NOT: in std_logic;
		mipirx_RX_ULPS_ESC_LAN0: in std_logic;
		mipirx_RX_ULPS_ESC_LAN1: in std_logic;
		mipirx_RX_ULPS_ESC_LAN2: in std_logic;
		mipirx_RX_ULPS_ESC_LAN3: in std_logic;
		mipirx_RX_VALID_HS_LAN0: in std_logic;
		mipirx_RX_VALID_HS_LAN1: in std_logic;
		mipirx_RX_VALID_HS_LAN2: in std_logic;
		mipirx_RX_VALID_HS_LAN3: in std_logic;
		mipirx_STOPSTATE_LAN0: in std_logic;
		mipirx_STOPSTATE_LAN1: in std_logic;
		mipirx_STOPSTATE_LAN2: in std_logic;
		mipirx_STOPSTATE_LAN3: in std_logic;

		scl_in: in std_logic;
		scl_out: out std_logic;
		scl_tri: out std_logic;

		sda_in: in std_logic;
		sda_out: out std_logic;
		sda_tri: out std_logic;

		ddrAXI_arid: out std_logic_vector(5 downto 0);
		ddrAXI_araddr: out std_logic_vector(32 downto 0);
		ddrAXI_arburst: out std_logic_vector(1 downto 0);
		ddrAXI_arcache: out std_logic_vector(3 downto 0);
		ddrAXI_arlen: out std_logic_vector(7 downto 0);
		ddrAXI_arlock: out std_logic_vector(0 downto 0);
		ddrAXI_arprot: out std_logic_vector(2 downto 0);
		ddrAXI_arqos: out std_logic_vector(3 downto 0);
		ddrAXI_arready: in std_logic;
		ddrAXI_arregion: out std_logic_vector(3 downto 0);
		ddrAXI_arsize: out std_logic_vector(2 downto 0);
		ddrAXI_arvalid: out std_logic;

		ddrAXI_rid: in std_logic_vector(5 downto 0);
		ddrAXI_rdata: in std_logic_vector(511 downto 0);
		ddrAXI_rlast: in std_logic;
		ddrAXI_rresp: in std_logic_vector(1 downto 0);
		ddrAXI_rvalid: in std_logic;

		ddrAXI_awid: out std_logic_vector(5 downto 0);
		ddrAXI_awaddr: out std_logic_vector(32 downto 0);
		ddrAXI_awburst: out std_logic_vector(1 downto 0);
		ddrAXI_awcache: out std_logic_vector(3 downto 0);
		ddrAXI_awlen: out std_logic_vector(7 downto 0);
		ddrAXI_awlock: out std_logic_vector(0 downto 0);
		ddrAXI_awprot: out std_logic_vector(2 downto 0);
		ddrAXI_awqos: out std_logic_vector(3 downto 0);
		ddrAXI_awready: in std_logic;
		ddrAXI_awregion: out std_logic_vector(3 downto 0);
		ddrAXI_awsize: out std_logic_vector(2 downto 0);
		ddrAXI_awvalid: out std_logic;

		ddrAXI_wdata: out std_logic_vector(511 downto 0);
		ddrAXI_wlast: out std_logic;
		ddrAXI_wready: in std_logic;
		ddrAXI_wstrb: out std_logic_vector(63 downto 0);

		ddrAXI_bid: in std_logic_vector(5 downto 0);
		ddrAXI_bready: out std_logic;
		ddrAXI_bresp: in std_logic_vector(1 downto 0);
		ddrAXI_bvalid: in std_logic
	);
end Vsp_core;

architecture Rtl of Vsp_core is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Camif is
		generic (
			fMclk: natural
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;
			resetPixrxclk: in std_logic;
			pixrxclk: in std_logic;
			tkclk: in std_logic;

			NRowRaw: in std_logic_vector(11 downto 0);
			NCol: in std_logic_vector(10 downto 0);

			toVideoinAXIS_tready: in std_logic;
			toVideoinAXIS_tvalid: out std_logic;
			toVideoinAXIS_tdata: out std_logic_vector(23 downto 0);
			toVideoinAXIS_tlast: out std_logic;

			reqInvConfig: in std_logic;
			ackInvConfig: out std_logic;

			configHdrNotFix: in std_logic_vector(7 downto 0);
			configSynthNotLive: in std_logic_vector(7 downto 0);

			reqInvConfigSynth: in std_logic;
			ackInvConfigSynth: out std_logic;

			configSynthTixVSynthmode: in std_logic_vector(7 downto 0);
			configSynthTFramepad: in std_logic_vector(15 downto 0);
			configSynthTLinepad: in std_logic_vector(7 downto 0);

			reqInvSetReg: in std_logic;
			ackInvSetReg: out std_logic;

			setRegAddr: in std_logic_vector(15 downto 0);
			setRegVal: in std_logic_vector(7 downto 0);

			reqInvGetReg: in std_logic;
			ackInvGetReg: out std_logic;

			getRegAddr: in std_logic_vector(15 downto 0);
			getRegVal: out std_logic_vector(7 downto 0);

			reqInvModReg: in std_logic;
			ackInvModReg: out std_logic;

			modRegAddr: in std_logic_vector(15 downto 0);
			modRegMask: in std_logic_vector(7 downto 0);
			modRegVal: in std_logic_vector(7 downto 0);

			reqInvSetCorereg: in std_logic;
			ackInvSetCorereg: out std_logic;

			setCoreregAddr: in std_logic_vector(7 downto 0);
			setCoreregVal: in std_logic_vector(31 downto 0);

			reqInvGetCorereg: in std_logic;
			ackInvGetCorereg: out std_logic;

			getCoreregAddr: in std_logic_vector(7 downto 0);
			getCoreregVal: out std_logic_vector(31 downto 0);

			rng: in std_logic;

			vsync: out std_logic;
			ixTExp: out std_logic_vector(3 downto 0);

			clk_byte_HS: in std_logic;

			mipirx_RESET_N: out std_logic;
			mipirx_RST0_N: out std_logic;
			mipirx_ERR_CONTROL_LAN0: in std_logic;
			mipirx_ERR_CONTROL_LAN1: in std_logic;
			mipirx_ERR_CONTROL_LAN2: in std_logic;
			mipirx_ERR_CONTROL_LAN3: in std_logic;
			mipirx_ERR_ESC_LAN0: in std_logic;
			mipirx_ERR_ESC_LAN1: in std_logic;
			mipirx_ERR_ESC_LAN2: in std_logic;
			mipirx_ERR_ESC_LAN3: in std_logic;
			mipirx_ERR_SOT_SYNC_HS_LAN0: in std_logic;
			mipirx_ERR_SOT_SYNC_HS_LAN1: in std_logic;
			mipirx_ERR_SOT_SYNC_HS_LAN2: in std_logic;
			mipirx_ERR_SOT_SYNC_HS_LAN3: in std_logic;
			mipirx_ESC_CLK_LAN0: in std_logic;
			mipirx_ESC_CLK_LAN1: in std_logic;
			mipirx_ESC_CLK_LAN2: in std_logic;
			mipirx_ESC_CLK_LAN3: in std_logic;
			mipirx_RX_DATA_HS_LAN0: in std_logic_vector(15 downto 0);
			mipirx_RX_DATA_HS_LAN1: in std_logic_vector(15 downto 0);
			mipirx_RX_DATA_HS_LAN2: in std_logic_vector(15 downto 0);
			mipirx_RX_DATA_HS_LAN3: in std_logic_vector(15 downto 0);
			mipirx_RX_SKEW_CAL_HS_LAN0: in std_logic;
			mipirx_RX_SKEW_CAL_HS_LAN1: in std_logic;
			mipirx_RX_SKEW_CAL_HS_LAN2: in std_logic;
			mipirx_RX_SKEW_CAL_HS_LAN3: in std_logic;
			mipirx_RX_SYNC_HS_LAN0: in std_logic;
			mipirx_RX_SYNC_HS_LAN1: in std_logic;
			mipirx_RX_SYNC_HS_LAN2: in std_logic;
			mipirx_RX_SYNC_HS_LAN3: in std_logic;
			mipirx_RX_ULPS_ACTIVE_CLK_NOT: in std_logic;
			mipirx_RX_ULPS_ACTIVE_NOT_LAN0: in std_logic;
			mipirx_RX_ULPS_ACTIVE_NOT_LAN1: in std_logic;
			mipirx_RX_ULPS_ACTIVE_NOT_LAN2: in std_logic;
			mipirx_RX_ULPS_ACTIVE_NOT_LAN3: in std_logic;
			mipirx_RX_ULPS_CLK_NOT: in std_logic;
			mipirx_RX_ULPS_ESC_LAN0: in std_logic;
			mipirx_RX_ULPS_ESC_LAN1: in std_logic;
			mipirx_RX_ULPS_ESC_LAN2: in std_logic;
			mipirx_RX_ULPS_ESC_LAN3: in std_logic;
			mipirx_RX_VALID_HS_LAN0: in std_logic;
			mipirx_RX_VALID_HS_LAN1: in std_logic;
			mipirx_RX_VALID_HS_LAN2: in std_logic;
			mipirx_RX_VALID_HS_LAN3: in std_logic;
			mipirx_STOPSTATE_LAN0: in std_logic;
			mipirx_STOPSTATE_LAN1: in std_logic;
			mipirx_STOPSTATE_LAN2: in std_logic;
			mipirx_STOPSTATE_LAN3: in std_logic;

			scl_in: in std_logic;
			scl_out: out std_logic;
			scl_tri: out std_logic;

			sda_in: in std_logic;
			sda_out: out std_logic;
			sda_tri: out std_logic;

			RxDataHS0: in std_logic_vector(15 downto 0);
			RxDataHS1: in std_logic_vector(15 downto 0);
			RxDataHS2: in std_logic_vector(15 downto 0);
			RxDataHS3: in std_logic_vector(15 downto 0);

			datatype_dbg: out std_logic_vector(5 downto 0);
			mipiAXIS_dbg: out std_logic_vector(3 downto 0);
			video_out_dbg: out std_logic_vector(3 downto 0);

			stateConfig_dbg: out std_logic_vector(7 downto 0)
		);
	end component;

	component Corner is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			vsync: in std_logic;
			NRow: in std_logic_vector(10 downto 0);
			NCol: in std_logic_vector(10 downto 0);

			grayFromVideoinAXIS_tready: out std_logic;
			grayFromVideoinAXIS_tvalid: in std_logic;
			grayFromVideoinAXIS_tdata: in std_logic_vector(71 downto 0);
			grayFromVideoinAXIS_tlast: in std_logic;

			reqInvAcquire: in std_logic;
			ackInvAcquire: out std_logic;

			reqInvConfig: in std_logic;
			ackInvConfig: out std_logic;

			configLinNotLog: in std_logic_vector(7 downto 0);
			configThd: in std_logic_vector(7 downto 0);
			configRow0: in std_logic_vector(15 downto 0);
			configRow1: in std_logic_vector(15 downto 0);
			configCol0: in std_logic_vector(15 downto 0);
			configCol1: in std_logic_vector(15 downto 0);

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTkst: out std_logic_vector(31 downto 0);
			getInfoScoreMin: out std_logic_vector(7 downto 0);
			getInfoScoreMax: out std_logic_vector(7 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);

			reqInvUnlock: in std_logic;
			ackInvUnlock: out std_logic;

			tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0);

			reqCoobufToHostif: in std_logic;
			ackCoobufToHostif: out std_logic;
			dneCoobufToHostif: in std_logic;
			avllenCoobufToHostif: out std_logic_vector(31 downto 0);

			coobufToHostifAXIS_tready: in std_logic;
			coobufToHostifAXIS_tvalid: out std_logic;
			coobufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			coobufToHostifAXIS_tlast: out std_logic
		);
	end component;

	component Cputrack is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			trigA: in std_logic;
			trigB: in std_logic;
			trigC: in std_logic;
			trigD: in std_logic;

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTCapt: out std_logic_vector(31 downto 0);
			getInfoPtr0Seqbuf: out std_logic_vector(15 downto 0);

			reqInvSelect: in std_logic;
			ackInvSelect: out std_logic;

			selectTixVCapture: in std_logic_vector(7 downto 0);
			selectStaTixVTrigger: in std_logic_vector(7 downto 0);
			selectStaFallingNotRising: in std_logic_vector(7 downto 0);
			selectStoTixVTrigger: in std_logic_vector(7 downto 0);
			selectStoFallingNotRising: in std_logic_vector(7 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);
			setTCaptMax: in std_logic_vector(31 downto 0);

			reqSeqbufToHostif: in std_logic;
			ackSeqbufToHostif: out std_logic;
			dneSeqbufToHostif: in std_logic;
			avllenSeqbufToHostif: out std_logic_vector(31 downto 0);

			seqbufToHostifAXIS_tready: in std_logic;
			seqbufToHostifAXIS_tvalid: out std_logic;
			seqbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			seqbufToHostifAXIS_tlast: out std_logic;

			hostifStateOp: in std_logic_vector(7 downto 0)
		);
	end component;

	component Ddrif is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			resetMemclk: in std_logic;
			memclk: in std_logic;

			tkclk: in std_logic;

			getStatsNRdA: out std_logic_vector(31 downto 0);
			getStatsNRdB: out std_logic_vector(31 downto 0);
			getStatsNWrA: out std_logic_vector(31 downto 0);
			getStatsNWrB: out std_logic_vector(31 downto 0);

			reqRdA: in std_logic;
			ackRdA: out std_logic;

			rdAAXI_araddr: in std_logic_vector(17 downto 0);
			rdAAXI_arready: out std_logic;
			rdAAXI_arvalid: in std_logic;
			rdAAXI_rdata: out std_logic_vector(127 downto 0);
			rdAAXI_rlast: out std_logic;
			rdAAXI_rready: in std_logic;
			rdAAXI_rresp: out std_logic_vector(1 downto 0);
			rdAAXI_rvalid: out std_logic;

			reqRdB: in std_logic;
			ackRdB: out std_logic;

			rdBAXI_araddr: in std_logic_vector(17 downto 0);
			rdBAXI_arready: out std_logic;
			rdBAXI_arvalid: in std_logic;
			rdBAXI_rdata: out std_logic_vector(127 downto 0);
			rdBAXI_rlast: out std_logic;
			rdBAXI_rready: in std_logic;
			rdBAXI_rresp: out std_logic_vector(1 downto 0);
			rdBAXI_rvalid: out std_logic;

			reqWrA: in std_logic;
			ackWrA: out std_logic;

			wrAAXI_awaddr: in std_logic_vector(17 downto 0);
			wrAAXI_awready: out std_logic;
			wrAAXI_awvalid: in std_logic;
			wrAAXI_wdata: in std_logic_vector(127 downto 0);
			wrAAXI_wlast: in std_logic;
			wrAAXI_wready: out std_logic;
			wrAAXI_wvalid: in std_logic;

			reqWrB: in std_logic;
			ackWrB: out std_logic;

			wrBAXI_awaddr: in std_logic_vector(17 downto 0);
			wrBAXI_awready: out std_logic;
			wrBAXI_awvalid: in std_logic;
			wrBAXI_wdata: in std_logic_vector(127 downto 0);
			wrBAXI_wlast: in std_logic;
			wrBAXI_wready: out std_logic;
			wrBAXI_wvalid: in std_logic;

			ddrAXI_arid: out std_logic_vector(5 downto 0);
			ddrAXI_araddr: out std_logic_vector(32 downto 0);
			ddrAXI_arburst: out std_logic_vector(1 downto 0);
			ddrAXI_arcache: out std_logic_vector(3 downto 0);
			ddrAXI_arlen: out std_logic_vector(7 downto 0);
			ddrAXI_arlock: out std_logic_vector(0 downto 0);
			ddrAXI_arprot: out std_logic_vector(2 downto 0);
			ddrAXI_arqos: out std_logic_vector(3 downto 0);
			ddrAXI_arready: in std_logic;
			ddrAXI_arregion: out std_logic_vector(3 downto 0);
			ddrAXI_arsize: out std_logic_vector(2 downto 0);
			ddrAXI_arvalid: out std_logic;

			ddrAXI_rid: in std_logic_vector(5 downto 0);
			ddrAXI_rdata: in std_logic_vector(511 downto 0);
			ddrAXI_rlast: in std_logic;
			ddrAXI_rready: out std_logic;
			ddrAXI_rresp: in std_logic_vector(1 downto 0);
			ddrAXI_rvalid: in std_logic;

			ddrAXI_awid: out std_logic_vector(5 downto 0);
			ddrAXI_awaddr: out std_logic_vector(32 downto 0);
			ddrAXI_awburst: out std_logic_vector(1 downto 0);
			ddrAXI_awcache: out std_logic_vector(3 downto 0);
			ddrAXI_awlen: out std_logic_vector(7 downto 0);
			ddrAXI_awlock: out std_logic_vector(0 downto 0);
			ddrAXI_awprot: out std_logic_vector(2 downto 0);
			ddrAXI_awqos: out std_logic_vector(3 downto 0);
			ddrAXI_awready: in std_logic;
			ddrAXI_awregion: out std_logic_vector(3 downto 0);
			ddrAXI_awsize: out std_logic_vector(2 downto 0);
			ddrAXI_awvalid: out std_logic;

			ddrAXI_wdata: out std_logic_vector(511 downto 0);
			ddrAXI_wlast: out std_logic;
			ddrAXI_wready: in std_logic;
			ddrAXI_wstrb: out std_logic_vector(63 downto 0);
			ddrAXI_wvalid: out std_logic;

			ddrAXI_bid: in std_logic_vector(5 downto 0);
			ddrAXI_bready: out std_logic;
			ddrAXI_bresp: in std_logic_vector(1 downto 0);
			ddrAXI_bvalid: in std_logic
		);
	end component;

	component Decim is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			vsync: in std_logic;
			ixTExp: in std_logic_vector(3 downto 0);

			NRow: in std_logic_vector(10 downto 0);
			NCol: in std_logic_vector(10 downto 0);

			grayFromVideoinAXIS_tready: out std_logic;
			grayFromVideoinAXIS_tvalid: in std_logic;
			grayFromVideoinAXIS_tdata: in std_logic_vector(71 downto 0);
			grayFromVideoinAXIS_tlast: in std_logic;

			rgbFromVideoinAXIS_tready: out std_logic;
			rgbFromVideoinAXIS_tvalid: in std_logic;
			rgbFromVideoinAXIS_tdata: in std_logic_vector(35 downto 0);
			rgbFromVideoinAXIS_tlast: in std_logic;

			reqInvAcquire: in std_logic;
			ackInvAcquire: out std_logic;

			acquireIxTExp: in std_logic_vector(7 downto 0);

			reqInvConfig: in std_logic;
			ackInvConfig: out std_logic;

			configRgbNotGray: in std_logic_vector(7 downto 0);
			configEdge: in std_logic_vector(7 downto 0);
			configEdge2: in std_logic_vector(15 downto 0);
			configNDecim: in std_logic_vector(15 downto 0);

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTkst: out std_logic_vector(31 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);

			reqInvUnlock: in std_logic;
			ackInvUnlock: out std_logic;

			tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0);

			reqPvwbufToHostif: in std_logic;
			ackPvwbufToHostif: out std_logic;
			dnePvwbufToHostif: in std_logic;
			avllenPvwbufToHostif: out std_logic_vector(31 downto 0);

			pvwbufToHostifAXIS_tready: in std_logic;
			pvwbufToHostifAXIS_tvalid: out std_logic;
			pvwbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			pvwbufToHostifAXIS_tlast: out std_logic;

			stateStore_dbg: out std_logic_vector(7 downto 0);
			stateStream_dbg: out std_logic_vector(7 downto 0)
		);
	end component;

	component Director is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			NRowRaw: out std_logic_vector(11 downto 0);
			NColRaw: out std_logic_vector(11 downto 0);

			rng: out std_logic;

			reqInvConfig: in std_logic;
			ackInvConfig: out std_logic;

			configNRowRaw: in std_logic_vector(15 downto 0);
			configNColRaw: in std_logic_vector(15 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0)
		);
	end component;

	component Freqprobe_v1_0 is
		generic (
			fMclk: natural := 50000
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;
			bcdNotHex: in std_logic;
			capt: in std_logic_vector(15 downto 0);
			freq: out std_logic
		);
	end component;

	component Hdreng is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			resetMemclk: in std_logic;
			memclk: in std_logic;

			hdrmemAXI_awaddr: out std_logic_vector(17 downto 0);
			hdrmemAXI_awready: in std_logic;
			hdrmemAXI_awvalid: out std_logic;
			hdrmemAXI_bready: out std_logic;
			hdrmemAXI_bresp: in std_logic_vector(1 downto 0);
			hdrmemAXI_bvalid: in std_logic;
			hdrmemAXI_wdata: out std_logic_vector(127 downto 0);
			hdrmemAXI_wlast: out std_logic;
			hdrmemAXI_wready: in std_logic;
			hdrmemAXI_wvalid: out std_logic;

			reqToDdrifWr: out std_logic;
			ackToDdrifWr: in std_logic;

			hdrmemAXI_araddr: out std_logic_vector(17 downto 0);
			hdrmemAXI_arready: in std_logic;
			hdrmemAXI_arvalid: out std_logic;
			hdrmemAXI_rdata: in std_logic_vector(127 downto 0);
			hdrmemAXI_rlast: in std_logic;
			hdrmemAXI_rready: out std_logic;
			hdrmemAXI_rresp: in std_logic_vector(1 downto 0);
			hdrmemAXI_rvalid: in std_logic;

			reqToDdrifRd: out std_logic;
			ackToDdrifRd: in std_logic;

			vsync: in std_logic;
			ixTExp: in std_logic_vector(3 downto 0);

			NRow: in std_logic_vector(10 downto 0);
			NCol: in std_logic_vector(10 downto 0);

			rgbFromVideoinAXIS_tready: out std_logic;
			rgbFromVideoinAXIS_tvalid: in std_logic;
			rgbFromVideoinAXIS_tdata: in std_logic_vector(35 downto 0);
			rgbFromVideoinAXIS_tlast: in std_logic;

			reqInvAssign: in std_logic;
			ackInvAssign: out std_logic;

			assignIxMem: in std_logic_vector(7 downto 0);

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTkst: out std_logic_vector(31 downto 0);
			getInfoIxMem: out std_logic_vector(7 downto 0);
			getInfoIxMemAcq: out std_logic_vector(7 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);

			tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0)
		);
	end component;

	component Hostif is
		generic (
			fMclk: natural := 50000
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;
			tkclk: in std_logic;
			commok: out std_logic;
			reqReset: out std_logic;

			identGetUnt: in std_logic_vector(95 downto 0);
			identGetVer: in std_logic_vector(63 downto 0);
			identGetHash: in std_logic_vector(63 downto 0);
			identGetWho: in std_logic_vector(63 downto 0);

			identGetCfgFMclk: in std_logic_vector(31 downto 0);
			identGetCfgFMemclk: in std_logic_vector(31 downto 0);

			reqInvCamifConfig: out std_logic;
			ackInvCamifConfig: in std_logic;

			camifConfigHdrNotFix: out std_logic_vector(7 downto 0);
			camifConfigSynthNotLive: out std_logic_vector(7 downto 0);

			reqInvCamifConfigSynth: out std_logic;
			ackInvCamifConfigSynth: in std_logic;

			camifConfigSynthTixVSynthmode: out std_logic_vector(7 downto 0);
			camifConfigSynthTFramepad: out std_logic_vector(15 downto 0);
			camifConfigSynthTLinepad: out std_logic_vector(7 downto 0);

			reqInvCamifSetReg: out std_logic;
			ackInvCamifSetReg: in std_logic;

			camifSetRegAddr: out std_logic_vector(15 downto 0);
			camifSetRegVal: out std_logic_vector(7 downto 0);

			reqInvCamifGetReg: out std_logic;
			ackInvCamifGetReg: in std_logic;

			camifGetRegAddr: out std_logic_vector(15 downto 0);
			camifGetRegVal: in std_logic_vector(7 downto 0);

			reqInvCamifModReg: out std_logic;
			ackInvCamifModReg: in std_logic;

			camifModRegAddr: out std_logic_vector(15 downto 0);
			camifModRegMask: out std_logic_vector(7 downto 0);
			camifModRegVal: out std_logic_vector(7 downto 0);

			reqInvCamifSetCorereg: out std_logic;
			ackInvCamifSetCorereg: in std_logic;

			camifSetCoreregAddr: out std_logic_vector(7 downto 0);
			camifSetCoreregVal: out std_logic_vector(31 downto 0);

			reqInvCamifGetCorereg: out std_logic;
			ackInvCamifGetCorereg: in std_logic;

			camifGetCoreregAddr: out std_logic_vector(7 downto 0);
			camifGetCoreregVal: in std_logic_vector(31 downto 0);

			reqInvCornerAcquire: out std_logic;
			ackInvCornerAcquire: in std_logic;

			reqInvCornerConfig: out std_logic;
			ackInvCornerConfig: in std_logic;

			cornerConfigLinNotLog: out std_logic_vector(7 downto 0);
			cornerConfigThd: out std_logic_vector(7 downto 0);
			cornerConfigRow0: out std_logic_vector(15 downto 0);
			cornerConfigRow1: out std_logic_vector(15 downto 0);
			cornerConfigCol0: out std_logic_vector(15 downto 0);
			cornerConfigCol1: out std_logic_vector(15 downto 0);

			cornerGetInfoTixVState: in std_logic_vector(7 downto 0);
			cornerGetInfoTkst: in std_logic_vector(31 downto 0);
			cornerGetInfoScoreMin: in std_logic_vector(7 downto 0);
			cornerGetInfoScoreMax: in std_logic_vector(7 downto 0);

			reqInvCornerSet: out std_logic;
			ackInvCornerSet: in std_logic;

			cornerSetRng: out std_logic_vector(7 downto 0);

			reqInvCornerUnlock: out std_logic;
			ackInvCornerUnlock: in std_logic;

			ddrifGetStatsNRdA: in std_logic_vector(31 downto 0);
			ddrifGetStatsNRdB: in std_logic_vector(31 downto 0);
			ddrifGetStatsNWrA: in std_logic_vector(31 downto 0);
			ddrifGetStatsNWrB: in std_logic_vector(31 downto 0);

			reqInvDecimAcquire: out std_logic;
			ackInvDecimAcquire: in std_logic;

			decimAcquireIxTExp: out std_logic_vector(7 downto 0);

			reqInvDecimConfig: out std_logic;
			ackInvDecimConfig: in std_logic;

			decimConfigRgbNotGray: out std_logic_vector(7 downto 0);
			decimConfigEdge: out std_logic_vector(7 downto 0);
			decimConfigEdge2: out std_logic_vector(15 downto 0);
			decimConfigNDecim: out std_logic_vector(15 downto 0);

			decimGetInfoTixVState: in std_logic_vector(7 downto 0);
			decimGetInfoTkst: in std_logic_vector(31 downto 0);

			reqInvDecimSet: out std_logic;
			ackInvDecimSet: in std_logic;

			decimSetRng: out std_logic_vector(7 downto 0);

			reqInvDecimUnlock: out std_logic;
			ackInvDecimUnlock: in std_logic;

			reqInvDirectorConfig: out std_logic;
			ackInvDirectorConfig: in std_logic;

			directorConfigNRowRaw: out std_logic_vector(15 downto 0);
			directorConfigNColRaw: out std_logic_vector(15 downto 0);

			reqInvDirectorSet: out std_logic;
			ackInvDirectorSet: in std_logic;

			directorSetRng: out std_logic_vector(7 downto 0);

			reqInvHdrengAssign: out std_logic;
			ackInvHdrengAssign: in std_logic;

			hdrengAssignIxMem: out std_logic_vector(7 downto 0);

			hdrengGetInfoTixVState: in std_logic_vector(7 downto 0);
			hdrengGetInfoTkst: in std_logic_vector(31 downto 0);
			hdrengGetInfoIxMem: in std_logic_vector(7 downto 0);
			hdrengGetInfoIxMemAcq: in std_logic_vector(7 downto 0);

			reqInvHdrengSet: out std_logic;
			ackInvHdrengSet: in std_logic;

			hdrengSetRng: out std_logic_vector(7 downto 0);

			reqInvLaserSet: out std_logic;
			ackInvLaserSet: in std_logic;

			laserSetL: out std_logic_vector(15 downto 0);
			laserSetR: out std_logic_vector(15 downto 0);

			reqInvRotaryConfig: out std_logic;
			ackInvRotaryConfig: in std_logic;

			rotaryConfigTixVStepmode: out std_logic_vector(7 downto 0);
			rotaryConfigTStep: out std_logic_vector(7 downto 0);

			rotaryGetInfoTixVState: in std_logic_vector(7 downto 0);
			rotaryGetInfoAngle: in std_logic_vector(15 downto 0);

			reqInvRotaryMoveto: out std_logic;
			ackInvRotaryMoveto: in std_logic;

			rotaryMovetoAngle: out std_logic_vector(15 downto 0);

			hshktrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);

			reqInvRotarySet: out std_logic;

			hshktrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);

			ackInvRotarySet: in std_logic;

			hshktrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);

			rotarySetRng: out std_logic_vector(7 downto 0);

			hshktrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

			rotarySetCcwNotCw: out std_logic_vector(7 downto 0);

			reqInvHshktrackSet: out std_logic;

			reqInvRotaryZero: out std_logic;

			ackInvHshktrackSet: in std_logic;

			ackInvRotaryZero: in std_logic;

			hshktrackSetRng: out std_logic_vector(7 downto 0);

			reqInvStepmuxSet: out std_logic;

			hshktrackSetTCaptMax: out std_logic_vector(31 downto 0);

			ackInvStepmuxSet: in std_logic;

			reqInvHshktrackSetMask: out std_logic;

			stepmuxSetLinNotRot: out std_logic_vector(7 downto 0);

			ackInvHshktrackSetMask: in std_logic;

			tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0);

			hshktrackSetMaskTixVCapture: out std_logic_vector(7 downto 0);

			reqInvTkclksrcSetTkst: out std_logic;

			reqInvMemtrackClearMask: out std_logic;

			ackInvTkclksrcSetTkst: in std_logic;

			ackInvMemtrackClearMask: in std_logic;

			tkclksrcSetTkstTkst: out std_logic_vector(31 downto 0);

			memtrackGetInfoTixVState: in std_logic_vector(7 downto 0);

			reqInvTraceAcquire: out std_logic;

			memtrackGetInfoTCapt: in std_logic_vector(31 downto 0);

			ackInvTraceAcquire: in std_logic;

			memtrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

			reqInvTraceConfig: out std_logic;

			reqInvMemtrackSelect: out std_logic;

			ackInvTraceConfig: in std_logic;

			ackInvMemtrackSelect: in std_logic;

			traceConfigTixVOrient: out std_logic_vector(7 downto 0);

			memtrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);

			traceConfigRow0: out std_logic_vector(15 downto 0);

			memtrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);

			traceConfigCol0: out std_logic_vector(15 downto 0);

			memtrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);

			traceGetInfoTixVState: in std_logic_vector(7 downto 0);

			memtrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

			traceGetInfoTkst: in std_logic_vector(31 downto 0);

			reqInvMemtrackSet: out std_logic;

			reqInvTraceUnlock: out std_logic;

			ackInvMemtrackSet: in std_logic;

			ackInvTraceUnlock: in std_logic;

			memtrackSetRng: out std_logic_vector(7 downto 0);

			cputrackGetInfoTixVState: in std_logic_vector(7 downto 0);

			memtrackSetTCaptMax: out std_logic_vector(31 downto 0);

			cputrackGetInfoTCapt: in std_logic_vector(31 downto 0);

			reqInvMemtrackSetMask: out std_logic;

			cputrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

			ackInvMemtrackSetMask: in std_logic;

			reqInvCputrackSelect: out std_logic;

			memtrackSetMaskTixVCapture: out std_logic_vector(7 downto 0);

			ackInvCputrackSelect: in std_logic;

			vidtrackGetInfoTixVState: in std_logic_vector(7 downto 0);

			cputrackSelectTixVCapture: out std_logic_vector(7 downto 0);

			vidtrackGetInfoTCapt: in std_logic_vector(31 downto 0);

			cputrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);

			vidtrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

			cputrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);

			reqInvVidtrackSelect: out std_logic;

			cputrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);

			ackInvVidtrackSelect: in std_logic;

			cputrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

			vidtrackSelectTixVCapture: out std_logic_vector(7 downto 0);

			reqInvCputrackSet: out std_logic;

			vidtrackSelectStaTixVTrigger: out std_logic_vector(7 downto 0);

			ackInvCputrackSet: in std_logic;

			vidtrackSelectStaFallingNotRising: out std_logic_vector(7 downto 0);

			cputrackSetRng: out std_logic_vector(7 downto 0);

			vidtrackSelectStoTixVTrigger: out std_logic_vector(7 downto 0);

			cputrackSetTCaptMax: out std_logic_vector(31 downto 0);

			vidtrackSelectStoFallingNotRising: out std_logic_vector(7 downto 0);

			reqInvHshktrackClearMask: out std_logic;

			reqInvVidtrackSet: out std_logic;

			ackInvHshktrackClearMask: in std_logic;

			ackInvVidtrackSet: in std_logic;

			hshktrackGetInfoTixVState: in std_logic_vector(7 downto 0);

			vidtrackSetRng: out std_logic_vector(7 downto 0);

			hshktrackGetInfoTCapt: in std_logic_vector(31 downto 0);

			vidtrackSetTCaptMax: out std_logic_vector(31 downto 0);

			hshktrackGetInfoPtr0Seqbuf: in std_logic_vector(15 downto 0);

			reqInvHshktrackSelect: out std_logic;
			ackInvHshktrackSelect: in std_logic;

			reqPvwbufFromDecim: out std_logic;
			ackPvwbufFromDecim: in std_logic;
			dnePvwbufFromDecim: out std_logic;
			avllenPvwbufFromDecim: in std_logic_vector(31 downto 0);

			pvwbufFromDecimAXIS_tready: out std_logic;
			pvwbufFromDecimAXIS_tvalid: in std_logic;
			pvwbufFromDecimAXIS_tdata: in std_logic_vector(31 downto 0);
			pvwbufFromDecimAXIS_tlast: in std_logic;

			reqCoobufFromCorner: out std_logic;
			ackCoobufFromCorner: in std_logic;
			dneCoobufFromCorner: out std_logic;
			avllenCoobufFromCorner: in std_logic_vector(31 downto 0);

			reqFlgbufFromTrace: out std_logic;
			ackFlgbufFromTrace: in std_logic;

			coobufFromCornerAXIS_tready: out std_logic;
			coobufFromCornerAXIS_tvalid: in std_logic;
			coobufFromCornerAXIS_tdata: in std_logic_vector(31 downto 0);
			coobufFromCornerAXIS_tlast: in std_logic;

			dneFlgbufFromTrace: out std_logic;
			avllenFlgbufFromTrace: in std_logic_vector(31 downto 0);

			flgbufFromTraceAXIS_tready: out std_logic;
			flgbufFromTraceAXIS_tvalid: in std_logic;
			flgbufFromTraceAXIS_tdata: in std_logic_vector(31 downto 0);
			flgbufFromTraceAXIS_tlast: in std_logic;

			reqSeqbufFromCputrack: out std_logic;
			ackSeqbufFromCputrack: in std_logic;
			dneSeqbufFromCputrack: out std_logic;
			avllenSeqbufFromCputrack: in std_logic_vector(31 downto 0);

			seqbufFromCputrackAXIS_tready: out std_logic;
			seqbufFromCputrackAXIS_tvalid: in std_logic;
			seqbufFromCputrackAXIS_tdata: in std_logic_vector(31 downto 0);
			seqbufFromCputrackAXIS_tlast: in std_logic;

			reqSeqbufFromHshktrack: out std_logic;
			ackSeqbufFromHshktrack: in std_logic;
			dneSeqbufFromHshktrack: out std_logic;
			avllenSeqbufFromHshktrack: in std_logic_vector(31 downto 0);

			reqSeqbufFromMemtrack: out std_logic;
			ackSeqbufFromMemtrack: in std_logic;
			dneSeqbufFromMemtrack: out std_logic;
			avllenSeqbufFromMemtrack: in std_logic_vector(31 downto 0);

			seqbufFromHshktrackAXIS_tready: out std_logic;
			seqbufFromHshktrackAXIS_tvalid: in std_logic;
			seqbufFromHshktrackAXIS_tdata: in std_logic_vector(31 downto 0);
			seqbufFromHshktrackAXIS_tlast: in std_logic;

			seqbufFromMemtrackAXIS_tready: out std_logic;

			reqSeqbufFromVidtrack: out std_logic;
			ackSeqbufFromVidtrack: in std_logic;
			dneSeqbufFromVidtrack: out std_logic;
			avllenSeqbufFromVidtrack: in std_logic_vector(31 downto 0);

			seqbufFromMemtrackAXIS_tvalid: in std_logic;
			seqbufFromMemtrackAXIS_tdata: in std_logic_vector(31 downto 0);
			seqbufFromMemtrackAXIS_tlast: in std_logic;

			seqbufFromVidtrackAXIS_tready: out std_logic;
			seqbufFromVidtrackAXIS_tvalid: in std_logic;
			seqbufFromVidtrackAXIS_tdata: in std_logic_vector(31 downto 0);
			seqbufFromVidtrackAXIS_tlast: in std_logic;

			AXIL_araddr: in std_logic_vector(31 downto 0);
			AXIL_arprot: in std_logic_vector(2 downto 0);
			AXIL_arready: out std_logic;
			AXIL_arvalid: in std_logic;
			AXIL_rdata: out std_logic_vector(31 downto 0);
			AXIL_rready: in std_logic;
			AXIL_rresp: out std_logic_vector(1 downto 0);
			AXIL_rvalid: out std_logic;
			AXIL_rlast: out std_logic;
			AXIL_awaddr: in std_logic_vector(31 downto 0);
			AXIL_awprot: in std_logic_vector(2 downto 0);
			AXIL_awready: out std_logic;
			AXIL_awvalid: in std_logic;
			AXIL_wdata: in std_logic_vector(31 downto 0);
			AXIL_wready: out std_logic;
			AXIL_wstrb: in std_logic_vector(3 downto 0);
			AXIL_wvalid: in std_logic;
			AXIL_bready: in std_logic;
			AXIL_bresp: out std_logic_vector(1 downto 0);
			AXIL_bvalid: out std_logic;

			stateOp_dbg: out std_logic_vector(7 downto 0)
		);
	end component;

	component Hshktrack is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			trigA: in std_logic;
			trigB: in std_logic;
			trigC: in std_logic;
			trigD: in std_logic;

			reqInvClearMask: in std_logic;
			ackInvClearMask: out std_logic;

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTCapt: out std_logic_vector(31 downto 0);
			getInfoPtr0Seqbuf: out std_logic_vector(15 downto 0);

			reqInvSelect: in std_logic;
			ackInvSelect: out std_logic;

			selectStaTixVTrigger: in std_logic_vector(7 downto 0);
			selectStaFallingNotRising: in std_logic_vector(7 downto 0);
			selectStoTixVTrigger: in std_logic_vector(7 downto 0);
			selectStoFallingNotRising: in std_logic_vector(7 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);
			setTCaptMax: in std_logic_vector(31 downto 0);

			reqInvSetMask: in std_logic;
			ackInvSetMask: out std_logic;

			setMaskTixVCapture: in std_logic_vector(7 downto 0);

			reqSeqbufToHostif: in std_logic;
			ackSeqbufToHostif: out std_logic;
			dneSeqbufToHostif: in std_logic;
			avllenSeqbufToHostif: out std_logic_vector(31 downto 0);

			seqbufToHostifAXIS_tready: in std_logic;
			seqbufToHostifAXIS_tvalid: out std_logic;
			seqbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			seqbufToHostifAXIS_tlast: out std_logic;

			vsync: in std_logic;
			cornerGetInfoTixVState: in std_logic_vector(1 downto 0);
			reqInvRotarySet: in std_logic;
			rotaryToStepmuxStep: in std_logic
		);
	end component;

	component Ident is
		generic (
			fMclk: natural := 0;
			fMemclk: natural := 0
		);
		port (
			getUnt: out std_logic_vector(95 downto 0);
			getVer: out std_logic_vector(63 downto 0);
			getHash: out std_logic_vector(63 downto 0);
			getWho: out std_logic_vector(63 downto 0);

			getCfgFMclk: out std_logic_vector(31 downto 0);
			getCfgFMemclk: out std_logic_vector(31 downto 0)
		);
	end component;

	component Laser is
		generic (
			fMclk: natural := 50000
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setL: in std_logic_vector(15 downto 0);
			setR: in std_logic_vector(15 downto 0);

			nss: out std_logic;
			sclk: out std_logic;
			mosi: out std_logic
		);
	end component;

	component Linear is
		port (
			reset: in std_logic;
			mclk: in std_logic;
			toStepmuxNslp: out std_logic;
			toStepmuxM0: out std_logic;
			toStepmuxM0z: out std_logic;
			toStepmuxM1: out std_logic;
			toStepmuxDir: out std_logic;
			toStepmuxStep: out std_logic
		);
	end component;

	component Memtrack is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			resetMemclk: in std_logic;
			memclk: in std_logic;

			vsync: in std_logic;
			rgbVideoinToManyAXIS_tlast: in std_logic;

			reqInvClearMask: in std_logic;
			ackInvClearMask: out std_logic;

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTCapt: out std_logic_vector(31 downto 0);
			getInfoPtr0Seqbuf: out std_logic_vector(15 downto 0);

			reqInvSelect: in std_logic;
			ackInvSelect: out std_logic;

			selectStaTixVTrigger: in std_logic_vector(7 downto 0);
			selectStaFallingNotRising: in std_logic_vector(7 downto 0);
			selectStoTixVTrigger: in std_logic_vector(7 downto 0);
			selectStoFallingNotRising: in std_logic_vector(7 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);
			setTCaptMax: in std_logic_vector(31 downto 0);

			reqInvSetMask: in std_logic;
			ackInvSetMask: out std_logic;

			setMaskTixVCapture: in std_logic_vector(7 downto 0);

			reqSeqbufToHostif: in std_logic;
			ackSeqbufToHostif: out std_logic;
			dneSeqbufToHostif: in std_logic;
			avllenSeqbufToHostif: out std_logic_vector(31 downto 0);

			seqbufToHostifAXIS_tready: in std_logic;
			seqbufToHostifAXIS_tvalid: out std_logic;
			seqbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			seqbufToHostifAXIS_tlast: out std_logic;

			reqHdrengToDdrifRd: in std_logic;
			ackHdrengToDdrifRd: in std_logic;
			reqHdrengToDdrifWr: in std_logic;
			ackHdrengToDdrifWr: in std_logic;
			ddrAXI_rvalid: in std_logic;
			ddrAXI_rready_sig: in std_logic;
			ddrAXI_wready: in std_logic;
			ddrAXI_bvalid: in std_logic;
			ddrAXI_wvalid_sig: in std_logic
		);
	end component;

	component Render is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			resetMemclk: in std_logic;
			memclk: in std_logic;

			rndmemAXI_awaddr: out std_logic_vector(17 downto 0);
			rndmemAXI_awready: in std_logic;
			rndmemAXI_awvalid: out std_logic;
			rndmemAXI_wdata: out std_logic_vector(127 downto 0);
			rndmemAXI_wlast: out std_logic;
			rndmemAXI_wready: in std_logic;
			rndmemAXI_wvalid: out std_logic;

			reqToDdrifWr: out std_logic;
			ackToDdrifWr: in std_logic;

			rndmemAXI_araddr: out std_logic_vector(17 downto 0);
			rndmemAXI_arready: in std_logic;
			rndmemAXI_arvalid: out std_logic;
			rndmemAXI_rdata: in std_logic_vector(127 downto 0);
			rndmemAXI_rlast: in std_logic;
			rndmemAXI_rready: out std_logic;
			rndmemAXI_rresp: in std_logic_vector(1 downto 0);
			rndmemAXI_rvalid: in std_logic;

			reqToDdrifRd: out std_logic;
			ackToDdrifRd: in std_logic
		);
	end component;

	component Rgbled_v1_0 is
		generic (
			fMclk: natural := 50000
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;
			rgb: in std_logic_vector(23 downto 0);

			r: out std_logic;
			g: out std_logic;
			b: out std_logic
		);
	end component;

	component Rotary is
		port (
			reset: in std_logic;
			mclk: in std_logic;
			tkclk: in std_logic;

			toStepmuxNslp: out std_logic;
			toStepmuxM0: out std_logic;
			toStepmuxM0z: out std_logic;
			toStepmuxM1: out std_logic;
			toStepmuxDir: out std_logic;
			toStepmuxStep: out std_logic;

			reqInvConfig: in std_logic;
			ackInvConfig: out std_logic;

			configTixVStepmode: in std_logic_vector(7 downto 0);
			configTStep: in std_logic_vector(7 downto 0);

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoAngle: out std_logic_vector(15 downto 0);

			reqInvMoveto: in std_logic;
			ackInvMoveto: out std_logic;

			movetoAngle: in std_logic_vector(15 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);
			setCcwNotCw: in std_logic_vector(7 downto 0);

			reqInvZero: in std_logic;
			ackInvZero: out std_logic
		);
	end component;

	component State is
		port (
			reset: in std_logic;
			mclk: in std_logic;
			tkclk: in std_logic;
			commok: in std_logic;
			rng: in std_logic;
			rgb: out std_logic_vector(23 downto 0)
		);
	end component;

	component Stepmux is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			fromLinearNslp: in std_logic;
			fromLinearM0: in std_logic;
			fromLinearM0z: in std_logic;
			fromLinearM1: in std_logic;
			fromLinearDir: in std_logic;
			fromLinearStep: in std_logic;

			fromRotaryNslp: in std_logic;
			fromRotaryM0: in std_logic;
			fromRotaryM0z: in std_logic;
			fromRotaryM1: in std_logic;
			fromRotaryDir: in std_logic;
			fromRotaryStep: in std_logic;

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setLinNotRot: in std_logic_vector(7 downto 0);

			nslp: out std_logic;

			m0: out std_logic;
			m0z: out std_logic;

			m1: out std_logic;
			m1z: out std_logic;

			dir: out std_logic;
			step: out std_logic
		);
	end component;

	component Tkclksrc_Easy_v1_0 is
		generic (
			fMclk: natural := 50000
		);
		port (
			reset: in std_logic;
			mclk: in std_logic;
			tkclk: out std_logic;

			getTkstTkst: out std_logic_vector(31 downto 0);

			reqInvSetTkst: in std_logic;
			ackInvSetTkst: out std_logic;

			setTkstTkst: in std_logic_vector(31 downto 0);

			stateOp_dbg: out std_logic_vector(7 downto 0)
		);
	end component;

	component Trace is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			vsync: in std_logic;
			ixTExp: in std_logic_vector(3 downto 0);

			NRow: in std_logic_vector(10 downto 0);
			NCol: in std_logic_vector(10 downto 0);

			rgbFromVideoinAXIS_tready: out std_logic;
			rgbFromVideoinAXIS_tvalid: in std_logic;
			rgbFromVideoinAXIS_tdata: in std_logic_vector(35 downto 0);
			rgbFromVideoinAXIS_tlast: in std_logic;

			tkclksrcGetTkstTkst: in std_logic_vector(31 downto 0);

			reqInvAcquire: in std_logic;
			ackInvAcquire: out std_logic;

			reqInvConfig: in std_logic;
			ackInvConfig: out std_logic;

			configTixVOrient: in std_logic_vector(7 downto 0);
			configRow0: in std_logic_vector(15 downto 0);
			configCol0: in std_logic_vector(15 downto 0);

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTkst: out std_logic_vector(31 downto 0);

			reqInvUnlock: in std_logic;
			ackInvUnlock: out std_logic;

			reqFlgbufToHostif: in std_logic;
			ackFlgbufToHostif: out std_logic;
			dneFlgbufToHostif: in std_logic;
			avllenFlgbufToHostif: out std_logic_vector(31 downto 0);

			flgbufToHostifAXIS_tready: in std_logic;
			flgbufToHostifAXIS_tvalid: out std_logic;
			flgbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			flgbufToHostifAXIS_tlast: out std_logic
		);
	end component;

	component Vecrend is
		port (
			reset: in std_logic;
			mclk: in std_logic
		);
	end component;

	component Videoin is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			fromCamifAXIS_tready: out std_logic;
			fromCamifAXIS_tvalid: in std_logic;
			fromCamifAXIS_tdata: in std_logic_vector(23 downto 0);
			fromCamifAXIS_tlast: in std_logic;

			vsync: in std_logic;
			NCol: in std_logic_vector(10 downto 0);

			grayToManyAXIS_tready: in std_logic;
			grayToManyAXIS_tvalid: out std_logic;
			grayToManyAXIS_tdata: out std_logic_vector(71 downto 0);
			grayToManyAXIS_tlast: out std_logic;

			rgbToManyAXIS_tready: in std_logic;
			rgbToManyAXIS_tvalid: out std_logic;
			rgbToManyAXIS_tdata: out std_logic_vector(35 downto 0);
			rgbToManyAXIS_tlast: out std_logic;

			stateIgr_dbg: out std_logic_vector(7 downto 0);
			stateRgbegr_dbg: out std_logic_vector(7 downto 0)
		);
	end component;

	component Vidtrack is
		port (
			reset: in std_logic;
			mclk: in std_logic;

			trigA: in std_logic;
			trigB: in std_logic;
			trigC: in std_logic;
			trigD: in std_logic;

			getInfoTixVState: out std_logic_vector(7 downto 0);
			getInfoTCapt: out std_logic_vector(31 downto 0);
			getInfoPtr0Seqbuf: out std_logic_vector(15 downto 0);

			reqInvSelect: in std_logic;
			ackInvSelect: out std_logic;

			selectTixVCapture: in std_logic_vector(7 downto 0);
			selectStaTixVTrigger: in std_logic_vector(7 downto 0);
			selectStaFallingNotRising: in std_logic_vector(7 downto 0);
			selectStoTixVTrigger: in std_logic_vector(7 downto 0);
			selectStoFallingNotRising: in std_logic_vector(7 downto 0);

			reqInvSet: in std_logic;
			ackInvSet: out std_logic;

			setRng: in std_logic_vector(7 downto 0);
			setTCaptMax: in std_logic_vector(31 downto 0);

			reqSeqbufToHostif: in std_logic;
			ackSeqbufToHostif: out std_logic;
			dneSeqbufToHostif: in std_logic;
			avllenSeqbufToHostif: out std_logic_vector(31 downto 0);

			seqbufToHostifAXIS_tready: in std_logic;
			seqbufToHostifAXIS_tvalid: out std_logic;
			seqbufToHostifAXIS_tdata: out std_logic_vector(31 downto 0);
			seqbufToHostifAXIS_tlast: out std_logic;

			videoinStateIgr: in std_logic_vector(7 downto 0);
			videoinStateRgbegr: in std_logic_vector(7 downto 0);
			decimStateStream: in std_logic_vector(7 downto 0);
			decimStateStore: in std_logic_vector(7 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- mclk wiring and reset (mclk)
	type stateMclk_t is (
		stateMclkReset,
		stateMclkRun
	);
	signal stateMclk: stateMclk_t;

	signal reset: std_logic;
	signal mclk: std_logic;

	-- IP sigs.mclk.cust --- INSERT

	---- memclk wiring and reset (memclk)
	type stateMemclk_t is (
		stateMemclkReset,
		stateMemclkRun
	);
	signal stateMemclk: stateMemclk_t;

	signal resetMemclk: std_logic;

	signal reset_memclk: std_logic;
	signal reset_to_memclkm1: std_logic;
	signal reset_to_memclkm2: std_logic;

	-- IP sigs.memclk.cust --- INSERT

	---- pixrxclk wiring and reset (pixrxclk)
	type statePixrxclk_t is (
		statePixrxclkReset,
		statePixrxclkRun
	);
	signal statePixrxclk: statePixrxclk_t;

	signal resetPixrxclk: std_logic;

	signal reset_pixrxclk: std_logic;
	signal reset_to_pixrxclkm1: std_logic;
	signal reset_to_pixrxclkm2: std_logic;

	-- IP sigs.pixrxclk.cust --- INSERT

	---- myCamif
	signal camifGetRegVal: std_logic_vector(7 downto 0);

	signal camifGetCoreregVal: std_logic_vector(31 downto 0);

	signal camifToVideoinAXIS_tvalid: std_logic;
	signal camifToVideoinAXIS_tdata: std_logic_vector(23 downto 0);
	signal camifToVideoinAXIS_tlast: std_logic;

	signal vsync: std_logic;
	signal ixTExp: std_logic_vector(3 downto 0);

	signal camifDatatype_dbg: std_logic_vector(5 downto 0);
	signal camifMipiAXIS_dbg: std_logic_vector(3 downto 0);
	signal camifVideo_out_dbg: std_logic_vector(3 downto 0);

	signal camifStateConfig_dbg: std_logic_vector(7 downto 0);

	---- myCorner
	signal avllenCoobufCornerToHostif: std_logic_vector(31 downto 0);

	signal coobufCornerToHostifAXIS_tvalid: std_logic;
	signal coobufCornerToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal coobufCornerToHostifAXIS_tlast: std_logic;

	signal cornerGetInfoTixVState: std_logic_vector(7 downto 0);
	signal cornerGetInfoTkst: std_logic_vector(31 downto 0);
	signal cornerGetInfoScoreMin: std_logic_vector(7 downto 0);
	signal cornerGetInfoScoreMax: std_logic_vector(7 downto 0);

	---- myCputrack
	signal avllenSeqbufCputrackToHostif: std_logic_vector(31 downto 0);

	signal seqbufCputrackToHostifAXIS_tvalid: std_logic;
	signal seqbufCputrackToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal seqbufCputrackToHostifAXIS_tlast: std_logic;

	signal cputrackGetInfoTixVState: std_logic_vector(7 downto 0);
	signal cputrackGetInfoTCapt: std_logic_vector(31 downto 0);
	signal cputrackGetInfoPtr0Seqbuf: std_logic_vector(15 downto 0);

	---- myDdrif
	signal hdrmemAXI_arready: std_logic;
	signal hdrmemAXI_rdata: std_logic_vector(127 downto 0);
	signal hdrmemAXI_rlast: std_logic;
	signal hdrmemAXI_rresp: std_logic_vector(1 downto 0);
	signal hdrmemAXI_rvalid: std_logic;

	signal hdrmemAXI_awready: std_logic;
	signal hdrmemAXI_bresp: std_logic_vector(1 downto 0);
	signal hdrmemAXI_bvalid: std_logic;
	signal hdrmemAXI_wready: std_logic;

	signal rndmemAXI_arready: std_logic;
	signal rndmemAXI_rdata: std_logic_vector(127 downto 0);
	signal rndmemAXI_rlast: std_logic;
	signal rndmemAXI_rresp: std_logic_vector(1 downto 0);
	signal rndmemAXI_rvalid: std_logic;

	signal rndmemAXI_awready: std_logic;
	signal rndmemAXI_bresp: std_logic_vector(1 downto 0);
	signal rndmemAXI_bvalid: std_logic;
	signal rndmemAXI_wready: std_logic;

	signal ddrifGetStatsNRdA: std_logic_vector(31 downto 0);
	signal ddrifGetStatsNRdB: std_logic_vector(31 downto 0);
	signal ddrifGetStatsNWrA: std_logic_vector(31 downto 0);
	signal ddrifGetStatsNWrB: std_logic_vector(31 downto 0);

	signal ddrAXI_rready_sig: std_logic;
	signal ddrAXI_wvalid_sig: std_logic;

	---- myDecim
	signal avllenPvwbufDecimToHostif: std_logic_vector(31 downto 0);

	signal pvwbufDecimToHostifAXIS_tvalid: std_logic;
	signal pvwbufDecimToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal pvwbufDecimToHostifAXIS_tlast: std_logic;

	signal decimGetInfoTixVState: std_logic_vector(7 downto 0);
	signal decimGetInfoTkst: std_logic_vector(31 downto 0);

	signal decimStateStore_dbg: std_logic_vector(7 downto 0);
	signal decimStateStream_dbg: std_logic_vector(7 downto 0);

	---- myDirector
	signal rng: std_logic;

	signal NRowRaw: std_logic_vector(11 downto 0);
	signal NColRaw: std_logic_vector(11 downto 0);

	---- myFreqprobeDbg0
	signal freqDbg0: std_logic;

	---- myFreqprobeDbg1
	signal freqDbg1: std_logic;

	---- myGbufceAclk
	signal aclk_sig: std_logic;

	---- myHdreng
	signal hdrmemAXI_araddr: std_logic_vector(17 downto 0);
	signal hdrmemAXI_arvalid: std_logic;
	signal hdrmemAXI_rready: std_logic;

	signal hdrmemAXI_awaddr: std_logic_vector(17 downto 0);
	signal hdrmemAXI_awvalid: std_logic;
	signal hdrmemAXI_bready: std_logic;
	signal hdrmemAXI_wdata: std_logic_vector(127 downto 0);
	signal hdrmemAXI_wlast: std_logic;
	signal hdrmemAXI_wvalid: std_logic;

	signal hdrengGetInfoTixVState: std_logic_vector(7 downto 0);
	signal hdrengGetInfoTkst: std_logic_vector(31 downto 0);
	signal hdrengGetInfoIxMem: std_logic_vector(7 downto 0);
	signal hdrengGetInfoIxMemAcq: std_logic_vector(7 downto 0);

	---- myHostif
	signal commok: std_logic;

	signal pvwbufDecimToHostifAXIS_tready: std_logic;

	signal coobufCornerToHostifAXIS_tready: std_logic;

	signal flgbufTraceToHostifAXIS_tready: std_logic;

	signal camifConfigHdrNotFix: std_logic_vector(7 downto 0);
	signal camifConfigSynthNotLive: std_logic_vector(7 downto 0);

	signal camifConfigSynthTixVSynthmode: std_logic_vector(7 downto 0);
	signal camifConfigSynthTFramepad: std_logic_vector(15 downto 0);
	signal camifConfigSynthTLinepad: std_logic_vector(7 downto 0);

	signal seqbufCputrackToHostifAXIS_tready: std_logic;

	signal camifSetRegAddr: std_logic_vector(15 downto 0);

	signal seqbufHshktrackToHostifAXIS_tready: std_logic;

	signal camifSetRegVal: std_logic_vector(7 downto 0);

	signal seqbufMemtrackToHostifAXIS_tready: std_logic;

	signal camifGetRegAddr: std_logic_vector(15 downto 0);

	signal camifModRegAddr: std_logic_vector(15 downto 0);
	signal camifModRegMask: std_logic_vector(7 downto 0);
	signal camifModRegVal: std_logic_vector(7 downto 0);

	signal seqbufVidtrackToHostifAXIS_tready: std_logic;

	signal camifSetCoreregAddr: std_logic_vector(7 downto 0);
	signal camifSetCoreregVal: std_logic_vector(31 downto 0);

	signal camifGetCoreregAddr: std_logic_vector(7 downto 0);

	signal cornerConfigLinNotLog: std_logic_vector(7 downto 0);
	signal cornerConfigThd: std_logic_vector(7 downto 0);
	signal cornerConfigRow0: std_logic_vector(15 downto 0);
	signal cornerConfigRow1: std_logic_vector(15 downto 0);
	signal cornerConfigCol0: std_logic_vector(15 downto 0);
	signal cornerConfigCol1: std_logic_vector(15 downto 0);

	signal cornerSetRng: std_logic_vector(7 downto 0);

	signal decimAcquireIxTExp: std_logic_vector(7 downto 0);

	signal decimConfigRgbNotGray: std_logic_vector(7 downto 0);
	signal decimConfigEdge: std_logic_vector(7 downto 0);
	signal decimConfigEdge2: std_logic_vector(15 downto 0);
	signal decimConfigNDecim: std_logic_vector(15 downto 0);

	signal decimSetRng: std_logic_vector(7 downto 0);

	signal directorConfigNRowRaw: std_logic_vector(15 downto 0);
	signal directorConfigNColRaw: std_logic_vector(15 downto 0);

	signal directorSetRng: std_logic_vector(7 downto 0);

	signal hdrengAssignIxMem: std_logic_vector(7 downto 0);

	signal hdrengSetRng: std_logic_vector(7 downto 0);

	signal laserSetL: std_logic_vector(15 downto 0);
	signal laserSetR: std_logic_vector(15 downto 0);

	signal rotaryConfigTixVStepmode: std_logic_vector(7 downto 0);
	signal rotaryConfigTStep: std_logic_vector(7 downto 0);

	signal rotaryMovetoAngle: std_logic_vector(15 downto 0);

	signal rotarySetRng: std_logic_vector(7 downto 0);
	signal rotarySetCcwNotCw: std_logic_vector(7 downto 0);

	signal stepmuxSetLinNotRot: std_logic_vector(7 downto 0);

	signal tkclksrcSetTkstTkst: std_logic_vector(31 downto 0);

	signal traceConfigTixVOrient: std_logic_vector(7 downto 0);
	signal traceConfigRow0: std_logic_vector(15 downto 0);
	signal traceConfigCol0: std_logic_vector(15 downto 0);

	signal cputrackSelectTixVCapture: std_logic_vector(7 downto 0);
	signal cputrackSelectStaTixVTrigger: std_logic_vector(7 downto 0);
	signal cputrackSelectStaFallingNotRising: std_logic_vector(7 downto 0);
	signal cputrackSelectStoTixVTrigger: std_logic_vector(7 downto 0);
	signal cputrackSelectStoFallingNotRising: std_logic_vector(7 downto 0);

	signal cputrackSetRng: std_logic_vector(7 downto 0);
	signal cputrackSetTCaptMax: std_logic_vector(31 downto 0);

	signal hshktrackSelectStaTixVTrigger: std_logic_vector(7 downto 0);
	signal hshktrackSelectStaFallingNotRising: std_logic_vector(7 downto 0);
	signal hshktrackSelectStoTixVTrigger: std_logic_vector(7 downto 0);
	signal hshktrackSelectStoFallingNotRising: std_logic_vector(7 downto 0);

	signal hshktrackSetRng: std_logic_vector(7 downto 0);
	signal hshktrackSetTCaptMax: std_logic_vector(31 downto 0);

	signal hshktrackSetMaskTixVCapture: std_logic_vector(7 downto 0);

	signal memtrackSelectStaTixVTrigger: std_logic_vector(7 downto 0);
	signal memtrackSelectStaFallingNotRising: std_logic_vector(7 downto 0);
	signal memtrackSelectStoTixVTrigger: std_logic_vector(7 downto 0);
	signal memtrackSelectStoFallingNotRising: std_logic_vector(7 downto 0);

	signal memtrackSetRng: std_logic_vector(7 downto 0);
	signal memtrackSetTCaptMax: std_logic_vector(31 downto 0);

	signal memtrackSetMaskTixVCapture: std_logic_vector(7 downto 0);

	signal vidtrackSelectTixVCapture: std_logic_vector(7 downto 0);
	signal vidtrackSelectStaTixVTrigger: std_logic_vector(7 downto 0);
	signal vidtrackSelectStaFallingNotRising: std_logic_vector(7 downto 0);
	signal vidtrackSelectStoTixVTrigger: std_logic_vector(7 downto 0);
	signal vidtrackSelectStoFallingNotRising: std_logic_vector(7 downto 0);

	signal vidtrackSetRng: std_logic_vector(7 downto 0);
	signal vidtrackSetTCaptMax: std_logic_vector(31 downto 0);

	signal hostifStateOp_dbg: std_logic_vector(7 downto 0);

	---- myHshktrack
	signal avllenSeqbufHshktrackToHostif: std_logic_vector(31 downto 0);

	signal seqbufHshktrackToHostifAXIS_tvalid: std_logic;
	signal seqbufHshktrackToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal seqbufHshktrackToHostifAXIS_tlast: std_logic;

	signal hshktrackGetInfoTixVState: std_logic_vector(7 downto 0);
	signal hshktrackGetInfoTCapt: std_logic_vector(31 downto 0);
	signal hshktrackGetInfoPtr0Seqbuf: std_logic_vector(15 downto 0);

	---- myIdent
	signal identGetUnt: std_logic_vector(95 downto 0);
	signal identGetVer: std_logic_vector(63 downto 0);
	signal identGetHash: std_logic_vector(63 downto 0);
	signal identGetWho: std_logic_vector(63 downto 0);

	signal identGetCfgFMclk: std_logic_vector(31 downto 0);
	signal identGetCfgFMemclk: std_logic_vector(31 downto 0);

	---- myLinear
	signal linearToStepmuxNslp: std_logic;
	signal linearToStepmuxM0: std_logic;
	signal linearToStepmuxM0z: std_logic;
	signal linearToStepmuxM1: std_logic;
	signal linearToStepmuxDir: std_logic;
	signal linearToStepmuxStep: std_logic;

	---- myMemtrack
	signal avllenSeqbufMemtrackToHostif: std_logic_vector(31 downto 0);

	signal seqbufMemtrackToHostifAXIS_tvalid: std_logic;
	signal seqbufMemtrackToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal seqbufMemtrackToHostifAXIS_tlast: std_logic;

	signal memtrackGetInfoTixVState: std_logic_vector(7 downto 0);
	signal memtrackGetInfoTCapt: std_logic_vector(31 downto 0);
	signal memtrackGetInfoPtr0Seqbuf: std_logic_vector(15 downto 0);

	---- myRender
	signal rndmemAXI_araddr: std_logic_vector(17 downto 0);
	signal rndmemAXI_arvalid: std_logic;
	signal rndmemAXI_rready: std_logic;

	signal rndmemAXI_awaddr: std_logic_vector(17 downto 0);
	signal rndmemAXI_awvalid: std_logic;
	signal rndmemAXI_bready: std_logic;
	signal rndmemAXI_wdata: std_logic_vector(127 downto 0);
	signal rndmemAXI_wlast: std_logic;
	signal rndmemAXI_wvalid: std_logic;

	---- myRotary
	signal rotaryToStepmuxNslp: std_logic;
	signal rotaryToStepmuxM0: std_logic;
	signal rotaryToStepmuxM0z: std_logic;
	signal rotaryToStepmuxM1: std_logic;
	signal rotaryToStepmuxDir: std_logic;
	signal rotaryToStepmuxStep: std_logic;

	signal rotaryGetInfoTixVState: std_logic_vector(7 downto 0);
	signal rotaryGetInfoAngle: std_logic_vector(15 downto 0);

	---- myState
	signal rgb0: std_logic_vector(23 downto 0);
	signal rgb1: std_logic_vector(23 downto 0);

	---- myTkclksrc
	signal tkclk: std_logic;

	signal tkclksrcGetTkstTkst: std_logic_vector(31 downto 0);

	signal tkclksrcStateOp_dbg: std_logic_vector(7 downto 0);

	---- myTrace
	signal avllenFlgbufTraceToHostif: std_logic_vector(31 downto 0);

	signal flgbufTraceToHostifAXIS_tvalid: std_logic;
	signal flgbufTraceToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal flgbufTraceToHostifAXIS_tlast: std_logic;

	signal traceGetInfoTixVState: std_logic_vector(7 downto 0);
	signal traceGetInfoTkst: std_logic_vector(31 downto 0);

	---- myVideoin
	signal camifToVideoinAXIS_tready: std_logic;

	signal grayVideoinToManyAXIS_tvalid: std_logic;
	signal grayVideoinToManyAXIS_tdata: std_logic_vector(71 downto 0);
	signal grayVideoinToManyAXIS_tlast: std_logic;

	signal rgbVideoinToManyAXIS_tvalid: std_logic;
	signal rgbVideoinToManyAXIS_tdata: std_logic_vector(35 downto 0);
	signal rgbVideoinToManyAXIS_tlast: std_logic;

	signal videoinStateIgr_dbg: std_logic_vector(7 downto 0);
	signal videoinStateRgbegr_dbg: std_logic_vector(7 downto 0);

	---- myVidtrack
	signal avllenSeqbufVidtrackToHostif: std_logic_vector(31 downto 0);

	signal seqbufVidtrackToHostifAXIS_tvalid: std_logic;
	signal seqbufVidtrackToHostifAXIS_tdata: std_logic_vector(31 downto 0);
	signal seqbufVidtrackToHostifAXIS_tlast: std_logic;

	signal vidtrackGetInfoTixVState: std_logic_vector(7 downto 0);
	signal vidtrackGetInfoTCapt: std_logic_vector(31 downto 0);
	signal vidtrackGetInfoPtr0Seqbuf: std_logic_vector(15 downto 0);

	---- handshake
	-- myHostif to myDecim
	signal reqPvwbufDecimToHostif: std_logic;
	signal ackPvwbufDecimToHostif: std_logic;
	signal dnePvwbufDecimToHostif: std_logic;

	-- myHostif to myCorner
	signal reqCoobufCornerToHostif: std_logic;
	signal ackCoobufCornerToHostif: std_logic;
	signal dneCoobufCornerToHostif: std_logic;

	-- myHostif to myTrace
	signal reqFlgbufTraceToHostif: std_logic;
	signal ackFlgbufTraceToHostif: std_logic;
	signal dneFlgbufTraceToHostif: std_logic;

	-- myHostif to (many)
	signal reqResetFromHostif: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifConfig: std_logic;
	signal ackInvCamifConfig: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifConfigSynth: std_logic;
	signal ackInvCamifConfigSynth: std_logic;

	-- myHostif to myCputrack
	signal reqSeqbufCputrackToHostif: std_logic;
	signal ackSeqbufCputrackToHostif: std_logic;
	signal dneSeqbufCputrackToHostif: std_logic;

	-- myHostif to myHshktrack
	signal reqSeqbufHshktrackToHostif: std_logic;
	signal ackSeqbufHshktrackToHostif: std_logic;
	signal dneSeqbufHshktrackToHostif: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifSetReg: std_logic;
	signal ackInvCamifSetReg: std_logic;

	-- myHostif to myMemtrack
	signal reqSeqbufMemtrackToHostif: std_logic;
	signal ackSeqbufMemtrackToHostif: std_logic;
	signal dneSeqbufMemtrackToHostif: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifGetReg: std_logic;
	signal ackInvCamifGetReg: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifModReg: std_logic;
	signal ackInvCamifModReg: std_logic;

	-- myHostif to myVidtrack
	signal reqSeqbufVidtrackToHostif: std_logic;
	signal ackSeqbufVidtrackToHostif: std_logic;
	signal dneSeqbufVidtrackToHostif: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifSetCorereg: std_logic;
	signal ackInvCamifSetCorereg: std_logic;

	-- myRender to myDdrif
	signal reqRenderToDdrifWr: std_logic;
	signal ackRenderToDdrifWr: std_logic;

	-- myRender to myDdrif
	signal reqRenderToDdrifRd: std_logic;
	signal ackRenderToDdrifRd: std_logic;

	-- myHostif to myCamif
	signal reqInvCamifGetCorereg: std_logic;
	signal ackInvCamifGetCorereg: std_logic;

	-- myHdreng to myDdrif
	signal reqHdrengToDdrifWr: std_logic;
	signal ackHdrengToDdrifWr: std_logic;

	-- myHdreng to myDdrif
	signal reqHdrengToDdrifRd: std_logic;
	signal ackHdrengToDdrifRd: std_logic;

	-- myHostif to myCorner
	signal reqInvCornerAcquire: std_logic;
	signal ackInvCornerAcquire: std_logic;

	-- myHostif to myCorner
	signal reqInvCornerConfig: std_logic;
	signal ackInvCornerConfig: std_logic;

	-- myHostif to myCorner
	signal reqInvCornerSet: std_logic;
	signal ackInvCornerSet: std_logic;

	-- myHostif to myCorner
	signal reqInvCornerUnlock: std_logic;
	signal ackInvCornerUnlock: std_logic;

	-- myHostif to myDecim
	signal reqInvDecimAcquire: std_logic;
	signal ackInvDecimAcquire: std_logic;

	-- myHostif to myDecim
	signal reqInvDecimConfig: std_logic;
	signal ackInvDecimConfig: std_logic;

	-- myHostif to myDecim
	signal reqInvDecimSet: std_logic;
	signal ackInvDecimSet: std_logic;

	-- myHostif to myDecim
	signal reqInvDecimUnlock: std_logic;
	signal ackInvDecimUnlock: std_logic;

	-- myHostif to myDirector
	signal reqInvDirectorConfig: std_logic;
	signal ackInvDirectorConfig: std_logic;

	-- myHostif to myDirector
	signal reqInvDirectorSet: std_logic;
	signal ackInvDirectorSet: std_logic;

	-- myHostif to myHdreng
	signal reqInvHdrengAssign: std_logic;
	signal ackInvHdrengAssign: std_logic;

	-- myHostif to myHdreng
	signal reqInvHdrengSet: std_logic;
	signal ackInvHdrengSet: std_logic;

	-- myHostif to myLaser
	signal reqInvLaserSet: std_logic;
	signal ackInvLaserSet: std_logic;

	-- myHostif to myRotary
	signal reqInvRotaryConfig: std_logic;
	signal ackInvRotaryConfig: std_logic;

	-- myHostif to myRotary
	signal reqInvRotaryMoveto: std_logic;
	signal ackInvRotaryMoveto: std_logic;

	-- myHostif to myRotary
	signal reqInvRotarySet: std_logic;
	signal ackInvRotarySet: std_logic;

	-- myHostif to myRotary
	signal reqInvRotaryZero: std_logic;
	signal ackInvRotaryZero: std_logic;

	-- myHostif to myStepmux
	signal reqInvStepmuxSet: std_logic;
	signal ackInvStepmuxSet: std_logic;

	-- myHostif to myTkclksrc
	signal reqInvTkclksrcSetTkst: std_logic;
	signal ackInvTkclksrcSetTkst: std_logic;

	-- myHostif to myTrace
	signal reqInvTraceAcquire: std_logic;
	signal ackInvTraceAcquire: std_logic;

	-- myHostif to myTrace
	signal reqInvTraceConfig: std_logic;
	signal ackInvTraceConfig: std_logic;

	-- myHostif to myTrace
	signal reqInvTraceUnlock: std_logic;
	signal ackInvTraceUnlock: std_logic;

	-- myHostif to myCputrack
	signal reqInvCputrackSelect: std_logic;
	signal ackInvCputrackSelect: std_logic;

	-- myHostif to myCputrack
	signal reqInvCputrackSet: std_logic;
	signal ackInvCputrackSet: std_logic;

	-- myHostif to myHshktrack
	signal reqInvHshktrackClearMask: std_logic;
	signal ackInvHshktrackClearMask: std_logic;

	-- myHostif to myHshktrack
	signal reqInvHshktrackSelect: std_logic;
	signal ackInvHshktrackSelect: std_logic;

	-- myHostif to myHshktrack
	signal reqInvHshktrackSet: std_logic;
	signal ackInvHshktrackSet: std_logic;

	-- myHostif to myHshktrack
	signal reqInvHshktrackSetMask: std_logic;
	signal ackInvHshktrackSetMask: std_logic;

	-- myHostif to myMemtrack
	signal reqInvMemtrackClearMask: std_logic;
	signal ackInvMemtrackClearMask: std_logic;

	-- myHostif to myMemtrack
	signal reqInvMemtrackSelect: std_logic;
	signal ackInvMemtrackSelect: std_logic;

	-- myHostif to myMemtrack
	signal reqInvMemtrackSet: std_logic;
	signal ackInvMemtrackSet: std_logic;

	-- myHostif to myMemtrack
	signal reqInvMemtrackSetMask: std_logic;
	signal ackInvMemtrackSetMask: std_logic;

	-- myHostif to myVidtrack
	signal reqInvVidtrackSelect: std_logic;
	signal ackInvVidtrackSelect: std_logic;

	-- myHostif to myVidtrack
	signal reqInvVidtrackSet: std_logic;
	signal ackInvVidtrackSet: std_logic;

	---- other
	signal grayVideoinToManyAXIS_tready: std_logic;

	signal rgbVideoinToManyAXIS_tready: std_logic;

	signal NRow: std_logic_vector(10 downto 0);
	signal NCol: std_logic_vector(10 downto 0);

	signal trigA: std_logic;
	signal trigB: std_logic;
	signal trigC: std_logic;
	signal trigD: std_logic;

	signal dbg0: std_logic_vector(15 downto 0);
	signal dbg1: std_logic_vector(15 downto 0);

	signal probe_sig: std_logic_vector(5 downto 0);
	-- IP sigs.oth.cust --- IBEGIN

	signal ddrAXI_awvalid_sig: std_logic;

	signal apuAXIL_awready_sig: std_logic;
	signal apuAXIL_wready_sig: std_logic;
	signal apuAXIL_bvalid_sig: std_logic;

	signal datatype_dbg: std_logic_vector(5 downto 0);

	signal mipiAXIS_dbg: std_logic_vector(3 downto 0);
	signal video_out_dbg: std_logic_vector(3 downto 0);
	-- IP sigs.oth.cust --- IEND

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myCamif : Camif
		generic map (
			fMclk => fMclk -- in kHz
		)
		port map (
			reset => reset,
			mclk => mclk,
			resetPixrxclk => resetPixrxclk,
			pixrxclk => pixrxclk,
			tkclk => tkclk,

			NRowRaw => NRowRaw,
			NCol => NCol,

			toVideoinAXIS_tready => camifToVideoinAXIS_tready,
			toVideoinAXIS_tvalid => camifToVideoinAXIS_tvalid,
			toVideoinAXIS_tdata => camifToVideoinAXIS_tdata,
			toVideoinAXIS_tlast => camifToVideoinAXIS_tlast,

			reqInvConfig => reqInvCamifConfig,
			ackInvConfig => ackInvCamifConfig,

			configHdrNotFix => camifConfigHdrNotFix,
			configSynthNotLive => camifConfigSynthNotLive,

			reqInvConfigSynth => reqInvCamifConfigSynth,
			ackInvConfigSynth => ackInvCamifConfigSynth,

			configSynthTixVSynthmode => camifConfigSynthTixVSynthmode,
			configSynthTFramepad => camifConfigSynthTFramepad,
			configSynthTLinepad => camifConfigSynthTLinepad,

			reqInvSetReg => reqInvCamifSetReg,
			ackInvSetReg => ackInvCamifSetReg,

			setRegAddr => camifSetRegAddr,
			setRegVal => camifSetRegVal,

			reqInvGetReg => reqInvCamifGetReg,
			ackInvGetReg => ackInvCamifGetReg,

			getRegAddr => camifGetRegAddr,
			getRegVal => camifGetRegVal,

			reqInvModReg => reqInvCamifModReg,
			ackInvModReg => ackInvCamifModReg,

			modRegAddr => camifModRegAddr,
			modRegMask => camifModRegMask,
			modRegVal => camifModRegVal,

			reqInvSetCorereg => reqInvCamifSetCorereg,
			ackInvSetCorereg => ackInvCamifSetCorereg,

			setCoreregAddr => camifSetCoreregAddr,
			setCoreregVal => camifSetCoreregVal,

			reqInvGetCorereg => reqInvCamifGetCorereg,
			ackInvGetCorereg => ackInvCamifGetCorereg,

			getCoreregAddr => camifGetCoreregAddr,
			getCoreregVal => camifGetCoreregVal,

			rng => rng,

			vsync => vsync,
			ixTExp => ixTExp,

			clk_byte_HS => clk_byte_HS,

			mipirx_RESET_N => mipirx_RESET_N,
			mipirx_RST0_N => mipirx_RST0_N,
			mipirx_ERR_CONTROL_LAN0 => mipirx_ERR_CONTROL_LAN0,
			mipirx_ERR_CONTROL_LAN1 => mipirx_ERR_CONTROL_LAN1,
			mipirx_ERR_CONTROL_LAN2 => mipirx_ERR_CONTROL_LAN2,
			mipirx_ERR_CONTROL_LAN3 => mipirx_ERR_CONTROL_LAN3,
			mipirx_ERR_ESC_LAN0 => mipirx_ERR_ESC_LAN0,
			mipirx_ERR_ESC_LAN1 => mipirx_ERR_ESC_LAN1,
			mipirx_ERR_ESC_LAN2 => mipirx_ERR_ESC_LAN2,
			mipirx_ERR_ESC_LAN3 => mipirx_ERR_ESC_LAN3,
			mipirx_ERR_SOT_SYNC_HS_LAN0 => mipirx_ERR_SOT_SYNC_HS_LAN0,
			mipirx_ERR_SOT_SYNC_HS_LAN1 => mipirx_ERR_SOT_SYNC_HS_LAN1,
			mipirx_ERR_SOT_SYNC_HS_LAN2 => mipirx_ERR_SOT_SYNC_HS_LAN2,
			mipirx_ERR_SOT_SYNC_HS_LAN3 => mipirx_ERR_SOT_SYNC_HS_LAN3,
			mipirx_ESC_CLK_LAN0 => mipirx_ESC_CLK_LAN0,
			mipirx_ESC_CLK_LAN1 => mipirx_ESC_CLK_LAN1,
			mipirx_ESC_CLK_LAN2 => mipirx_ESC_CLK_LAN2,
			mipirx_ESC_CLK_LAN3 => mipirx_ESC_CLK_LAN3,
			mipirx_RX_DATA_HS_LAN0 => mipirx_RX_DATA_HS_LAN0,
			mipirx_RX_DATA_HS_LAN1 => mipirx_RX_DATA_HS_LAN1,
			mipirx_RX_DATA_HS_LAN2 => mipirx_RX_DATA_HS_LAN2,
			mipirx_RX_DATA_HS_LAN3 => mipirx_RX_DATA_HS_LAN3,
			mipirx_RX_SKEW_CAL_HS_LAN0 => mipirx_RX_SKEW_CAL_HS_LAN0,
			mipirx_RX_SKEW_CAL_HS_LAN1 => mipirx_RX_SKEW_CAL_HS_LAN1,
			mipirx_RX_SKEW_CAL_HS_LAN2 => mipirx_RX_SKEW_CAL_HS_LAN2,
			mipirx_RX_SKEW_CAL_HS_LAN3 => mipirx_RX_SKEW_CAL_HS_LAN3,
			mipirx_RX_SYNC_HS_LAN0 => mipirx_RX_SYNC_HS_LAN0,
			mipirx_RX_SYNC_HS_LAN1 => mipirx_RX_SYNC_HS_LAN1,
			mipirx_RX_SYNC_HS_LAN2 => mipirx_RX_SYNC_HS_LAN2,
			mipirx_RX_SYNC_HS_LAN3 => mipirx_RX_SYNC_HS_LAN3,
			mipirx_RX_ULPS_ACTIVE_CLK_NOT => mipirx_RX_ULPS_ACTIVE_CLK_NOT,
			mipirx_RX_ULPS_ACTIVE_NOT_LAN0 => mipirx_RX_ULPS_ACTIVE_NOT_LAN0,
			mipirx_RX_ULPS_ACTIVE_NOT_LAN1 => mipirx_RX_ULPS_ACTIVE_NOT_LAN1,
			mipirx_RX_ULPS_ACTIVE_NOT_LAN2 => mipirx_RX_ULPS_ACTIVE_NOT_LAN2,
			mipirx_RX_ULPS_ACTIVE_NOT_LAN3 => mipirx_RX_ULPS_ACTIVE_NOT_LAN3,
			mipirx_RX_ULPS_CLK_NOT => mipirx_RX_ULPS_CLK_NOT,
			mipirx_RX_ULPS_ESC_LAN0 => mipirx_RX_ULPS_ESC_LAN0,
			mipirx_RX_ULPS_ESC_LAN1 => mipirx_RX_ULPS_ESC_LAN1,
			mipirx_RX_ULPS_ESC_LAN2 => mipirx_RX_ULPS_ESC_LAN2,
			mipirx_RX_ULPS_ESC_LAN3 => mipirx_RX_ULPS_ESC_LAN3,
			mipirx_RX_VALID_HS_LAN0 => mipirx_RX_VALID_HS_LAN0,
			mipirx_RX_VALID_HS_LAN1 => mipirx_RX_VALID_HS_LAN1,
			mipirx_RX_VALID_HS_LAN2 => mipirx_RX_VALID_HS_LAN2,
			mipirx_RX_VALID_HS_LAN3 => mipirx_RX_VALID_HS_LAN3,
			mipirx_STOPSTATE_LAN0 => mipirx_STOPSTATE_LAN0,
			mipirx_STOPSTATE_LAN1 => mipirx_STOPSTATE_LAN1,
			mipirx_STOPSTATE_LAN2 => mipirx_STOPSTATE_LAN2,
			mipirx_STOPSTATE_LAN3 => mipirx_STOPSTATE_LAN3,

			scl_in => scl_in,
			scl_out => scl_out,
			scl_tri => scl_tri,

			sda_in => sda_in,
			sda_out => sda_out,
			sda_tri => sda_tri,

			RxDataHS0 => mipirx_RX_DATA_HS_LAN0,
			RxDataHS1 => mipirx_RX_DATA_HS_LAN1,
			RxDataHS2 => mipirx_RX_DATA_HS_LAN2,
			RxDataHS3 => mipirx_RX_DATA_HS_LAN3,

			datatype_dbg => camifDatatype_dbg,
			mipiAXIS_dbg => open,
			video_out_dbg => open,

			stateConfig_dbg => camifStateConfig_dbg
		);

	myCorner : Corner
		port map (
			reset => reset,
			mclk => mclk,

			vsync => vsync,
			NRow => NRow,
			NCol => NCol,

			grayFromVideoinAXIS_tready => grayVideoinToManyAXIS_tready,
			grayFromVideoinAXIS_tvalid => grayVideoinToManyAXIS_tvalid,
			grayFromVideoinAXIS_tdata => grayVideoinToManyAXIS_tdata,
			grayFromVideoinAXIS_tlast => grayVideoinToManyAXIS_tlast,

			reqInvAcquire => reqInvCornerAcquire,
			ackInvAcquire => ackInvCornerAcquire,

			reqInvConfig => reqInvCornerConfig,
			ackInvConfig => ackInvCornerConfig,

			configLinNotLog => cornerConfigLinNotLog,
			configThd => cornerConfigThd,
			configRow0 => cornerConfigRow0,
			configRow1 => cornerConfigRow1,
			configCol0 => cornerConfigCol0,
			configCol1 => cornerConfigCol1,

			getInfoTixVState => cornerGetInfoTixVState,
			getInfoTkst => cornerGetInfoTkst,
			getInfoScoreMin => cornerGetInfoScoreMin,
			getInfoScoreMax => cornerGetInfoScoreMax,

			reqInvSet => reqInvCornerSet,
			ackInvSet => ackInvCornerSet,

			setRng => cornerSetRng,

			reqInvUnlock => reqInvCornerUnlock,
			ackInvUnlock => ackInvCornerUnlock,

			tkclksrcGetTkstTkst => tkclksrcGetTkstTkst,

			reqCoobufToHostif => reqCoobufCornerToHostif,
			ackCoobufToHostif => ackCoobufCornerToHostif,
			dneCoobufToHostif => dneCoobufCornerToHostif,
			avllenCoobufToHostif => avllenCoobufCornerToHostif,

			coobufToHostifAXIS_tready => coobufCornerToHostifAXIS_tready,
			coobufToHostifAXIS_tvalid => coobufCornerToHostifAXIS_tvalid,
			coobufToHostifAXIS_tdata => coobufCornerToHostifAXIS_tdata,
			coobufToHostifAXIS_tlast => coobufCornerToHostifAXIS_tlast
		);

	myCputrack : Cputrack
		port map (
			reset => reset,
			mclk => mclk,

			trigA => trigA,
			trigB => trigB,
			trigC => trigC,
			trigD => trigD,

			getInfoTixVState => cputrackGetInfoTixVState,
			getInfoTCapt => cputrackGetInfoTCapt,
			getInfoPtr0Seqbuf => cputrackGetInfoPtr0Seqbuf,

			reqInvSelect => reqInvCputrackSelect,
			ackInvSelect => ackInvCputrackSelect,

			selectTixVCapture => cputrackSelectTixVCapture,
			selectStaTixVTrigger => cputrackSelectStaTixVTrigger,
			selectStaFallingNotRising => cputrackSelectStaFallingNotRising,
			selectStoTixVTrigger => cputrackSelectStoTixVTrigger,
			selectStoFallingNotRising => cputrackSelectStoFallingNotRising,

			reqInvSet => reqInvCputrackSet,
			ackInvSet => ackInvCputrackSet,

			setRng => cputrackSetRng,
			setTCaptMax => cputrackSetTCaptMax,

			reqSeqbufToHostif => reqSeqbufCputrackToHostif,
			ackSeqbufToHostif => ackSeqbufCputrackToHostif,
			dneSeqbufToHostif => dneSeqbufCputrackToHostif,
			avllenSeqbufToHostif => avllenSeqbufCputrackToHostif,

			seqbufToHostifAXIS_tready => seqbufCputrackToHostifAXIS_tready,
			seqbufToHostifAXIS_tvalid => seqbufCputrackToHostifAXIS_tvalid,
			seqbufToHostifAXIS_tdata => seqbufCputrackToHostifAXIS_tdata,
			seqbufToHostifAXIS_tlast => seqbufCputrackToHostifAXIS_tlast,

			hostifStateOp => hostifStateOp_dbg
		);

	myDdrif : Ddrif
		port map (
			reset => reset,
			mclk => mclk,

			resetMemclk => resetMemclk,
			memclk => memclk,

			tkclk => tkclk,

			getStatsNRdA => ddrifGetStatsNRdA,
			getStatsNRdB => ddrifGetStatsNRdB,
			getStatsNWrA => ddrifGetStatsNWrA,
			getStatsNWrB => ddrifGetStatsNWrB,

			reqRdA => reqHdrengToDdrifRd,
			ackRdA => ackHdrengToDdrifRd,

			rdAAXI_araddr => hdrmemAXI_araddr,
			rdAAXI_arready => hdrmemAXI_arready,
			rdAAXI_arvalid => hdrmemAXI_arvalid,
			rdAAXI_rdata => hdrmemAXI_rdata,
			rdAAXI_rlast => hdrmemAXI_rlast,
			rdAAXI_rready => hdrmemAXI_rready,
			rdAAXI_rresp => hdrmemAXI_rresp,
			rdAAXI_rvalid => hdrmemAXI_rvalid,

			reqRdB => reqRenderToDdrifRd,
			ackRdB => ackRenderToDdrifRd,

			rdBAXI_araddr => rndmemAXI_araddr,
			rdBAXI_arready => rndmemAXI_arready,
			rdBAXI_arvalid => rndmemAXI_arvalid,
			rdBAXI_rdata => rndmemAXI_rdata,
			rdBAXI_rlast => rndmemAXI_rlast,
			rdBAXI_rready => rndmemAXI_rready,
			rdBAXI_rresp => rndmemAXI_rresp,
			rdBAXI_rvalid => rndmemAXI_rvalid,

			reqWrA => reqHdrengToDdrifWr,
			ackWrA => ackHdrengToDdrifWr,

			wrAAXI_awaddr => hdrmemAXI_awaddr,
			wrAAXI_awready => hdrmemAXI_awready,
			wrAAXI_awvalid => hdrmemAXI_awvalid,
			wrAAXI_wdata => hdrmemAXI_wdata,
			wrAAXI_wlast => hdrmemAXI_wlast,
			wrAAXI_wready => hdrmemAXI_wready,
			wrAAXI_wvalid => hdrmemAXI_wvalid,

			reqWrB => reqRenderToDdrifWr,
			ackWrB => ackRenderToDdrifWr,

			wrBAXI_awaddr => rndmemAXI_awaddr,
			wrBAXI_awready => rndmemAXI_awready,
			wrBAXI_awvalid => rndmemAXI_awvalid,
			wrBAXI_wdata => rndmemAXI_wdata,
			wrBAXI_wlast => rndmemAXI_wlast,
			wrBAXI_wready => rndmemAXI_wready,
			wrBAXI_wvalid => rndmemAXI_wvalid,

			ddrAXI_arid => ddrAXI_arid,
			ddrAXI_araddr => ddrAXI_araddr,
			ddrAXI_arburst => ddrAXI_arburst,
			ddrAXI_arcache => ddrAXI_arcache,
			ddrAXI_arlen => ddrAXI_arlen,
			ddrAXI_arlock => ddrAXI_arlock,
			ddrAXI_arprot => ddrAXI_arprot,
			ddrAXI_arqos => ddrAXI_arqos,
			ddrAXI_arready => ddrAXI_arready,
			ddrAXI_arregion => ddrAXI_arregion,
			ddrAXI_arsize => ddrAXI_arsize,
			ddrAXI_arvalid => ddrAXI_arvalid,

			ddrAXI_rid => ddrAXI_rid,
			ddrAXI_rdata => ddrAXI_rdata,
			ddrAXI_rlast => ddrAXI_rlast,
			ddrAXI_rready => ddrAXI_rready_sig,
			ddrAXI_rresp => ddrAXI_rresp,
			ddrAXI_rvalid => ddrAXI_rvalid,

			ddrAXI_awid => ddrAXI_awid,
			ddrAXI_awaddr => ddrAXI_awaddr,
			ddrAXI_awburst => ddrAXI_awburst,
			ddrAXI_awcache => ddrAXI_awcache,
			ddrAXI_awlen => ddrAXI_awlen,
			ddrAXI_awlock => ddrAXI_awlock,
			ddrAXI_awprot => ddrAXI_awprot,
			ddrAXI_awqos => ddrAXI_awqos,
			ddrAXI_awready => ddrAXI_awready,
			ddrAXI_awregion => ddrAXI_awregion,
			ddrAXI_awsize => ddrAXI_awsize,
			ddrAXI_awvalid => ddrAXI_awvalid,

			ddrAXI_wdata => ddrAXI_wdata,
			ddrAXI_wlast => ddrAXI_wlast,
			ddrAXI_wready => ddrAXI_wready,
			ddrAXI_wstrb => ddrAXI_wstrb,
			ddrAXI_wvalid => ddrAXI_wvalid_sig,

			ddrAXI_bid => ddrAXI_bid,
			ddrAXI_bready => ddrAXI_bready,
			ddrAXI_bresp => ddrAXI_bresp,
			ddrAXI_bvalid => ddrAXI_bvalid
		);

	myDecim : Decim
		port map (
			reset => reset,
			mclk => mclk,

			vsync => vsync,
			ixTExp => ixTExp,

			NRow => NRow,
			NCol => NCol,

			grayFromVideoinAXIS_tready => grayVideoinToManyAXIS_tready,
			grayFromVideoinAXIS_tvalid => grayVideoinToManyAXIS_tvalid,
			grayFromVideoinAXIS_tdata => grayVideoinToManyAXIS_tdata,
			grayFromVideoinAXIS_tlast => grayVideoinToManyAXIS_tlast,

			rgbFromVideoinAXIS_tready => rgbVideoinToManyAXIS_tready,
			rgbFromVideoinAXIS_tvalid => rgbVideoinToManyAXIS_tvalid,
			rgbFromVideoinAXIS_tdata => rgbVideoinToManyAXIS_tdata,
			rgbFromVideoinAXIS_tlast => rgbVideoinToManyAXIS_tlast,

			reqInvAcquire => reqInvDecimAcquire,
			ackInvAcquire => ackInvDecimAcquire,

			acquireIxTExp => decimAcquireIxTExp,

			reqInvConfig => reqInvDecimConfig,
			ackInvConfig => ackInvDecimConfig,

			configRgbNotGray => decimConfigRgbNotGray,
			configEdge => decimConfigEdge,
			configEdge2 => decimConfigEdge2,
			configNDecim => decimConfigNDecim,

			getInfoTixVState => decimGetInfoTixVState,
			getInfoTkst => decimGetInfoTkst,

			reqInvSet => reqInvDecimSet,
			ackInvSet => ackInvDecimSet,

			setRng => decimSetRng,

			reqInvUnlock => reqInvDecimUnlock,
			ackInvUnlock => ackInvDecimUnlock,

			tkclksrcGetTkstTkst => tkclksrcGetTkstTkst,

			reqPvwbufToHostif => reqPvwbufDecimToHostif,
			ackPvwbufToHostif => ackPvwbufDecimToHostif,
			dnePvwbufToHostif => dnePvwbufDecimToHostif,
			avllenPvwbufToHostif => avllenPvwbufDecimToHostif,

			pvwbufToHostifAXIS_tready => pvwbufDecimToHostifAXIS_tready,
			pvwbufToHostifAXIS_tvalid => pvwbufDecimToHostifAXIS_tvalid,
			pvwbufToHostifAXIS_tdata => pvwbufDecimToHostifAXIS_tdata,
			pvwbufToHostifAXIS_tlast => pvwbufDecimToHostifAXIS_tlast,

			stateStore_dbg => decimStateStore_dbg,
			stateStream_dbg => decimStateStream_dbg
		);

	myDirector : Director
		port map (
			reset => reset,
			mclk => mclk,

			NRowRaw => NRowRaw,
			NColRaw => NColRaw,

			rng => rng,

			reqInvConfig => reqInvDirectorConfig,
			ackInvConfig => ackInvDirectorConfig,

			configNRowRaw => directorConfigNRowRaw,
			configNColRaw => directorConfigNColRaw,

			reqInvSet => reqInvDirectorSet,
			ackInvSet => ackInvDirectorSet,

			setRng => directorSetRng
		);

	myFreqprobeDbg0 : Freqprobe_v1_0
		generic map (
			fMclk => fMclk
		)
		port map (
			reset => reset,
			mclk => mclk,
			bcdNotHex => '1',
			capt => dbg0,
			freq => freqDbg0
		);

	myFreqprobeDbg1 : Freqprobe_v1_0
		generic map (
			fMclk => fMclk
		)
		port map (
			reset => reset,
			mclk => mclk,
			bcdNotHex => '1',
			capt => dbg1,
			freq => freqDbg1
		);

	myHdreng : Hdreng
		port map (
			reset => reset,
			mclk => mclk,

			resetMemclk => resetMemclk,
			memclk => memclk,

			hdrmemAXI_awaddr => hdrmemAXI_awaddr,
			hdrmemAXI_awready => hdrmemAXI_awready,
			hdrmemAXI_awvalid => hdrmemAXI_awvalid,
			hdrmemAXI_bready => hdrmemAXI_bready,
			hdrmemAXI_bresp => hdrmemAXI_bresp,
			hdrmemAXI_bvalid => hdrmemAXI_bvalid,
			hdrmemAXI_wdata => hdrmemAXI_wdata,
			hdrmemAXI_wlast => hdrmemAXI_wlast,
			hdrmemAXI_wready => hdrmemAXI_wready,
			hdrmemAXI_wvalid => hdrmemAXI_wvalid,

			reqToDdrifWr => reqHdrengToDdrifWr,
			ackToDdrifWr => ackHdrengToDdrifWr,

			hdrmemAXI_araddr => hdrmemAXI_araddr,
			hdrmemAXI_arready => hdrmemAXI_arready,
			hdrmemAXI_arvalid => hdrmemAXI_arvalid,
			hdrmemAXI_rdata => hdrmemAXI_rdata,
			hdrmemAXI_rlast => hdrmemAXI_rlast,
			hdrmemAXI_rready => hdrmemAXI_rready,
			hdrmemAXI_rresp => hdrmemAXI_rresp,
			hdrmemAXI_rvalid => hdrmemAXI_rvalid,

			reqToDdrifRd => reqHdrengToDdrifRd,
			ackToDdrifRd => ackHdrengToDdrifRd,

			vsync => vsync,
			ixTExp => ixTExp,

			NRow => NRow,
			NCol => NCol,

			rgbFromVideoinAXIS_tready => rgbVideoinToManyAXIS_tready,
			rgbFromVideoinAXIS_tvalid => rgbVideoinToManyAXIS_tvalid,
			rgbFromVideoinAXIS_tdata => rgbVideoinToManyAXIS_tdata,
			rgbFromVideoinAXIS_tlast => rgbVideoinToManyAXIS_tlast,

			reqInvAssign => reqInvHdrengAssign,
			ackInvAssign => ackInvHdrengAssign,

			assignIxMem => hdrengAssignIxMem,

			getInfoTixVState => hdrengGetInfoTixVState,
			getInfoTkst => hdrengGetInfoTkst,
			getInfoIxMem => hdrengGetInfoIxMem,
			getInfoIxMemAcq => hdrengGetInfoIxMemAcq,

			reqInvSet => reqInvHdrengSet,
			ackInvSet => ackInvHdrengSet,

			setRng => hdrengSetRng,

			tkclksrcGetTkstTkst => tkclksrcGetTkstTkst
		);

	myHostif : Hostif
		generic map (
			fMclk => fMclk
		)
		port map (
			reset => reset,
			mclk => mclk,
			tkclk => tkclk,
			commok => commok,
			reqReset => reqResetFromHostif,

			identGetUnt => identGetUnt,
			identGetVer => identGetVer,
			identGetHash => identGetHash,
			identGetWho => identGetWho,

			identGetCfgFMclk => identGetCfgFMclk,
			identGetCfgFMemclk => identGetCfgFMemclk,

			reqInvCamifConfig => reqInvCamifConfig,
			ackInvCamifConfig => ackInvCamifConfig,

			camifConfigHdrNotFix => camifConfigHdrNotFix,
			camifConfigSynthNotLive => camifConfigSynthNotLive,

			reqInvCamifConfigSynth => reqInvCamifConfigSynth,
			ackInvCamifConfigSynth => ackInvCamifConfigSynth,

			camifConfigSynthTixVSynthmode => camifConfigSynthTixVSynthmode,
			camifConfigSynthTFramepad => camifConfigSynthTFramepad,
			camifConfigSynthTLinepad => camifConfigSynthTLinepad,

			reqInvCamifSetReg => reqInvCamifSetReg,
			ackInvCamifSetReg => ackInvCamifSetReg,

			camifSetRegAddr => camifSetRegAddr,
			camifSetRegVal => camifSetRegVal,

			reqInvCamifGetReg => reqInvCamifGetReg,
			ackInvCamifGetReg => ackInvCamifGetReg,

			camifGetRegAddr => camifGetRegAddr,
			camifGetRegVal => camifGetRegVal,

			reqInvCamifModReg => reqInvCamifModReg,
			ackInvCamifModReg => ackInvCamifModReg,

			camifModRegAddr => camifModRegAddr,
			camifModRegMask => camifModRegMask,
			camifModRegVal => camifModRegVal,

			reqInvCamifSetCorereg => reqInvCamifSetCorereg,
			ackInvCamifSetCorereg => ackInvCamifSetCorereg,

			camifSetCoreregAddr => camifSetCoreregAddr,
			camifSetCoreregVal => camifSetCoreregVal,

			reqInvCamifGetCorereg => reqInvCamifGetCorereg,
			ackInvCamifGetCorereg => ackInvCamifGetCorereg,

			camifGetCoreregAddr => camifGetCoreregAddr,
			camifGetCoreregVal => camifGetCoreregVal,

			reqInvCornerAcquire => reqInvCornerAcquire,
			ackInvCornerAcquire => ackInvCornerAcquire,

			reqInvCornerConfig => reqInvCornerConfig,
			ackInvCornerConfig => ackInvCornerConfig,

			cornerConfigLinNotLog => cornerConfigLinNotLog,
			cornerConfigThd => cornerConfigThd,
			cornerConfigRow0 => cornerConfigRow0,
			cornerConfigRow1 => cornerConfigRow1,
			cornerConfigCol0 => cornerConfigCol0,
			cornerConfigCol1 => cornerConfigCol1,

			cornerGetInfoTixVState => cornerGetInfoTixVState,
			cornerGetInfoTkst => cornerGetInfoTkst,
			cornerGetInfoScoreMin => cornerGetInfoScoreMin,
			cornerGetInfoScoreMax => cornerGetInfoScoreMax,

			reqInvCornerSet => reqInvCornerSet,
			ackInvCornerSet => ackInvCornerSet,

			cornerSetRng => cornerSetRng,

			reqInvCornerUnlock => reqInvCornerUnlock,
			ackInvCornerUnlock => ackInvCornerUnlock,

			ddrifGetStatsNRdA => ddrifGetStatsNRdA,
			ddrifGetStatsNRdB => ddrifGetStatsNRdB,
			ddrifGetStatsNWrA => ddrifGetStatsNWrA,
			ddrifGetStatsNWrB => ddrifGetStatsNWrB,

			reqInvDecimAcquire => reqInvDecimAcquire,
			ackInvDecimAcquire => ackInvDecimAcquire,

			decimAcquireIxTExp => decimAcquireIxTExp,

			reqInvDecimConfig => reqInvDecimConfig,
			ackInvDecimConfig => ackInvDecimConfig,

			decimConfigRgbNotGray => decimConfigRgbNotGray,
			decimConfigEdge => decimConfigEdge,
			decimConfigEdge2 => decimConfigEdge2,
			decimConfigNDecim => decimConfigNDecim,

			decimGetInfoTixVState => decimGetInfoTixVState,
			decimGetInfoTkst => decimGetInfoTkst,

			reqInvDecimSet => reqInvDecimSet,
			ackInvDecimSet => ackInvDecimSet,

			decimSetRng => decimSetRng,

			reqInvDecimUnlock => reqInvDecimUnlock,
			ackInvDecimUnlock => ackInvDecimUnlock,

			reqInvDirectorConfig => reqInvDirectorConfig,
			ackInvDirectorConfig => ackInvDirectorConfig,

			directorConfigNRowRaw => directorConfigNRowRaw,
			directorConfigNColRaw => directorConfigNColRaw,

			reqInvDirectorSet => reqInvDirectorSet,
			ackInvDirectorSet => ackInvDirectorSet,

			directorSetRng => directorSetRng,

			reqInvHdrengAssign => reqInvHdrengAssign,
			ackInvHdrengAssign => ackInvHdrengAssign,

			hdrengAssignIxMem => hdrengAssignIxMem,

			hdrengGetInfoTixVState => hdrengGetInfoTixVState,
			hdrengGetInfoTkst => hdrengGetInfoTkst,
			hdrengGetInfoIxMem => hdrengGetInfoIxMem,
			hdrengGetInfoIxMemAcq => hdrengGetInfoIxMemAcq,

			reqInvHdrengSet => reqInvHdrengSet,
			ackInvHdrengSet => ackInvHdrengSet,

			hdrengSetRng => hdrengSetRng,

			reqInvLaserSet => reqInvLaserSet,
			ackInvLaserSet => ackInvLaserSet,

			laserSetL => laserSetL,
			laserSetR => laserSetR,

			reqInvRotaryConfig => reqInvRotaryConfig,
			ackInvRotaryConfig => ackInvRotaryConfig,

			rotaryConfigTixVStepmode => rotaryConfigTixVStepmode,
			rotaryConfigTStep => rotaryConfigTStep,

			rotaryGetInfoTixVState => rotaryGetInfoTixVState,
			rotaryGetInfoAngle => rotaryGetInfoAngle,

			reqInvRotaryMoveto => reqInvRotaryMoveto,
			ackInvRotaryMoveto => ackInvRotaryMoveto,

			rotaryMovetoAngle => rotaryMovetoAngle,

			reqInvRotarySet => reqInvRotarySet,
			ackInvRotarySet => ackInvRotarySet,

			rotarySetRng => rotarySetRng,
			rotarySetCcwNotCw => rotarySetCcwNotCw,

			reqInvRotaryZero => reqInvRotaryZero,
			ackInvRotaryZero => ackInvRotaryZero,

			reqInvStepmuxSet => reqInvStepmuxSet,
			ackInvStepmuxSet => ackInvStepmuxSet,

			stepmuxSetLinNotRot => stepmuxSetLinNotRot,

			tkclksrcGetTkstTkst => tkclksrcGetTkstTkst,

			reqInvTkclksrcSetTkst => reqInvTkclksrcSetTkst,
			ackInvTkclksrcSetTkst => ackInvTkclksrcSetTkst,

			tkclksrcSetTkstTkst => tkclksrcSetTkstTkst,

			reqInvTraceAcquire => reqInvTraceAcquire,
			ackInvTraceAcquire => ackInvTraceAcquire,

			reqInvTraceConfig => reqInvTraceConfig,
			ackInvTraceConfig => ackInvTraceConfig,

			traceConfigTixVOrient => traceConfigTixVOrient,
			traceConfigRow0 => traceConfigRow0,
			traceConfigCol0 => traceConfigCol0,

			traceGetInfoTixVState => traceGetInfoTixVState,
			traceGetInfoTkst => traceGetInfoTkst,

			reqInvTraceUnlock => reqInvTraceUnlock,
			ackInvTraceUnlock => ackInvTraceUnlock,

			cputrackGetInfoTixVState => cputrackGetInfoTixVState,
			cputrackGetInfoTCapt => cputrackGetInfoTCapt,
			cputrackGetInfoPtr0Seqbuf => cputrackGetInfoPtr0Seqbuf,

			reqInvCputrackSelect => reqInvCputrackSelect,
			ackInvCputrackSelect => ackInvCputrackSelect,

			cputrackSelectTixVCapture => cputrackSelectTixVCapture,
			cputrackSelectStaTixVTrigger => cputrackSelectStaTixVTrigger,
			cputrackSelectStaFallingNotRising => cputrackSelectStaFallingNotRising,
			cputrackSelectStoTixVTrigger => cputrackSelectStoTixVTrigger,
			cputrackSelectStoFallingNotRising => cputrackSelectStoFallingNotRising,

			reqInvCputrackSet => reqInvCputrackSet,
			ackInvCputrackSet => ackInvCputrackSet,

			cputrackSetRng => cputrackSetRng,
			cputrackSetTCaptMax => cputrackSetTCaptMax,

			reqInvHshktrackClearMask => reqInvHshktrackClearMask,
			ackInvHshktrackClearMask => ackInvHshktrackClearMask,

			hshktrackGetInfoTixVState => hshktrackGetInfoTixVState,
			hshktrackGetInfoTCapt => hshktrackGetInfoTCapt,
			hshktrackGetInfoPtr0Seqbuf => hshktrackGetInfoPtr0Seqbuf,

			reqInvHshktrackSelect => reqInvHshktrackSelect,
			ackInvHshktrackSelect => ackInvHshktrackSelect,

			hshktrackSelectStaTixVTrigger => hshktrackSelectStaTixVTrigger,
			hshktrackSelectStaFallingNotRising => hshktrackSelectStaFallingNotRising,
			hshktrackSelectStoTixVTrigger => hshktrackSelectStoTixVTrigger,
			hshktrackSelectStoFallingNotRising => hshktrackSelectStoFallingNotRising,

			reqInvHshktrackSet => reqInvHshktrackSet,
			ackInvHshktrackSet => ackInvHshktrackSet,

			hshktrackSetRng => hshktrackSetRng,
			hshktrackSetTCaptMax => hshktrackSetTCaptMax,

			reqInvHshktrackSetMask => reqInvHshktrackSetMask,
			ackInvHshktrackSetMask => ackInvHshktrackSetMask,

			hshktrackSetMaskTixVCapture => hshktrackSetMaskTixVCapture,

			reqInvMemtrackClearMask => reqInvMemtrackClearMask,
			ackInvMemtrackClearMask => ackInvMemtrackClearMask,

			memtrackGetInfoTixVState => memtrackGetInfoTixVState,
			memtrackGetInfoTCapt => memtrackGetInfoTCapt,
			memtrackGetInfoPtr0Seqbuf => memtrackGetInfoPtr0Seqbuf,

			reqInvMemtrackSelect => reqInvMemtrackSelect,
			ackInvMemtrackSelect => ackInvMemtrackSelect,

			memtrackSelectStaTixVTrigger => memtrackSelectStaTixVTrigger,
			memtrackSelectStaFallingNotRising => memtrackSelectStaFallingNotRising,
			memtrackSelectStoTixVTrigger => memtrackSelectStoTixVTrigger,
			memtrackSelectStoFallingNotRising => memtrackSelectStoFallingNotRising,

			reqInvMemtrackSet => reqInvMemtrackSet,
			ackInvMemtrackSet => ackInvMemtrackSet,

			memtrackSetRng => memtrackSetRng,
			memtrackSetTCaptMax => memtrackSetTCaptMax,

			reqInvMemtrackSetMask => reqInvMemtrackSetMask,
			ackInvMemtrackSetMask => ackInvMemtrackSetMask,

			memtrackSetMaskTixVCapture => memtrackSetMaskTixVCapture,

			vidtrackGetInfoTixVState => vidtrackGetInfoTixVState,
			vidtrackGetInfoTCapt => vidtrackGetInfoTCapt,
			vidtrackGetInfoPtr0Seqbuf => vidtrackGetInfoPtr0Seqbuf,

			reqInvVidtrackSelect => reqInvVidtrackSelect,
			ackInvVidtrackSelect => ackInvVidtrackSelect,

			vidtrackSelectTixVCapture => vidtrackSelectTixVCapture,
			vidtrackSelectStaTixVTrigger => vidtrackSelectStaTixVTrigger,
			vidtrackSelectStaFallingNotRising => vidtrackSelectStaFallingNotRising,
			vidtrackSelectStoTixVTrigger => vidtrackSelectStoTixVTrigger,
			vidtrackSelectStoFallingNotRising => vidtrackSelectStoFallingNotRising,

			reqInvVidtrackSet => reqInvVidtrackSet,
			ackInvVidtrackSet => ackInvVidtrackSet,

			vidtrackSetRng => vidtrackSetRng,
			vidtrackSetTCaptMax => vidtrackSetTCaptMax,

			reqPvwbufFromDecim => reqPvwbufDecimToHostif,
			ackPvwbufFromDecim => ackPvwbufDecimToHostif,
			dnePvwbufFromDecim => dnePvwbufDecimToHostif,
			avllenPvwbufFromDecim => avllenPvwbufDecimToHostif,

			pvwbufFromDecimAXIS_tready => pvwbufDecimToHostifAXIS_tready,
			pvwbufFromDecimAXIS_tvalid => pvwbufDecimToHostifAXIS_tvalid,
			pvwbufFromDecimAXIS_tdata => pvwbufDecimToHostifAXIS_tdata,
			pvwbufFromDecimAXIS_tlast => pvwbufDecimToHostifAXIS_tlast,

			reqCoobufFromCorner => reqCoobufCornerToHostif,
			ackCoobufFromCorner => ackCoobufCornerToHostif,
			dneCoobufFromCorner => dneCoobufCornerToHostif,
			avllenCoobufFromCorner => avllenCoobufCornerToHostif,

			reqFlgbufFromTrace => reqFlgbufTraceToHostif,
			ackFlgbufFromTrace => ackFlgbufTraceToHostif,

			coobufFromCornerAXIS_tready => coobufCornerToHostifAXIS_tready,
			coobufFromCornerAXIS_tvalid => coobufCornerToHostifAXIS_tvalid,
			coobufFromCornerAXIS_tdata => coobufCornerToHostifAXIS_tdata,
			coobufFromCornerAXIS_tlast => coobufCornerToHostifAXIS_tlast,

			dneFlgbufFromTrace => dneFlgbufTraceToHostif,
			avllenFlgbufFromTrace => avllenFlgbufTraceToHostif,

			flgbufFromTraceAXIS_tready => flgbufTraceToHostifAXIS_tready,
			flgbufFromTraceAXIS_tvalid => flgbufTraceToHostifAXIS_tvalid,
			flgbufFromTraceAXIS_tdata => flgbufTraceToHostifAXIS_tdata,
			flgbufFromTraceAXIS_tlast => flgbufTraceToHostifAXIS_tlast,

			reqSeqbufFromCputrack => reqSeqbufCputrackToHostif,
			ackSeqbufFromCputrack => ackSeqbufCputrackToHostif,
			dneSeqbufFromCputrack => dneSeqbufCputrackToHostif,
			avllenSeqbufFromCputrack => avllenSeqbufCputrackToHostif,

			seqbufFromCputrackAXIS_tready => seqbufCputrackToHostifAXIS_tready,
			seqbufFromCputrackAXIS_tvalid => seqbufCputrackToHostifAXIS_tvalid,
			seqbufFromCputrackAXIS_tdata => seqbufCputrackToHostifAXIS_tdata,
			seqbufFromCputrackAXIS_tlast => seqbufCputrackToHostifAXIS_tlast,

			reqSeqbufFromHshktrack => reqSeqbufHshktrackToHostif,
			ackSeqbufFromHshktrack => ackSeqbufHshktrackToHostif,
			dneSeqbufFromHshktrack => dneSeqbufHshktrackToHostif,
			avllenSeqbufFromHshktrack => avllenSeqbufHshktrackToHostif,

			reqSeqbufFromMemtrack => reqSeqbufMemtrackToHostif,
			ackSeqbufFromMemtrack => ackSeqbufMemtrackToHostif,
			dneSeqbufFromMemtrack => dneSeqbufMemtrackToHostif,
			avllenSeqbufFromMemtrack => avllenSeqbufMemtrackToHostif,

			seqbufFromHshktrackAXIS_tready => seqbufHshktrackToHostifAXIS_tready,
			seqbufFromHshktrackAXIS_tvalid => seqbufHshktrackToHostifAXIS_tvalid,
			seqbufFromHshktrackAXIS_tdata => seqbufHshktrackToHostifAXIS_tdata,
			seqbufFromHshktrackAXIS_tlast => seqbufHshktrackToHostifAXIS_tlast,

			seqbufFromMemtrackAXIS_tready => seqbufMemtrackToHostifAXIS_tready,

			reqSeqbufFromVidtrack => reqSeqbufVidtrackToHostif,
			ackSeqbufFromVidtrack => ackSeqbufVidtrackToHostif,
			dneSeqbufFromVidtrack => dneSeqbufVidtrackToHostif,
			avllenSeqbufFromVidtrack => avllenSeqbufVidtrackToHostif,

			seqbufFromMemtrackAXIS_tvalid => seqbufMemtrackToHostifAXIS_tvalid,
			seqbufFromMemtrackAXIS_tdata => seqbufMemtrackToHostifAXIS_tdata,
			seqbufFromMemtrackAXIS_tlast => seqbufMemtrackToHostifAXIS_tlast,

			seqbufFromVidtrackAXIS_tready => seqbufVidtrackToHostifAXIS_tready,
			seqbufFromVidtrackAXIS_tvalid => seqbufVidtrackToHostifAXIS_tvalid,
			seqbufFromVidtrackAXIS_tdata => seqbufVidtrackToHostifAXIS_tdata,
			seqbufFromVidtrackAXIS_tlast => seqbufVidtrackToHostifAXIS_tlast,

			AXIL_araddr => apuAXIL_araddr,
			AXIL_arprot => apuAXIL_arprot,
			AXIL_arready => apuAXIL_arready,
			AXIL_arvalid => apuAXIL_arvalid,
			AXIL_rdata => apuAXIL_rdata,
			AXIL_rready => apuAXIL_rready,
			AXIL_rresp => apuAXIL_rresp,
			AXIL_rvalid => apuAXIL_rvalid,
			AXIL_rlast => apuAXIL_rlast,
			AXIL_awaddr => apuAXIL_awaddr,
			AXIL_awprot => apuAXIL_awprot,
			AXIL_awready => apuAXIL_awready,
			AXIL_awvalid => apuAXIL_awvalid,
			AXIL_wdata => apuAXIL_wdata,
			AXIL_wready => apuAXIL_wready,
			AXIL_wstrb => apuAXIL_wstrb,
			AXIL_wvalid => apuAXIL_wvalid,
			AXIL_bready => apuAXIL_bready,
			AXIL_bresp => apuAXIL_bresp,
			AXIL_bvalid => apuAXIL_bvalid,

			stateOp_dbg => hostifStateOp_dbg
		);

	myHshktrack : Hshktrack
		port map (
			reset => reset,
			mclk => mclk,

			trigA => trigA,
			trigB => trigB,
			trigC => trigC,
			trigD => trigD,

			reqInvClearMask => reqInvHshktrackClearMask,
			ackInvClearMask => ackInvHshktrackClearMask,

			getInfoTixVState => hshktrackGetInfoTixVState,
			getInfoTCapt => hshktrackGetInfoTCapt,
			getInfoPtr0Seqbuf => hshktrackGetInfoPtr0Seqbuf,

			reqInvSelect => reqInvHshktrackSelect,
			ackInvSelect => ackInvHshktrackSelect,

			selectStaTixVTrigger => hshktrackSelectStaTixVTrigger,
			selectStaFallingNotRising => hshktrackSelectStaFallingNotRising,
			selectStoTixVTrigger => hshktrackSelectStoTixVTrigger,
			selectStoFallingNotRising => hshktrackSelectStoFallingNotRising,

			reqInvSet => reqInvHshktrackSet,
			ackInvSet => ackInvHshktrackSet,

			setRng => hshktrackSetRng,
			setTCaptMax => hshktrackSetTCaptMax,

			reqInvSetMask => reqInvHshktrackSetMask,
			ackInvSetMask => ackInvHshktrackSetMask,

			setMaskTixVCapture => hshktrackSetMaskTixVCapture,

			reqSeqbufToHostif => reqSeqbufHshktrackToHostif,
			ackSeqbufToHostif => ackSeqbufHshktrackToHostif,
			dneSeqbufToHostif => dneSeqbufHshktrackToHostif,
			avllenSeqbufToHostif => avllenSeqbufHshktrackToHostif,

			seqbufToHostifAXIS_tready => seqbufHshktrackToHostifAXIS_tready,
			seqbufToHostifAXIS_tvalid => seqbufHshktrackToHostifAXIS_tvalid,
			seqbufToHostifAXIS_tdata => seqbufHshktrackToHostifAXIS_tdata,
			seqbufToHostifAXIS_tlast => seqbufHshktrackToHostifAXIS_tlast,

			vsync => vsync,
			cornerGetInfoTixVState => cornerGetInfoTixVState(1 downto 0),
			reqInvRotarySet => reqInvRotarySet,
			rotaryToStepmuxStep => rotaryToStepmuxStep
		);

	myIdent : Ident
		generic map (
			fMclk => fMclk,
			fMemclk => fMemclk
		)
		port map (
			getUnt => identGetUnt,
			getVer => identGetVer,
			getHash => identGetHash,
			getWho => identGetWho,

			getCfgFMclk => identGetCfgFMclk,
			getCfgFMemclk => identGetCfgFMemclk
		);

	myLaser : Laser
		generic map (
			fMclk => fMclk
		)
		port map (
			reset => reset,
			mclk => mclk,

			reqInvSet => reqInvLaserSet,
			ackInvSet => ackInvLaserSet,

			setL => laserSetL,
			setR => laserSetR,

			nss => cs,
			sclk => sclk,
			mosi => mosi
		);

	myLinear : Linear
		port map (
			reset => reset,
			mclk => mclk,
			toStepmuxNslp => linearToStepmuxNslp,
			toStepmuxM0 => linearToStepmuxM0,
			toStepmuxM0z => linearToStepmuxM0z,
			toStepmuxM1 => linearToStepmuxM1,
			toStepmuxDir => linearToStepmuxDir,
			toStepmuxStep => linearToStepmuxStep
		);

	myMemtrack : Memtrack
		port map (
			reset => reset,
			mclk => mclk,

			resetMemclk => resetMemclk,
			memclk => memclk,

			vsync => vsync,
			rgbVideoinToManyAXIS_tlast => rgbVideoinToManyAXIS_tlast,

			reqInvClearMask => reqInvMemtrackClearMask,
			ackInvClearMask => ackInvMemtrackClearMask,

			getInfoTixVState => memtrackGetInfoTixVState,
			getInfoTCapt => memtrackGetInfoTCapt,
			getInfoPtr0Seqbuf => memtrackGetInfoPtr0Seqbuf,

			reqInvSelect => reqInvMemtrackSelect,
			ackInvSelect => ackInvMemtrackSelect,

			selectStaTixVTrigger => memtrackSelectStaTixVTrigger,
			selectStaFallingNotRising => memtrackSelectStaFallingNotRising,
			selectStoTixVTrigger => memtrackSelectStoTixVTrigger,
			selectStoFallingNotRising => memtrackSelectStoFallingNotRising,

			reqInvSet => reqInvMemtrackSet,
			ackInvSet => ackInvMemtrackSet,

			setRng => memtrackSetRng,
			setTCaptMax => memtrackSetTCaptMax,

			reqInvSetMask => reqInvMemtrackSetMask,
			ackInvSetMask => ackInvMemtrackSetMask,

			setMaskTixVCapture => memtrackSetMaskTixVCapture,

			reqSeqbufToHostif => reqSeqbufMemtrackToHostif,
			ackSeqbufToHostif => ackSeqbufMemtrackToHostif,
			dneSeqbufToHostif => dneSeqbufMemtrackToHostif,
			avllenSeqbufToHostif => avllenSeqbufMemtrackToHostif,

			seqbufToHostifAXIS_tready => seqbufMemtrackToHostifAXIS_tready,
			seqbufToHostifAXIS_tvalid => seqbufMemtrackToHostifAXIS_tvalid,
			seqbufToHostifAXIS_tdata => seqbufMemtrackToHostifAXIS_tdata,
			seqbufToHostifAXIS_tlast => seqbufMemtrackToHostifAXIS_tlast,

			reqHdrengToDdrifRd => reqHdrengToDdrifRd,
			ackHdrengToDdrifRd => ackHdrengToDdrifRd,
			reqHdrengToDdrifWr => reqHdrengToDdrifWr,
			ackHdrengToDdrifWr => ackHdrengToDdrifWr,
			ddrAXI_rvalid => ddrAXI_rvalid,
			ddrAXI_rready_sig => ddrAXI_rready_sig,
			ddrAXI_wready => ddrAXI_wready,
			ddrAXI_bvalid => ddrAXI_bvalid,
			ddrAXI_wvalid_sig => ddrAXI_wvalid_sig
		);

	myRender : Render
		port map (
			reset => reset,
			mclk => mclk,

			resetMemclk => resetMemclk,
			memclk => memclk,

			rndmemAXI_awaddr => rndmemAXI_awaddr,
			rndmemAXI_awready => rndmemAXI_awready,
			rndmemAXI_awvalid => rndmemAXI_awvalid,
			rndmemAXI_wdata => rndmemAXI_wdata,
			rndmemAXI_wlast => rndmemAXI_wlast,
			rndmemAXI_wready => rndmemAXI_wready,
			rndmemAXI_wvalid => rndmemAXI_wvalid,

			reqToDdrifWr => reqRenderToDdrifWr,
			ackToDdrifWr => ackRenderToDdrifWr,

			rndmemAXI_araddr => rndmemAXI_araddr,
			rndmemAXI_arready => rndmemAXI_arready,
			rndmemAXI_arvalid => rndmemAXI_arvalid,
			rndmemAXI_rdata => rndmemAXI_rdata,
			rndmemAXI_rlast => rndmemAXI_rlast,
			rndmemAXI_rready => rndmemAXI_rready,
			rndmemAXI_rresp => rndmemAXI_rresp,
			rndmemAXI_rvalid => rndmemAXI_rvalid,

			reqToDdrifRd => reqRenderToDdrifRd,
			ackToDdrifRd => ackRenderToDdrifRd
		);

	myRgbled0 : Rgbled_v1_0
		generic map (
			fMclk => 50000
		)
		port map (
			reset => reset,
			mclk => mclk,
			rgb => rgb0,

			r => rgb0_r,
			g => rgb0_g,
			b => rgb0_b
		);

	myRgbled1 : Rgbled_v1_0
		generic map (
			fMclk => 50000
		)
		port map (
			reset => reset,
			mclk => mclk,
			rgb => rgb1,

			r => rgb1_r,
			g => rgb1_g,
			b => rgb1_b
		);

	myRotary : Rotary
		port map (
			reset => reset,
			mclk => mclk,
			tkclk => tkclk,

			toStepmuxNslp => rotaryToStepmuxNslp,
			toStepmuxM0 => rotaryToStepmuxM0,
			toStepmuxM0z => rotaryToStepmuxM0z,
			toStepmuxM1 => rotaryToStepmuxM1,
			toStepmuxDir => rotaryToStepmuxDir,
			toStepmuxStep => rotaryToStepmuxStep,

			reqInvConfig => reqInvRotaryConfig,
			ackInvConfig => ackInvRotaryConfig,

			configTixVStepmode => rotaryConfigTixVStepmode,
			configTStep => rotaryConfigTStep,

			getInfoTixVState => rotaryGetInfoTixVState,
			getInfoAngle => rotaryGetInfoAngle,

			reqInvMoveto => reqInvRotaryMoveto,
			ackInvMoveto => ackInvRotaryMoveto,

			movetoAngle => rotaryMovetoAngle,

			reqInvSet => reqInvRotarySet,
			ackInvSet => ackInvRotarySet,

			setRng => rotarySetRng,
			setCcwNotCw => rotarySetCcwNotCw,

			reqInvZero => reqInvRotaryZero,
			ackInvZero => ackInvRotaryZero
		);

	myState : State
		port map (
			reset => reset,
			mclk => mclk,
			tkclk => tkclk,
			commok => commok,
			rng => rng,
			rgb => rgb0
		);

	myStepmux : Stepmux
		port map (
			reset => reset,
			mclk => mclk,

			fromLinearNslp => linearToStepmuxNslp,
			fromLinearM0 => linearToStepmuxM0,
			fromLinearM0z => linearToStepmuxM0z,
			fromLinearM1 => linearToStepmuxM1,
			fromLinearDir => linearToStepmuxDir,
			fromLinearStep => linearToStepmuxStep,

			fromRotaryNslp => rotaryToStepmuxNslp,
			fromRotaryM0 => rotaryToStepmuxM0,
			fromRotaryM0z => rotaryToStepmuxM0z,
			fromRotaryM1 => rotaryToStepmuxM1,
			fromRotaryDir => rotaryToStepmuxDir,
			fromRotaryStep => rotaryToStepmuxStep,

			reqInvSet => reqInvStepmuxSet,
			ackInvSet => ackInvStepmuxSet,

			setLinNotRot => stepmuxSetLinNotRot,

			nslp => nslp,

			m0 => m0,
			m0z => m0z,

			m1 => m1,
			m1z => m1z,

			dir => dir,
			step => step
		);

	myTkclksrc : Tkclksrc_Easy_v1_0
		generic map (
			fMclk => fMclk
		)
		port map (
			reset => reset,
			mclk => mclk,
			tkclk => tkclk,

			getTkstTkst => tkclksrcGetTkstTkst,

			reqInvSetTkst => reqInvTkclksrcSetTkst,
			ackInvSetTkst => ackInvTkclksrcSetTkst,

			setTkstTkst => tkclksrcSetTkstTkst,

			stateOp_dbg => tkclksrcStateOp_dbg
		);

	myTrace : Trace
		port map (
			reset => reset,
			mclk => mclk,

			vsync => vsync,
			ixTExp => ixTExp,

			NRow => NRow,
			NCol => NCol,

			rgbFromVideoinAXIS_tready => rgbVideoinToManyAXIS_tready,
			rgbFromVideoinAXIS_tvalid => rgbVideoinToManyAXIS_tvalid,
			rgbFromVideoinAXIS_tdata => rgbVideoinToManyAXIS_tdata,
			rgbFromVideoinAXIS_tlast => rgbVideoinToManyAXIS_tlast,

			tkclksrcGetTkstTkst => tkclksrcGetTkstTkst,

			reqInvAcquire => reqInvTraceAcquire,
			ackInvAcquire => ackInvTraceAcquire,

			reqInvConfig => reqInvTraceConfig,
			ackInvConfig => ackInvTraceConfig,

			configTixVOrient => traceConfigTixVOrient,
			configRow0 => traceConfigRow0,
			configCol0 => traceConfigCol0,

			getInfoTixVState => traceGetInfoTixVState,
			getInfoTkst => traceGetInfoTkst,

			reqInvUnlock => reqInvTraceUnlock,
			ackInvUnlock => ackInvTraceUnlock,

			reqFlgbufToHostif => reqFlgbufTraceToHostif,
			ackFlgbufToHostif => ackFlgbufTraceToHostif,
			dneFlgbufToHostif => dneFlgbufTraceToHostif,
			avllenFlgbufToHostif => avllenFlgbufTraceToHostif,

			flgbufToHostifAXIS_tready => flgbufTraceToHostifAXIS_tready,
			flgbufToHostifAXIS_tvalid => flgbufTraceToHostifAXIS_tvalid,
			flgbufToHostifAXIS_tdata => flgbufTraceToHostifAXIS_tdata,
			flgbufToHostifAXIS_tlast => flgbufTraceToHostifAXIS_tlast
		);

	myVecrend : Vecrend
		port map (
			reset => reset,
			mclk => mclk
		);

	myVideoin : Videoin
		port map (
			reset => reset,
			mclk => mclk,

			fromCamifAXIS_tready => camifToVideoinAXIS_tready,
			fromCamifAXIS_tvalid => camifToVideoinAXIS_tvalid,
			fromCamifAXIS_tdata => camifToVideoinAXIS_tdata,
			fromCamifAXIS_tlast => camifToVideoinAXIS_tlast,

			vsync => vsync,
			NCol => NCol,

			grayToManyAXIS_tready => grayVideoinToManyAXIS_tready,
			grayToManyAXIS_tvalid => grayVideoinToManyAXIS_tvalid,
			grayToManyAXIS_tdata => grayVideoinToManyAXIS_tdata,
			grayToManyAXIS_tlast => grayVideoinToManyAXIS_tlast,

			rgbToManyAXIS_tready => rgbVideoinToManyAXIS_tready,
			rgbToManyAXIS_tvalid => rgbVideoinToManyAXIS_tvalid,
			rgbToManyAXIS_tdata => rgbVideoinToManyAXIS_tdata,
			rgbToManyAXIS_tlast => rgbVideoinToManyAXIS_tlast,

			stateIgr_dbg => videoinStateIgr_dbg,
			stateRgbegr_dbg => videoinStateRgbegr_dbg
		);

	myVidtrack : Vidtrack
		port map (
			reset => reset,
			mclk => mclk,

			trigA => trigA,
			trigB => trigB,
			trigC => trigC,
			trigD => trigD,

			getInfoTixVState => vidtrackGetInfoTixVState,
			getInfoTCapt => vidtrackGetInfoTCapt,
			getInfoPtr0Seqbuf => vidtrackGetInfoPtr0Seqbuf,

			reqInvSelect => reqInvVidtrackSelect,
			ackInvSelect => ackInvVidtrackSelect,

			selectTixVCapture => vidtrackSelectTixVCapture,
			selectStaTixVTrigger => vidtrackSelectStaTixVTrigger,
			selectStaFallingNotRising => vidtrackSelectStaFallingNotRising,
			selectStoTixVTrigger => vidtrackSelectStoTixVTrigger,
			selectStoFallingNotRising => vidtrackSelectStoFallingNotRising,

			reqInvSet => reqInvVidtrackSet,
			ackInvSet => ackInvVidtrackSet,

			setRng => vidtrackSetRng,
			setTCaptMax => vidtrackSetTCaptMax,

			reqSeqbufToHostif => reqSeqbufVidtrackToHostif,
			ackSeqbufToHostif => ackSeqbufVidtrackToHostif,
			dneSeqbufToHostif => dneSeqbufVidtrackToHostif,
			avllenSeqbufToHostif => avllenSeqbufVidtrackToHostif,

			seqbufToHostifAXIS_tready => seqbufVidtrackToHostifAXIS_tready,
			seqbufToHostifAXIS_tvalid => seqbufVidtrackToHostifAXIS_tvalid,
			seqbufToHostifAXIS_tdata => seqbufVidtrackToHostifAXIS_tdata,
			seqbufToHostifAXIS_tlast => seqbufVidtrackToHostifAXIS_tlast,

			videoinStateIgr => videoinStateIgr_dbg,
			videoinStateRgbegr => videoinStateRgbegr_dbg,
			decimStateStream => decimStateStream_dbg,
			decimStateStore => decimStateStore_dbg
		);

	------------------------------------------------------------------------
	-- implementation: mclk wiring and reset (mclk)
	------------------------------------------------------------------------

	-- IP impl.mclk.wiring --- RBEGIN
	mclk <= aclk;
	-- IP impl.mclk.wiring --- REND

	-- IP impl.mclk.wiring.cust --- LINE

	-- IP impl.mclk.rising --- BEGIN
	process (aresetn, mclk)
		-- IP impl.mclk.vars --- BEGIN
		constant imax: natural := 8;
		variable i: natural range 0 to imax;
		-- IP impl.mclk.vars --- END

	begin
		if aresetn='0' then
			-- IP impl.mclk.asyncrst --- BEGIN
			stateMclk <= stateMclkReset;
			reset <= '1';

			i := 0;
			-- IP impl.mclk.asyncrst --- END
			-- IP impl.mclk.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if stateMclk=stateMclkReset then
				if i=imax then
					reset <= '0';

					stateMclk <= stateMclkRun;

				else
					i := i + 1;

					stateMclk <= stateMclkReset;
				end if;

			elsif stateMclk=stateMclkRun then
				if reqResetFromHostif='1' then
					reset <= '1';

					i := 0;

					stateMclk <= stateMclkReset;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.mclk.rising --- END

	------------------------------------------------------------------------
	-- implementation: memclk wiring and reset (memclk)
	------------------------------------------------------------------------

	-- IP impl.memclk.wiring --- BEGIN
	-- IP impl.memclk.wiring --- END

	-- IP impl.memclk.wiring.cust --- LINE

	-- IP impl.memclk.rising --- BEGIN
	process (aresetn, memclk)
		-- IP impl.memclk.vars --- BEGIN
		constant imax: natural := (16*fMemclk)/fMclk+1;
		variable i: natural range 0 to imax;
		-- IP impl.memclk.vars --- END

	begin
		if aresetn='0' then
			-- IP impl.memclk.asyncrst --- BEGIN
			stateMemclk <= stateMemclkReset;
			resetMemclk <= '1';
			reset_memclk <= '1';
			reset_to_memclkm1 <= '1';
			reset_to_memclkm2 <= '1';

			i := 0;
			-- IP impl.memclk.asyncrst --- END
			-- IP impl.memclk.asyncrst.cust --- INSERT

		elsif rising_edge(memclk) then
			if reset_to_memclkm1=reset_to_memclkm2 then
				reset_memclk <= reset_to_memclkm2;
			end if;
			reset_to_memclkm1 <= reset;
			reset_to_memclkm2 <= reset_to_memclkm1;

			if stateMemclk=stateMemclkReset then
				if i=imax then
					if reset_memclk='0' then
						resetMemclk <= '0';

						stateMemclk <= stateMemclkRun;
					end if;

				else
					i := i + 1;

					stateMemclk <= stateMemclkReset;
				end if;

			elsif stateMemclk=stateMemclkRun then
				if reset_memclk='1' then
					resetMemclk <= '1';

					i := 0;

					stateMemclk <= stateMemclkReset;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.memclk.rising --- END

	------------------------------------------------------------------------
	-- implementation: pixrxclk wiring and reset (pixrxclk)
	------------------------------------------------------------------------

	-- IP impl.pixrxclk.wiring --- BEGIN
	-- IP impl.pixrxclk.wiring --- END

	-- IP impl.pixrxclk.wiring.cust --- LINE

	-- IP impl.pixrxclk.rising --- BEGIN
	process (aresetn, pixrxclk)
		-- IP impl.pixrxclk.vars --- BEGIN
		constant imax: natural := (16*fPixrxclk)/fMclk+1;
		variable i: natural range 0 to imax;
		-- IP impl.pixrxclk.vars --- END

	begin
		if aresetn='0' then
			-- IP impl.pixrxclk.asyncrst --- BEGIN
			statePixrxclk <= statePixrxclkReset;
			resetPixrxclk <= '1';
			reset_pixrxclk <= '1';
			reset_to_pixrxclkm1 <= '1';
			reset_to_pixrxclkm2 <= '1';

			i := 0;
			-- IP impl.pixrxclk.asyncrst --- END
			-- IP impl.pixrxclk.asyncrst.cust --- INSERT

		elsif rising_edge(pixrxclk) then
			if reset_to_pixrxclkm1=reset_to_pixrxclkm2 then
				reset_pixrxclk <= reset_to_pixrxclkm2;
			end if;
			reset_to_pixrxclkm1 <= reset;
			reset_to_pixrxclkm2 <= reset_to_pixrxclkm1;

			if statePixrxclk=statePixrxclkReset then
				if i=imax then
					if reset_pixrxclk='0' then
						resetPixrxclk <= '0';

						statePixrxclk <= statePixrxclkRun;
					end if;

				else
					i := i + 1;

					statePixrxclk <= statePixrxclkReset;
				end if;

			elsif statePixrxclk=statePixrxclkRun then
				if reset_pixrxclk='1' then
					resetPixrxclk <= '1';

					i := 0;

					statePixrxclk <= statePixrxclkReset;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.pixrxclk.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	probe <= probe_sig;
	
	-- IP impl.oth.cust --- IBEGIN
	resetnMemclk <= not resetMemclk;

	-- debug scenario I
	--probe_sig(0) <= apuAXIL_awvalid;
	--probe_sig(1) <= apuAXIL_awready_sig;

	--probe_sig(2) <= apuAXIL_wvalid;
	--probe_sig(3) <= apuAXIL_wready_sig;

	--probe_sig(4) <= apuAXIL_bready;
	--probe_sig(5) <= apuAXIL_bvalid_sig;

	-- debug scenario II
	--probe_sig(0) <= mipiAXIS_dbg(0);
	--probe_sig(1) <= mipiAXIS_dbg(1);
	--probe_sig(2) <= mipiAXIS_dbg(3);

	--probe_sig(3) <= video_out_dbg(0);
	--probe_sig(4) <= video_out_dbg(1);
	--probe_sig(5) <= video_out_dbg(3);

	-- debug scenario III
	--probe_sig(0) <= camifToVideoinAXIS_tvalid;
	--probe_sig(1) <= camifToVideoinAXIS_tlast;

	--probe_sig(2) <= grayVideoinToManyAXIS_tvalid;
	--probe_sig(3) <= grayVideoinToManyAXIS_tlast;

	--probe_sig(4) <= rgbVideoinToManyAXIS_tvalid;
	--probe_sig(5) <= rgbVideoinToManyAXIS_tlast;

	-- debug scenario IV
	--probe_sig(0) <= camifToVideoinAXIS_tdata(0);
	--probe_sig(1) <= camifToVideoinAXIS_tdata(1);

	--probe_sig(2) <= grayVideoinToManyAXIS_tdata(0);
	--probe_sig(3) <= grayVideoinToManyAXIS_tdata(1);

	--probe_sig(4) <= rgbVideoinToManyAXIS_tdata(0);
	--probe_sig(5) <= rgbVideoinToManyAXIS_tdata(1);

	-- debug scenario V
	probe_sig(0) <= reqHdrengToDdrifRd;
	probe_sig(1) <= ackHdrengToDdrifRd;

	probe_sig(2) <= reqHdrengToDdrifWr;
	probe_sig(3) <= ackHdrengToDdrifWr;

	probe_sig(4) <= ddrAXI_awvalid_sig;
	probe_sig(5) <= ddrAXI_wvalid_sig;

	--apuAXIL_awready <= apuAXIL_awready_sig;
	--apuAXIL_wready <= apuAXIL_wready_sig;
	--apuAXIL_bvalid <= apuAXIL_bvalid_sig;

	dbg0 <= x"00" & hostifStateOp_dbg;
	dbg1 <= x"00" & camifStateConfig_dbg;

	NCol <= NColRaw(11 downto 1);
	NRow <= NRowRaw(11 downto 1);

	ddrAXI_rready <= ddrAXI_rready_sig;
	ddrAXI_wvalid <= ddrAXI_wvalid_sig;
	-- IP impl.oth.cust --- IEND

end Rtl;
