-- file Stepmux.vhd
-- Stepmux easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Stepmux is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		fromLinearNslp: in std_logic;
		fromLinearM0: in std_logic;
		fromLinearM0z: in std_logic;
		fromLinearM1: in std_logic;
		fromLinearDir: in std_logic;
		fromLinearStep: in std_logic;

		fromRotaryNslp: in std_logic;
		fromRotaryM0: in std_logic;
		fromRotaryM0z: in std_logic;
		fromRotaryM1: in std_logic;
		fromRotaryDir: in std_logic;
		fromRotaryStep: in std_logic;

		reqInvSet: in std_logic;
		ackInvSet: out std_logic;

		setLinNotRot: in std_logic_vector(7 downto 0);

		nslp: out std_logic;
		dir: out std_logic;
		step: out std_logic;

		m0: out std_logic;
		m0z: out std_logic;

		m1: out std_logic;
		m1z: out std_logic
	);
end Stepmux;

architecture Rtl of Stepmux is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv
	);
	signal stateOp: stateOp_t;

	signal linNotRot: std_logic;

	-- IP sigs.op.cust --- INSERT

	---- other
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	ackInvSet <= '1' when stateOp=stateOpInv else '0';
	nslp <= fromLinearNslp when linNotRot='1' else fromRotaryNslp;

	m0 <= fromLinearM0 when linNotRot='1' else fromRotaryM0;
	m0z <= fromLinearM0z when linNotRot='1' else fromRotaryM0z;

	m1 <= fromLinearM1 when linNotRot='1' else fromRotaryM1;
	m1z <= '0';

	dir <= fromLinearDir when linNotRot='1' else fromRotaryDir;
	step <= fromLinearStep when linNotRot='1' else fromRotaryStep;
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- LINE

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- BEGIN
		-- IP impl.op.vars --- END

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- BEGIN
			stateOp <= stateOpInit;
			linNotRot <= '0';

			-- IP impl.op.asyncrst --- END
			-- IP impl.op.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateOp=stateOpInit or (stateOp/=stateOpInv and reqInvSet='1')) then
				-- IP impl.op.syncrst --- RBEGIN
				-- IP impl.op.syncrst --- REND
				-- IP impl.op.syncrst.cust --- INSERT

				if reqInvSet='1' then
					-- IP impl.op.init.invSet --- IBEGIN
					if setLinNotRot=tru8 then
						linNotRot <= '1';
					else
						linNotRot <= '0';
					end if;
					-- IP impl.op.init.invSet --- IEND

					stateOp <= stateOpInv;

				else
					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpInv then
				if reqInvSet='0' then
					stateOp <= stateOpInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;
