-- file Linear.vhd
-- Linear easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Tivsp.all;

entity Linear is
	port (
		reset: in std_logic;
		mclk: in std_logic;
		toStepmuxNslp: out std_logic;
		toStepmuxM0: out std_logic;
		toStepmuxM0z: out std_logic;
		toStepmuxM1: out std_logic;
		toStepmuxDir: out std_logic;
		toStepmuxStep: out std_logic
	);
end Linear;

architecture Rtl of Linear is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- IBEGIN
	process (reset, mclk)
	
	begin
		if reset='1' then
			toStepmuxNslp <= '0';
			toStepmuxM0 <= '0';
			toStepmuxM0z <= '0';
			toStepmuxM1 <= '0';
			toStepmuxDir <= '0';
			toStepmuxStep <= '0';

		elsif rising_edge(mclk) then
			toStepmuxNslp <= '0';
			toStepmuxM0 <= '0';
			toStepmuxM0z <= '0';
			toStepmuxM1 <= '0';
			toStepmuxDir <= '0';
			toStepmuxStep <= '0';
		end if;
	end process;
	-- IP impl.oth.cust --- IEND

end Rtl;
