#ifndef SOC_H
#define SOC_H
#define SYSTEM_PLIC_SYSTEM_CORES_0_EXTERNAL_INTERRUPT 0
#define SYSTEM_PLIC_SYSTEM_CORES_0_EXTERNAL_SUPERVISOR_INTERRUPT 1
#define SYSTEM_PLIC_SYSTEM_CORES_1_EXTERNAL_INTERRUPT 2
#define SYSTEM_PLIC_SYSTEM_CORES_1_EXTERNAL_SUPERVISOR_INTERRUPT 3
#define SYSTEM_PLIC_SYSTEM_CORES_2_EXTERNAL_INTERRUPT 4
#define SYSTEM_PLIC_SYSTEM_CORES_2_EXTERNAL_SUPERVISOR_INTERRUPT 5
#define SYSTEM_PLIC_SYSTEM_CORES_3_EXTERNAL_INTERRUPT 6
#define SYSTEM_PLIC_SYSTEM_CORES_3_EXTERNAL_SUPERVISOR_INTERRUPT 7
#define SYSTEM_PLIC_USER_INTERRUPT_B_INTERRUPT 17
#define SYSTEM_PLIC_USER_INTERRUPT_A_INTERRUPT 16
#define SYSTEM_PLIC_SYSTEM_AXI_A_INTERRUPT 30
#define SYSTEM_PLIC_SYSTEM_UART_0_IO_INTERRUPT 1
#define SYSTEM_PLIC_SYSTEM_SPI_1_IO_INTERRUPT 5
#define SYSTEM_PLIC_SYSTEM_SPI_0_IO_INTERRUPT 4
#define SYSTEM_RISCV_ISA_RV32I 1
#define SYSTEM_RISCV_ISA_EXT_M 1
#define SYSTEM_RISCV_ISA_EXT_A 1
#define SYSTEM_RISCV_ISA_EXT_C 0
#define SYSTEM_RISCV_ISA_EXT_F 1
#define SYSTEM_RISCV_ISA_EXT_D 1
#define SYSTEM_RISCV_ISA_EXT_ZICSR 1
#define SYSTEM_RISCV_ISA_EXT_ZIFENCE 1
#define SYSTEM_CLINT_HZ 200000000
#define SYSTEM_RAM_A_SIZE 4096
#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_DATA_WIDTH_MAX 8
#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_CLOCK_DIVIDER_WIDTH 20
#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_PRE_SAMPLING_SIZE 1
#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_SAMPLING_SIZE 5
#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_POST_SAMPLING_SIZE 2
#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_CTS_GEN 0
#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_RTS_GEN 0
#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_RX_SAMPLE_PER_BIT 8
#define SYSTEM_UART_0_IO_PARAMETER_INIT_CONFIG_BAUDRATE 115200
#define SYSTEM_UART_0_IO_PARAMETER_INIT_CONFIG_DATA_LENGTH 7
#define SYSTEM_UART_0_IO_PARAMETER_INIT_CONFIG_PARITY NONE
#define SYSTEM_UART_0_IO_PARAMETER_INIT_CONFIG_STOP ONE
#define SYSTEM_UART_0_IO_PARAMETER_BUS_CAN_WRITE_CLOCK_DIVIDER_CONFIG 1
#define SYSTEM_UART_0_IO_PARAMETER_BUS_CAN_WRITE_FRAME_CONFIG 1
#define SYSTEM_UART_0_IO_PARAMETER_TX_FIFO_DEPTH 128
#define SYSTEM_UART_0_IO_PARAMETER_RX_FIFO_DEPTH 128
#define SYSTEM_CORES_0_CFU 0
#define SYSTEM_CORES_0_FPU 1
#define SYSTEM_CORES_0_MMU 1
#define SYSTEM_CORES_0_ICACHE_WAYS 4
#define SYSTEM_CORES_0_ICACHE_SIZE 16384
#define SYSTEM_CORES_0_BYTES_PER_LINE 64
#define SYSTEM_CORES_0_DCACHE_WAYS 4
#define SYSTEM_CORES_0_DCACHE_SIZE 16384
#define SYSTEM_CORES_0_BYTES_PER_LINE 64
#define SYSTEM_CORES_0_SUPERVISOR 1
#define SYSTEM_CORES_1_CFU 0
#define SYSTEM_CORES_1_FPU 1
#define SYSTEM_CORES_1_MMU 1
#define SYSTEM_CORES_1_ICACHE_WAYS 4
#define SYSTEM_CORES_1_ICACHE_SIZE 16384
#define SYSTEM_CORES_1_BYTES_PER_LINE 64
#define SYSTEM_CORES_1_DCACHE_WAYS 4
#define SYSTEM_CORES_1_DCACHE_SIZE 16384
#define SYSTEM_CORES_1_BYTES_PER_LINE 64
#define SYSTEM_CORES_1_SUPERVISOR 1
#define SYSTEM_CORES_2_CFU 0
#define SYSTEM_CORES_2_FPU 1
#define SYSTEM_CORES_2_MMU 1
#define SYSTEM_CORES_2_ICACHE_WAYS 4
#define SYSTEM_CORES_2_ICACHE_SIZE 16384
#define SYSTEM_CORES_2_BYTES_PER_LINE 64
#define SYSTEM_CORES_2_DCACHE_WAYS 4
#define SYSTEM_CORES_2_DCACHE_SIZE 16384
#define SYSTEM_CORES_2_BYTES_PER_LINE 64
#define SYSTEM_CORES_2_SUPERVISOR 1
#define SYSTEM_CORES_3_CFU 0
#define SYSTEM_CORES_3_FPU 1
#define SYSTEM_CORES_3_MMU 1
#define SYSTEM_CORES_3_ICACHE_WAYS 4
#define SYSTEM_CORES_3_ICACHE_SIZE 16384
#define SYSTEM_CORES_3_BYTES_PER_LINE 64
#define SYSTEM_CORES_3_DCACHE_WAYS 4
#define SYSTEM_CORES_3_DCACHE_SIZE 16384
#define SYSTEM_CORES_3_BYTES_PER_LINE 64
#define SYSTEM_CORES_3_SUPERVISOR 1
#define SYSTEM_BRIDGE_BMB 0x0
#define SYSTEM_RAM_A_CTRL 0xf9000000
#define SYSTEM_RAM_A_CTRL_SIZE 0x1000
#define SYSTEM_BMB_PERIPHERAL_BMB 0xf8000000
#define SYSTEM_BMB_PERIPHERAL_BMB_SIZE 0x1000000
#define SYSTEM_PLIC_CTRL 0xf8c00000
#define SYSTEM_PLIC_CTRL_SIZE 0x400000
#define SYSTEM_CLINT_CTRL 0xf8b00000
#define SYSTEM_CLINT_CTRL_SIZE 0x10000
#define SYSTEM_UART_0_IO_CTRL 0xf8010000
#define SYSTEM_UART_0_IO_CTRL_SIZE 0x40
#define SYSTEM_SPI_1_IO_CTRL 0xf8015000
#define SYSTEM_SPI_1_IO_CTRL_SIZE 0x1000
#define SYSTEM_SPI_0_IO_CTRL 0xf8014000
#define SYSTEM_SPI_0_IO_CTRL_SIZE 0x1000
#define IO_APB_SLAVE_0_INPUT 0xf8100000
#define IO_APB_SLAVE_0_INPUT_SIZE 0x10000
#define IO_APB_SLAVE_1_INPUT 0xf8110000
#define IO_APB_SLAVE_1_INPUT_SIZE 0x10000
#define IO_APB_SLAVE_2_INPUT 0xf8120000
#define IO_APB_SLAVE_2_INPUT_SIZE 0x10000
#define SYSTEM_DDR_BMB 0x1000
#define SYSTEM_DDR_BMB_SIZE 0x40000000
#define SYSTEM_AXI_A_BMB 0x41000000
#define SYSTEM_AXI_A_BMB_SIZE 0x1000000
#define SYSTEM_CORES_COUNT 4
#endif
