xpm_memory.sv,systemverilog,xpm,../../../../../../../../../opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../opt/Xilinx/Vivado/2024.2/data/ip/xpm/xpm_VCOMP.vhd,
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_9,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
Dpbram_xlnx_size188kB_a8b8.v,verilog,xil_defaultlib,../../../../vsp_core.gen/sources_1/ip/Dpbram_xlnx_size188kB_a8b8/sim/Dpbram_xlnx_size188kB_a8b8.v,
glbl.v,Verilog,xil_defaultlib,glbl.v
