-- file Dpbram_size6kB_a64b64.vhd
-- Dpbram_size6kB_a64b64 dpbram_v1_0 implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 4 Nov 2025
-- IP header --- ABOVE

-- module parameters:
-- size (size [kB]): 6
-- wA (A-side width [bit]): 64
-- wB (B-side width [bit]): 64

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Zuvsp.all;

entity Dpbram_size6kB_a64b64 is
	port (
		rstA: in std_logic;
		clkA: in std_logic;

		enA: in std_logic;
		weA: in std_logic;

		aA: in std_logic_vector(9 downto 0);
		drdA: out std_logic_vector(63 downto 0);
		dwrA: in std_logic_vector(63 downto 0);

		rstB: in std_logic;
		clkB: in std_logic;

		enB: in std_logic;
		weB: in std_logic;

		aB: in std_logic_vector(9 downto 0);
		drdB: out std_logic_vector(63 downto 0);
		dwrB: in std_logic_vector(63 downto 0)
	);
end Dpbram_size6kB_a64b64;

architecture Rtl of Dpbram_size6kB_a64b64 is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	component Dpbram_xlnx_size6kB_a64b64 is
		port (
			clkA: in std_logic;

			enA: in std_logic;
			weA: in std_logic_vector(0 downto 0);

			addrA: in std_logic_vector(9 downto 0);
			doutA: out std_logic_vector(63 downto 0);
			dinA: in std_logic_vector(63 downto 0);

			clkB: in std_logic;

			enB: in std_logic;
			weB: in std_logic_vector(0 downto 0);

			addrB: in std_logic_vector(9 downto 0);
			doutB: out std_logic_vector(63 downto 0);
			dinB: in std_logic_vector(63 downto 0)
		);
	end component;

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- other
	signal weA_sig: std_logic_vector(0 downto 0);
	signal weB_sig: std_logic_vector(0 downto 0);
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	myMnfcore : Dpbram_xlnx_size6kB_a64b64
		port map (
			clkA => clkA,

			enA => enA,
			weA => weA_sig,

			addrA => aA,
			doutA => drdA,
			dinA => dwrA,

			clkB => clkB,

			enB => enB,
			weB => weB_sig,

			addrB => aB,
			doutB => drdB,
			dinB => dwrB
		);

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	weA_sig(0) <= weA;
	weB_sig(0) <= weB;

end Rtl;
