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`timescale 1ps/1ps
module bd_90ba_vfb_0_0_YUV420_DT_Mux (
  input s_axis_aclk,
  input s_axis_aresetn,
  output m_axis_tv,
  input m_axis_tr,
  input yuv420_line_prgs,
  input [5:0] cur_dt,
  output [64-1:0] m_axis_td,
  output [8-1:0] m_axis_tk,
  output [4-1:0]  m_axis_tdst,
  output [96-1:0] m_axis_tu,
  output m_axis_tl,
  output s2_axis_tr ,
  input s2_axis_tv ,
  input [64-1:0] s2_axis_td ,
  input [8-1:0] s2_axis_tk ,
  input [4-1:0]  s2_axis_tdst ,
  input [96-1:0] s2_axis_tu ,
  input s2_axis_tl ,
  output s1_axis_tr ,
  input s1_axis_tv ,
  input [64-1:0] s1_axis_td ,
  input [8-1:0] s1_axis_tk ,
  input [4-1:0]  s1_axis_tdst ,
  input [96-1:0] s1_axis_tu ,
  input s1_axis_tl 
);

wire filt_dt;
 assign filt_dt = (cur_dt == 6'b11000) || (yuv420_line_prgs == 1'b1);


  assign m_axis_tv =  filt_dt ? s1_axis_tv : s2_axis_tv;

  assign m_axis_tl  =  filt_dt ? s1_axis_tl  : s2_axis_tl ;
  
  assign m_axis_tu =  filt_dt ? s1_axis_tu  : s2_axis_tu ;
 
  assign m_axis_tk =  filt_dt ? s1_axis_tk  : s2_axis_tk ;
 
  assign m_axis_td =  filt_dt ? s1_axis_td  : s2_axis_td ;
 
  assign m_axis_tdst  = filt_dt ? s1_axis_tdst  : s2_axis_tdst ;

  assign s1_axis_tr  = filt_dt & m_axis_tr ;

  assign s2_axis_tr  = (~filt_dt) & m_axis_tr;

endmodule

