-- file Director.vhd
-- Director easy model controller implementation
-- copyright: (C) 2016-2020 MPSI Technologies GmbH
-- author: Alexander Wirthmueller (auto-generation)
-- date created: 10 May 2025
-- IP header --- ABOVE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.Dbecore.all;
use work.Zuvsp.all;

entity Director is
	port (
		reset: in std_logic;
		mclk: in std_logic;

		NRowRaw: out std_logic_vector(11 downto 0);
		NColRaw: out std_logic_vector(11 downto 0);

		rng: out std_logic;

		reqInvConfig: in std_logic;
		ackInvConfig: out std_logic;

		configNRowRaw: in std_logic_vector(15 downto 0);
		configNColRaw: in std_logic_vector(15 downto 0);

		reqInvSet: in std_logic;
		ackInvSet: out std_logic;

		setRng: in std_logic_vector(7 downto 0)
	);
end Director;

architecture Rtl of Director is

	------------------------------------------------------------------------
	-- component declarations
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- signal declarations
	------------------------------------------------------------------------

	---- main operation (op)
	type stateOp_t is (
		stateOpInit,
		stateOpInv
	);
	signal stateOp: stateOp_t;

	signal ackInvConfig_sig: std_logic;
	signal ackInvSet_sig: std_logic;

	signal NRowRaw_sig: natural range 0 to 3000;
	signal NColRaw_sig: natural range 0 to 4000;
	signal rng_sig: std_logic;

	-- IP sigs.op.cust --- INSERT

	---- other
	-- IP sigs.oth.cust --- INSERT

begin

	------------------------------------------------------------------------
	-- sub-module instantiation
	------------------------------------------------------------------------

	------------------------------------------------------------------------
	-- implementation: main operation (op)
	------------------------------------------------------------------------

	-- IP impl.op.wiring --- BEGIN
	ackInvConfig <= ackInvConfig_sig;
	ackInvSet <= ackInvSet_sig;

	rng <= rng_sig;
	-- IP impl.op.wiring --- END

	-- IP impl.op.wiring.cust --- RBEGIN
	NRowRaw <= std_logic_vector(to_unsigned(NRowRaw_sig, 12));
	NColRaw <= std_logic_vector(to_unsigned(NColRaw_sig, 12));
	-- IP impl.op.wiring.cust --- REND

	-- IP impl.op.rising --- BEGIN
	process (reset, mclk)
		-- IP impl.op.vars --- BEGIN
		-- IP impl.op.vars --- END

	begin
		if reset='1' then
			-- IP impl.op.asyncrst --- BEGIN
			stateOp <= stateOpInit;
			ackInvConfig_sig <= '0';
			ackInvSet_sig <= '0';
			NRowRaw_sig <= 1944;
			NColRaw_sig <= 2592;
			rng_sig <= '0';

			-- IP impl.op.asyncrst --- END
			-- IP impl.op.asyncrst.cust --- INSERT

		elsif rising_edge(mclk) then
			if (stateOp=stateOpInit or (stateOp/=stateOpInv and (reqInvConfig='1' or reqInvSet='1'))) then
				if reqInvConfig='1' then
					-- IP impl.op.init.invConfig --- IBEGIN
					NRowRaw_sig <= to_integer(unsigned(configNRowRaw));
					NColRaw_sig <= to_integer(unsigned(configNColRaw));

					ackInvConfig_sig <= '1';
					ackInvSet_sig <= '0';
					-- IP impl.op.init.invConfig --- IEND

					stateOp <= stateOpInv;

				elsif reqInvSet='1' then
					-- IP impl.op.init.invSet --- IBEGIN
					if setRng=tru8 then
						rng_sig <= '1';
					else
						rng_sig <= '0';
					end if;

					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '1';
					-- IP impl.op.init.invSet --- IEND

					stateOp <= stateOpInv;

				else
					-- IP impl.op.syncrst --- RBEGIN
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '0';

					-- IP impl.op.syncrst --- REND
					-- IP impl.op.syncrst.cust --- INSERT

					stateOp <= stateOpInit;
				end if;

			elsif stateOp=stateOpInv then
				if ((reqInvConfig='0' and ackInvConfig_sig='1') or (reqInvSet='0' and ackInvSet_sig='1')) then
					-- IP impl.op.inv.reset --- IBEGIN
					ackInvConfig_sig <= '0';
					ackInvSet_sig <= '0';
					-- IP impl.op.inv.reset --- IEND

					stateOp <= stateOpInit;
				end if;
			end if;
		end if;
	end process;
	-- IP impl.op.rising --- END

	------------------------------------------------------------------------
	-- implementation: other 
	------------------------------------------------------------------------

	
	-- IP impl.oth.cust --- INSERT

end Rtl;
