2024.2:
 * Version 6.0 (Rev. 2)
 * New Feature: Added feature enable or disable DPHY IP at subsystem level
 * Revision change in one or more subcores

2024.1.2:
 * Version 6.0 (Rev. 1)
 * No changes

2024.1.1:
 * Version 6.0 (Rev. 1)
 * Revision change in one or more subcores

2024.1:
 * Version 6.0
 * New Feature: C-PHY support
 * Other: IP packaging adjustments to address warnings from IP Packager integrity check
 * Revision change in one or more subcores

2023.2.2:
 * Version 5.4 (Rev. 2)
 * Revision change in one or more subcores

2023.2.1:
 * Version 5.4 (Rev. 1)
 * Revision change in one or more subcores

2023.2:
 * Version 5.4
 * Bug Fix: Fixed REQP-1839 DRC in Video Format Bridge (VFB)
 * Feature Enhancement: Feature request to add a port for frame end received output port when AXI-4 lite interface is enabled
 * Other: Upgrading the version from 5.3 to 5.4
 * Other: Rebrand to AMD copyright information
 * Revision change in one or more subcores

2023.1.2:
 * Version 5.3 (Rev. 1)
 * No changes

2023.1.1:
 * Version 5.3 (Rev. 1)
 * Revision change in one or more subcores

2023.1:
 * Version 5.3
 * Bug Fix: Removed unused ports rxbyteclkhs_cnts_out and rxbyteclkhs_cnts_in when Include Video Format Bridge (VFB) set to False.
 * Feature Enhancement: Enhancement added for MMCM sharing across multiple banks
 * Other: Added VEK280 based Example Design support
 * Revision change in one or more subcores

2022.2.2:
 * Version 5.2
 * No changes

2022.2.1:
 * Version 5.2
 * No changes

2022.2:
 * Version 5.2
 * Feature Enhancement: Register Added to allow dynamic VC selection
 * Other: Corrected the Line Rate support for the SBVB Package devices
 * Revision change in one or more subcores

2022.1.2:
 * Version 5.1 (Rev. 5)
 * No changes

2022.1.1:
 * Version 5.1 (Rev. 5)
 * No changes

2022.1:
 * Version 5.1 (Rev. 5)
 * Feature Enhancement: Active lanes setting using external ports when register interface is disabled
 * Feature Enhancement: ZCU102 Example design enhanced to support 4K60 resolution on HDMI output
 * Feature Enhancement: ISR[27] added to indicate pending writes in internal FIFO
 * Revision change in one or more subcores

2021.2.2:
 * Version 5.1 (Rev. 4)
 * No changes

2021.2.1:
 * Version 5.1 (Rev. 4)
 * No changes

2021.2:
 * Version 5.1 (Rev. 4)
 * General: Added support for Artix ultrascale plus devices
 * Revision change in one or more subcores

2021.1.1:
 * Version 5.1 (Rev. 3)
 * No changes

2021.1:
 * Version 5.1 (Rev. 3)
 * Bug Fix: Fixed VCK190 example design generation issue
 * Bug Fix: Fixed SP701 example design SW application to get proper colors
 * Bug Fix: Fixed buffer full condition(ISR[18]) issues for line rates > 1500
 * Feature Enhancement: IDELAY Tap Value setting in Fixed calibration mode using external ports for 7series devices
 * Feature Enhancement: Example design instance names reduced to support generation using Windows OS
 * Revision change in one or more subcores

2020.3:
 * Version 5.1 (Rev. 2)
 * Feature Enhancement: Changed VCK190 board option list
 * Revision change in one or more subcores

2020.2.2:
 * Version 5.1 (Rev. 1)
 * Feature Enhancement: Board support for a future board

2020.2.1:
 * Version 5.1
 * No changes

2020.2:
 * Version 5.1
 * Feature Enhancement: Allows higher line rate selection for 7series devices
 * Feature Enhancement: Added YUV420 data type (0x18) support
 * Feature Enhancement: Enabled DSI path in VCK190 Application example design
 * Revision change in one or more subcores

2020.1.1:
 * Version 5.0
 * No changes

2020.1:
 * Version 5.0
 * Bug Fix: Fixed multiple beat of TUSER/TLAST issue
 * Bug Fix: Fixed missing lines issue
 * Feature Enhancement: Added MIPI D-PHY v2.0 Specification support with limited line-rate support(upto 3.2G)
 * Other: Added VCK190 based Example Design support
 * Revision change in one or more subcores

2019.2.2:
 * Version 4.1
 * No changes

2019.2.1:
 * Version 4.1
 * No changes

2019.2:
 * Version 4.1
 * New Feature: Added additional parameter to disable register interface, this improves resource count
 * Feature Enhancement: Added MIPI D-PHY v2.0 Specification support and 2.5Gbps line rate support
 * Other: Added SP701 based Example Design support
 * Revision change in one or more subcores

2019.1.3:
 * Version 4.0 (Rev. 2)
 * No changes

2019.1.2:
 * Version 4.0 (Rev. 2)
 * No changes

2019.1.1:
 * Version 4.0 (Rev. 2)
 * Feature Enhancement: Added MIPI D-PHY v1.2 Specification support
 * Revision change in one or more subcores

2019.1:
 * Version 4.0 (Rev. 1)
 * Bug Fix: RAW20 data corruption issue fixed
 * Other: Added support for Versal devices
 * Revision change in one or more subcores

2018.3.1:
 * Version 4.0
 * No changes

2018.3:
 * Version 4.0
 * Feature Enhancement: Updated the core to follow latest UG934 Standard
 * Feature Enhancement: Enhancement for CSI v2.0 enablement: Addition of RAW16/RAW20/YUV422_10bit and VCx feature
 * Feature Enhancement: Added option to enable MIPI D-PHY HS/ESC timeout registers
 * Other: Migrated all the FIFOs to XPM FIFO
 * Revision change in one or more subcores

2018.2:
 * Version 3.0 (Rev. 3)
 * Revision change in one or more subcores

2018.1:
 * Version 3.0 (Rev. 2)
 * Feature Enhancement: ECC,CRC information made available on output ports for the corresponding long packets
 * Feature Enhancement: Dynamic IDELAY TAP value setting in Fixed Calibration mode of 7series
 * Other: Added support for additional 7 series devices
 * Revision change in one or more subcores

2017.4:
 * Version 3.0 (Rev. 1)
 * Port Change: Added dlyctrl_rdy_in port when C_SHARE_IDLYCTRL set to false
 * Feature Enhancement: Support for  Virtex7,Kintex7,Artix7,Zynq-7000 devices at Production status
 * Revision change in one or more subcores

2017.3:
 * Version 3.0
 * Port Change: Grouped *rxp, *rxn ports as *mipi_phy_if interface
 * New Feature: Added example design
 * New Feature: Added board support for FMC LI-IMX274MIPI-FMC V1.0 on ZCU102 HPC0
 * Revision change in one or more subcores

2017.2:
 * Version 2.2 (Rev. 1)
 * Bug Fix: Corrected License status from Included to Purchase in the IP Catalog GUI
 * Revision change in one or more subcores

2017.1:
 * Version 2.2
 * Port Change: Removed system_rst_in port due to system_rst_in removal from MIPI D-PHY
 * New Feature: Fsync(TUSER[0]) generation on Embedded non-image interface added
 * New Feature: GUI option to filter user defined data type packets on image interface
 * Other: High-Speed SelectIO v3.2 IP integration
 * Revision change in one or more subcores

2016.4:
 * Version 2.1 (Rev. 1)
 * Port Change: Added new ports based on Calibration mode parameter
 * Port Change: Removed mmcm_lock_out port due to MMCM removal from MIPI DPHY
 * Bug Fix: Fixed issue with Calibration mode parameters getting updated for MIPI D-PHY
 * Bug Fix: Improved lane to lane skew tolerance from 2 rxbyteclkhs to 6 rxbyteclkhs
 * Revision change in one or more subcores

2016.3:
 * Version 2.1
 * Port Change: Added new ports based on 7-Series support (See Product Guide PG232 "Port Descriptions" section for list of added ports.)
 * Bug Fix: Fixed issue with ECC corruption resulting in an invalid data type
 * Bug Fix: Fixed register access issue for MIPI CSI-2 Rx Controller
 * Other: Added support for 7-Series
 * Other: MIPI DPHY Controller v3.0 integration
 * Revision change in one or more subcores

2016.2:
 * Version 2.0 (Rev. 1)
 * AXI IIC Instance FREQ_KHZ setting corrected to 400Khz
 * Revision change in one or more subcores

2016.1:
 * Version 2.0
 * XPM_CDC integration
 * DPHY v2.0 integration
 * Added GUI option to include or exclude(Beta feature) Video Format Bridge(VFB).
 * Support for additional data types in VFB(User defined byte based data types)
 * Added GUI option to include or exclude shareable logic resources in the core(MMCM and PLL)
 * Clocking architecture updates in MIPI D-PHY RX High-Speed datapath
 * High-Speed Select IO IP integration
 * Enhanced IO planner feature with more IO selection options
 * IP top level ports will differ compared to mipi_csi2_rx_subsystem_1_0 IP due to Shared Logic feature
 * Revision change in one or more subcores

2015.4.2:
 * Version 1.0 (Rev. 1)
 * No changes

2015.4.1:
 * Version 1.0 (Rev. 1)
 * No changes

2015.4:
 * Version 1.0 (Rev. 1)
 * Revision change in one or more subcores

2015.3:
 * Version 1.0
 * Intial release
 * Subsystem with integrated DPHY and CSI-2 Rx Controller.
 * Support for 1 to 4 DPHY lanes
 * AXI4-Stream Video output interface
 * Optional AXI IIC support for Camera Control Interface (CCI)
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

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