// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
// -------------------------------------------------------------------------------

`timescale 1 ps / 1 ps

(* BLOCK_STUB = "true" *)
module design_1 (
  cs,
  csi_clk_n,
  csi_clk_p,
  csi_d0_n,
  csi_d0_p,
  csi_d1_n,
  csi_d1_p,
  csi_d2_n,
  csi_d2_p,
  csi_d3_n,
  csi_d3_p,
  dir,
  mosi,
  nslp,
  probe,
  rgb0_b,
  rgb0_g,
  rgb0_r,
  rgb1_b,
  rgb1_g,
  rgb1_r,
  scl,
  sclk,
  sda,
  step,
  m0,
  m0z,
  m1,
  m1z
);

  (* X_INTERFACE_IGNORE = "true" *)
  output cs;
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CSI_CLK_N CLK" *)
  (* X_INTERFACE_MODE = "slave CLK.CSI_CLK_N" *)
  (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CSI_CLK_N, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_csi_clk_n_0, INSERT_VIP 0" *)
  input csi_clk_n;
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CSI_CLK_P CLK" *)
  (* X_INTERFACE_MODE = "slave CLK.CSI_CLK_P" *)
  (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CSI_CLK_P, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_csi_clk_p_0, INSERT_VIP 0" *)
  input csi_clk_p;
  (* X_INTERFACE_IGNORE = "true" *)
  input csi_d0_n;
  (* X_INTERFACE_IGNORE = "true" *)
  input csi_d0_p;
  (* X_INTERFACE_IGNORE = "true" *)
  input csi_d1_n;
  (* X_INTERFACE_IGNORE = "true" *)
  input csi_d1_p;
  (* X_INTERFACE_IGNORE = "true" *)
  input csi_d2_n;
  (* X_INTERFACE_IGNORE = "true" *)
  input csi_d2_p;
  (* X_INTERFACE_IGNORE = "true" *)
  input csi_d3_n;
  (* X_INTERFACE_IGNORE = "true" *)
  input csi_d3_p;
  (* X_INTERFACE_IGNORE = "true" *)
  output dir;
  (* X_INTERFACE_IGNORE = "true" *)
  output mosi;
  (* X_INTERFACE_IGNORE = "true" *)
  output nslp;
  (* X_INTERFACE_IGNORE = "true" *)
  output [5:0]probe;
  (* X_INTERFACE_IGNORE = "true" *)
  output rgb0_b;
  (* X_INTERFACE_IGNORE = "true" *)
  output rgb0_g;
  (* X_INTERFACE_IGNORE = "true" *)
  output rgb0_r;
  (* X_INTERFACE_IGNORE = "true" *)
  output rgb1_b;
  (* X_INTERFACE_IGNORE = "true" *)
  output rgb1_g;
  (* X_INTERFACE_IGNORE = "true" *)
  output rgb1_r;
  (* X_INTERFACE_IGNORE = "true" *)
  inout scl;
  (* X_INTERFACE_IGNORE = "true" *)
  output sclk;
  (* X_INTERFACE_IGNORE = "true" *)
  inout sda;
  (* X_INTERFACE_IGNORE = "true" *)
  output step;
  (* X_INTERFACE_IGNORE = "true" *)
  output m0;
  (* X_INTERFACE_IGNORE = "true" *)
  output m0z;
  (* X_INTERFACE_IGNORE = "true" *)
  output m1;
  (* X_INTERFACE_IGNORE = "true" *)
  output m1z;

  // stub module has no contents

endmodule
