-------------------------------------
| Tool Version : Vivado v.2024.2
| Date         : Mon Apr 13 17:53:01 2026
| Host         : jim
| Design       : design_1
| Device       : xczu1cg-sbva484-1-E-
-------------------------------------

For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US

***********************
Running Pre-CRP Checker
***********************
Number of global clocks: 4
	Number of BUFGCE: 2
	Number of BUFGCE_HDIO: 0
	Number of BUFG_CTRL: 0
	Number of BUFGCE_DIV: 0
	Number of BUFG_GT: 0
	Number of BUFG_PS: 2
	Number of BUFG_FABRIC: 0
	Running suboptimal placement checker for 3 clocks (and their loads) which do not have the CLOCK_LOW_FANOUT property but have a fanout less than 2000...
Pre-CRP Checker took 0 secs

********************************
Clock Net Route Info (CRP Input)
********************************
Clock 1: design_1_i/zynq_ultra_ps_e_0/U0/pl_clk0
	Clock source type: BUFG_PS
	Clock source region: X0Y2
	Clock regions with locked loads: X0Y0 X0Y1 X0Y2 
	initial rect ((0, 0), (0, 2))

Clock 2: design_1_i/zynq_ultra_ps_e_0/U0/pl_clk1
	Clock source type: BUFG_PS
	Clock source region: X0Y2
	Clock regions with locked loads: X0Y0 
	initial rect ((0, 0), (0, 2))

Clock 3: design_1_i/Vsp_core_0/U0/myCamif/myMipirx/inst/phy/inst/inst/bd_7289_phy_0_rx_support_i/rxbyteclkhs
	Clock source type: BUFGCE
	Clock source region: X0Y0
	Clock regions with locked loads: X0Y1 
	initial rect ((0, 0), (0, 2))

Clock 4: design_1_i/Vsp_core_0/U0/myCamif/myMipirx/inst/phy/inst/inst/bd_7289_phy_0_rx_support_i/slave_rx.bd_7289_phy_0_rx_hssio_i/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/pll0_clkout0_out
	Clock source type: BUFGCE
	Clock source region: X0Y1
	initial rect ((0, 1), (0, 1))



*****************
User Constraints:
*****************
No user constraints found


