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//-----------------------------------------------------------------------------
// bd_90ba_phy_0_clock_module.v
//-----------------------------------------------------------------------------
//
// Filename        : bd_90ba_phy_0_clock_module.v
// Version         : v1.0
// Description     : MMCM Wrapper
// Verilog-Standard: Verilog'2001
//-----------------------------------------------------------------------------
//-- Structure:
//--            --mipi_dphy_v4_3_dphy_top.v
//--               -- mipi_dphy_v4_3_rx_fab_top.v
//                     -- mipi_dphy_v4_3_rx_clk_lane.v
//                     -- mipi_dphy_v4_3_rx_data_lane.v
//                     -- mipi_dphy_v4_3_rx_dphy_reg.v
//                 -- bd_90ba_phy_0_clock_module.v
//-----------------------------------------------------------------------------
// Naming Conventions:
//      active low signals:                     "*_n"
//      clock signals:                          "clk", "clk_div#", "clk_#x"
//      reset signals:                          "rst", "rst_n"
//      parameters:                             "C_*"
//      user defined types:                     "*_TYPE"
//      state machine next state:               "*_ns"
//      state machine current state:            "*_cs"
//      combinatorial signals:                  "*_com"
//      pipelined or register delay signals:    "*_d#"
//      counter signals:                        "*cnt*"
//      clock enable signals:                   "*_ce"
//      internal version of output port         "*_i"
//      device pins:                            "*_pin"
//      component instantiations:               "<MODULE>I_<#|FUNC>
//-----------------------------------------------------------------------------

///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps

(* DowngradeIPIdentifiedWarnings="yes" *)
module bd_90ba_phy_0_clock_module
#(
   parameter C_DPHY_LANES = 2,
   parameter MTBF_SYNC_STAGES = 3,
   parameter C_HS_LINE_RATE = 1000,
   parameter C_STABLE_CLK_PERIOD = 10,
   parameter C_TXPLL_CLKIN_PERIOD = 8.0,
   parameter EN_DPHY_IO = 1
   )
   (
       input               mmcm_clk_in,
       output              mmcm_clk_out0,
       input               cl_rxclkactivehs,
       output              rxbyteclkhs,
       input               pll_clk_in,
       output              clkoutphy_out,
       output              pll_locked,
       input               pll_reset,
       
       output              mmcm_locked,
       input               mmcm_reset
   );

   wire               pll_clk_in_w;
   wire               pll_locked_w;
   wire               pll_locked_sync;
   reg                clkoutphy_en;
   reg  [7:0]         clkoutphy_en_cntr;


assign  rxbyteclkhs   = 1'b0;
assign  mmcm_locked   = 1'b1;
assign  mmcm_clk_out0 = 1'b0;
assign  pll_clk_in_w  = pll_clk_in;

   //TXPLL Attributes for 1500 MHz CLKOUTPHY
   localparam  C_TXPLL_CLKIN_PERIOD_T   = 5.000;
   localparam  C_TXPLL_CLKOUTPHY_MODE   = "VCO";
   localparam  C_PLL_DIVCLK_DIVIDE      = 2;
   localparam  C_TXPLL_CLKFBOUT_MULT    = 15;
   localparam  C_TXPLL_CLKOUT0_DIVIDE   = 8;
   localparam  C_TXPLL_CLKOUT1_DIVIDE   = 8;

// This below logic will not get generated for Design (i.e. It will be
// generated for Exdes)
// As this module itself will not get generated if support level is 0
// This module is being used for Exdes So below logic has to be there

// ONLY FOR VERSAL 
//
// This below logic will not get generated for Design (i.e. It will be
// generated for Exdes)
// As this module itself will not get generated if support level is 0
// This module is being used for Exdes So below logic has to be there

endmodule

