// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024
// Date        : Mon Apr 13 17:52:00 2026
// Host        : jim running 64-bit Ubuntu 24.04.3 LTS
// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_Vsp_core_0_0_stub.v
// Design      : design_1_Vsp_core_0_0
// Purpose     : Stub declaration of top-level module interface
// Device      : xczu1cg-sbva484-1-e
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* CHECK_LICENSE_TYPE = "design_1_Vsp_core_0_0,Vsp_core,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *) 
(* x_core_info = "Vsp_core,Vivado 2024.2" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aresetn, aclk, memclk, apuAXIL_araddr, 
  apuAXIL_arprot, apuAXIL_arready, apuAXIL_arvalid, apuAXIL_rdata, apuAXIL_rready, 
  apuAXIL_rresp, apuAXIL_rvalid, apuAXIL_rlast, apuAXIL_awaddr, apuAXIL_awprot, 
  apuAXIL_awready, apuAXIL_awvalid, apuAXIL_wdata, apuAXIL_wready, apuAXIL_wstrb, 
  apuAXIL_wvalid, apuAXIL_bready, apuAXIL_bresp, apuAXIL_bvalid, rpuAXIL_araddr, 
  rpuAXIL_arprot, rpuAXIL_arready, rpuAXIL_arvalid, rpuAXIL_rdata, rpuAXIL_rready, 
  rpuAXIL_rresp, rpuAXIL_rvalid, rpuAXIL_rlast, rpuAXIL_awaddr, rpuAXIL_awprot, 
  rpuAXIL_awready, rpuAXIL_awvalid, rpuAXIL_wdata, rpuAXIL_wready, rpuAXIL_wstrb, 
  rpuAXIL_wvalid, rpuAXIL_bready, rpuAXIL_bresp, rpuAXIL_bvalid, ddrAXI_rready, 
  ddrAXI_wvalid, probe, scl, sda, csi_clk_p, csi_clk_n, csi_d0_p, csi_d0_n, csi_d1_p, csi_d1_n, 
  csi_d2_p, csi_d2_n, csi_d3_p, csi_d3_n, ddrAXI_arid, ddrAXI_araddr, ddrAXI_arburst, 
  ddrAXI_arcache, ddrAXI_arlen, ddrAXI_arlock, ddrAXI_arprot, ddrAXI_arqos, ddrAXI_arready, 
  ddrAXI_arregion, ddrAXI_arsize, ddrAXI_arvalid, ddrAXI_rid, ddrAXI_rdata, ddrAXI_rlast, 
  ddrAXI_rresp, ddrAXI_rvalid, ddrAXI_awid, ddrAXI_awaddr, ddrAXI_awburst, ddrAXI_awcache, 
  ddrAXI_awlen, ddrAXI_awlock, ddrAXI_awprot, ddrAXI_awqos, ddrAXI_awready, ddrAXI_awregion, 
  ddrAXI_awsize, ddrAXI_awvalid, ddrAXI_wdata, ddrAXI_wlast, ddrAXI_wready, ddrAXI_wstrb, 
  ddrAXI_bid, ddrAXI_bready, ddrAXI_bresp, ddrAXI_bvalid, cs, sclk, mosi, rgb0_r, rgb0_g, rgb0_b, 
  rgb1_r, rgb1_g, rgb1_b, nslp, m0, m0z, m1, m1z, dir, step)
/* synthesis syn_black_box black_box_pad_pin="aresetn,apuAXIL_araddr[39:0],apuAXIL_arprot[2:0],apuAXIL_arready,apuAXIL_arvalid,apuAXIL_rdata[63:0],apuAXIL_rready,apuAXIL_rresp[1:0],apuAXIL_rvalid,apuAXIL_rlast,apuAXIL_awaddr[39:0],apuAXIL_awprot[2:0],apuAXIL_awready,apuAXIL_awvalid,apuAXIL_wdata[63:0],apuAXIL_wready,apuAXIL_wstrb[7:0],apuAXIL_wvalid,apuAXIL_bready,apuAXIL_bresp[1:0],apuAXIL_bvalid,rpuAXIL_araddr[31:0],rpuAXIL_arprot[2:0],rpuAXIL_arready,rpuAXIL_arvalid,rpuAXIL_rdata[31:0],rpuAXIL_rready,rpuAXIL_rresp[1:0],rpuAXIL_rvalid,rpuAXIL_rlast,rpuAXIL_awaddr[31:0],rpuAXIL_awprot[2:0],rpuAXIL_awready,rpuAXIL_awvalid,rpuAXIL_wdata[31:0],rpuAXIL_wready,rpuAXIL_wstrb[3:0],rpuAXIL_wvalid,rpuAXIL_bready,rpuAXIL_bresp[1:0],rpuAXIL_bvalid,ddrAXI_rready,ddrAXI_wvalid,probe[5:0],scl,sda,csi_clk_p,csi_clk_n,csi_d0_p,csi_d0_n,csi_d1_p,csi_d1_n,csi_d2_p,csi_d2_n,csi_d3_p,csi_d3_n,ddrAXI_arid[5:0],ddrAXI_araddr[39:0],ddrAXI_arburst[1:0],ddrAXI_arcache[3:0],ddrAXI_arlen[7:0],ddrAXI_arlock[0:0],ddrAXI_arprot[2:0],ddrAXI_arqos[3:0],ddrAXI_arready,ddrAXI_arregion[3:0],ddrAXI_arsize[2:0],ddrAXI_arvalid,ddrAXI_rid[5:0],ddrAXI_rdata[127:0],ddrAXI_rlast,ddrAXI_rresp[1:0],ddrAXI_rvalid,ddrAXI_awid[5:0],ddrAXI_awaddr[39:0],ddrAXI_awburst[1:0],ddrAXI_awcache[3:0],ddrAXI_awlen[7:0],ddrAXI_awlock[0:0],ddrAXI_awprot[2:0],ddrAXI_awqos[3:0],ddrAXI_awready,ddrAXI_awregion[3:0],ddrAXI_awsize[2:0],ddrAXI_awvalid,ddrAXI_wdata[127:0],ddrAXI_wlast,ddrAXI_wready,ddrAXI_wstrb[15:0],ddrAXI_bid[5:0],ddrAXI_bready,ddrAXI_bresp[1:0],ddrAXI_bvalid,cs,sclk,mosi,rgb0_r,rgb0_g,rgb0_b,rgb1_r,rgb1_g,rgb1_b,nslp,m0,m0z,m1,m1z,dir,step" */
/* synthesis syn_force_seq_prim="aclk" */
/* synthesis syn_force_seq_prim="memclk" */;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 aresetn RST" *) (* x_interface_mode = "slave aresetn" *) (* x_interface_parameter = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aresetn;
  (* x_interface_info = "xilinx.com:signal:clock:1.0 aclk CLK" *) (* x_interface_mode = "slave aclk" *) (* x_interface_parameter = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF apuAXIL:rpuAXIL, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk0, INSERT_VIP 0" *) input aclk /* synthesis syn_isclock = 1 */;
  (* x_interface_info = "xilinx.com:signal:clock:1.0 memclk CLK" *) (* x_interface_mode = "slave memclk" *) (* x_interface_parameter = "XIL_INTERFACENAME memclk, ASSOCIATED_BUSIF ddrAXI, FREQ_HZ 325000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk1, INSERT_VIP 0" *) input memclk /* synthesis syn_isclock = 1 */;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL ARADDR" *) (* x_interface_mode = "slave apuAXIL" *) (* x_interface_parameter = "XIL_INTERFACENAME apuAXIL, DATA_WIDTH 64, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [39:0]apuAXIL_araddr;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL ARPROT" *) input [2:0]apuAXIL_arprot;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL ARREADY" *) output apuAXIL_arready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL ARVALID" *) input apuAXIL_arvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL RDATA" *) output [63:0]apuAXIL_rdata;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL RREADY" *) input apuAXIL_rready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL RRESP" *) output [1:0]apuAXIL_rresp;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL RVALID" *) output apuAXIL_rvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL RLAST" *) output apuAXIL_rlast;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL AWADDR" *) input [39:0]apuAXIL_awaddr;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL AWPROT" *) input [2:0]apuAXIL_awprot;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL AWREADY" *) output apuAXIL_awready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL AWVALID" *) input apuAXIL_awvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL WDATA" *) input [63:0]apuAXIL_wdata;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL WREADY" *) output apuAXIL_wready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL WSTRB" *) input [7:0]apuAXIL_wstrb;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL WVALID" *) input apuAXIL_wvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL BREADY" *) input apuAXIL_bready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL BRESP" *) output [1:0]apuAXIL_bresp;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 apuAXIL BVALID" *) output apuAXIL_bvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL ARADDR" *) (* x_interface_mode = "slave rpuAXIL" *) (* x_interface_parameter = "XIL_INTERFACENAME rpuAXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 200000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [31:0]rpuAXIL_araddr;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL ARPROT" *) input [2:0]rpuAXIL_arprot;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL ARREADY" *) output rpuAXIL_arready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL ARVALID" *) input rpuAXIL_arvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL RDATA" *) output [31:0]rpuAXIL_rdata;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL RREADY" *) input rpuAXIL_rready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL RRESP" *) output [1:0]rpuAXIL_rresp;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL RVALID" *) output rpuAXIL_rvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL RLAST" *) output rpuAXIL_rlast;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL AWADDR" *) input [31:0]rpuAXIL_awaddr;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL AWPROT" *) input [2:0]rpuAXIL_awprot;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL AWREADY" *) output rpuAXIL_awready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL AWVALID" *) input rpuAXIL_awvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL WDATA" *) input [31:0]rpuAXIL_wdata;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL WREADY" *) output rpuAXIL_wready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL WSTRB" *) input [3:0]rpuAXIL_wstrb;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL WVALID" *) input rpuAXIL_wvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL BREADY" *) input rpuAXIL_bready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL BRESP" *) output [1:0]rpuAXIL_bresp;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 rpuAXIL BVALID" *) output rpuAXIL_bvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI RREADY" *) (* x_interface_mode = "master ddrAXI" *) (* x_interface_parameter = "XIL_INTERFACENAME ddrAXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 325000000, ID_WIDTH 6, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output ddrAXI_rready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI WVALID" *) output ddrAXI_wvalid;
  output [5:0]probe;
  inout scl;
  inout sda;
  (* x_interface_info = "xilinx.com:signal:clock:1.0 csi_clk_p CLK" *) (* x_interface_mode = "slave csi_clk_p" *) (* x_interface_parameter = "XIL_INTERFACENAME csi_clk_p, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_csi_clk_p_0, INSERT_VIP 0" *) input csi_clk_p;
  (* x_interface_info = "xilinx.com:signal:clock:1.0 csi_clk_n CLK" *) (* x_interface_mode = "slave csi_clk_n" *) (* x_interface_parameter = "XIL_INTERFACENAME csi_clk_n, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_csi_clk_n_0, INSERT_VIP 0" *) input csi_clk_n;
  input csi_d0_p;
  input csi_d0_n;
  input csi_d1_p;
  input csi_d1_n;
  input csi_d2_p;
  input csi_d2_n;
  input csi_d3_p;
  input csi_d3_n;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI ARID" *) output [5:0]ddrAXI_arid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI ARADDR" *) output [39:0]ddrAXI_araddr;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI ARBURST" *) output [1:0]ddrAXI_arburst;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI ARCACHE" *) output [3:0]ddrAXI_arcache;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI ARLEN" *) output [7:0]ddrAXI_arlen;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI ARLOCK" *) output [0:0]ddrAXI_arlock;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI ARPROT" *) output [2:0]ddrAXI_arprot;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI ARQOS" *) output [3:0]ddrAXI_arqos;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI ARREADY" *) input ddrAXI_arready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI ARREGION" *) output [3:0]ddrAXI_arregion;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI ARSIZE" *) output [2:0]ddrAXI_arsize;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI ARVALID" *) output ddrAXI_arvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI RID" *) input [5:0]ddrAXI_rid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI RDATA" *) input [127:0]ddrAXI_rdata;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI RLAST" *) input ddrAXI_rlast;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI RRESP" *) input [1:0]ddrAXI_rresp;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI RVALID" *) input ddrAXI_rvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI AWID" *) output [5:0]ddrAXI_awid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI AWADDR" *) output [39:0]ddrAXI_awaddr;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI AWBURST" *) output [1:0]ddrAXI_awburst;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI AWCACHE" *) output [3:0]ddrAXI_awcache;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI AWLEN" *) output [7:0]ddrAXI_awlen;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI AWLOCK" *) output [0:0]ddrAXI_awlock;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI AWPROT" *) output [2:0]ddrAXI_awprot;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI AWQOS" *) output [3:0]ddrAXI_awqos;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI AWREADY" *) input ddrAXI_awready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI AWREGION" *) output [3:0]ddrAXI_awregion;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI AWSIZE" *) output [2:0]ddrAXI_awsize;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI AWVALID" *) output ddrAXI_awvalid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI WDATA" *) output [127:0]ddrAXI_wdata;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI WLAST" *) output ddrAXI_wlast;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI WREADY" *) input ddrAXI_wready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI WSTRB" *) output [15:0]ddrAXI_wstrb;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI BID" *) input [5:0]ddrAXI_bid;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI BREADY" *) output ddrAXI_bready;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI BRESP" *) input [1:0]ddrAXI_bresp;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 ddrAXI BVALID" *) input ddrAXI_bvalid;
  output cs;
  output sclk;
  output mosi;
  output rgb0_r;
  output rgb0_g;
  output rgb0_b;
  output rgb1_r;
  output rgb1_g;
  output rgb1_b;
  output nslp;
  output m0;
  output m0z;
  output m1;
  output m1z;
  output dir;
  output step;
endmodule
