This design is targeted for xczu1cg board (part number: xczu1cg-sbva484-1-e)

Zynq UltraScale+ Design Summary

Device	xczu1cg
SpeedGrade	-1
Part	xczu1cg-sbva484-1-e
Description	Zynq UltraScale+ PS Configuration Report
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction	Drive Strength(mA)
MIO 0	Quad SPI Flash	sclk_out	cmos	fast	pullup	out	12
MIO 1	Quad SPI Flash	miso_mo1	cmos	fast	pullup	inout	12
MIO 2	Quad SPI Flash	mo2	cmos	fast	pullup	inout	12
MIO 3	Quad SPI Flash	mo3	cmos	fast	pullup	inout	12
MIO 4	Quad SPI Flash	mosi_mi0	cmos	fast	pullup	inout	12
MIO 5	Quad SPI Flash	n_ss_out	cmos	fast	pullup	out	12
MIO 6	Feedback Clk	clk_for_lpbk	cmos	fast	pullup	out	12
MIO 7	GPIO0 MIO	gpio0[7]	cmos	fast	pullup	inout	12
MIO 8	I2C 1	scl_out	cmos	fast	pullup	inout	12
MIO 9	I2C 1	sda_out	cmos	fast	pullup	inout	12
MIO 10	UART 0	rxd	cmos	fast	pullup	in	12
MIO 11	UART 0	txd	cmos	fast	pullup	out	12
MIO 12	GPIO0 MIO	gpio0[12]	cmos	fast	pullup	inout	12
MIO 13	GPIO0 MIO	gpio0[13]	cmos	fast	pullup	inout	12
MIO 14	GPIO0 MIO	gpio0[14]	cmos	fast	pullup	inout	12
MIO 15	GPIO0 MIO	gpio0[15]	cmos	fast	pullup	inout	12
MIO 16	GPIO0 MIO	gpio0[16]	cmos	fast	pullup	inout	12
MIO 17	GPIO0 MIO	gpio0[17]	cmos	fast	pullup	inout	12
MIO 18	GPIO0 MIO	gpio0[18]	cmos	fast	pullup	inout	12
MIO 19	GPIO0 MIO	gpio0[19]	cmos	fast	pullup	inout	12
MIO 20	GPIO0 MIO	gpio0[20]	cmos	fast	pullup	inout	12
MIO 21	GPIO0 MIO	gpio0[21]	cmos	fast	pullup	inout	12
MIO 22	GPIO0 MIO	gpio0[22]	cmos	fast	pullup	inout	12
MIO 23	GPIO0 MIO	gpio0[23]	cmos	fast	pullup	inout	12
MIO 24	GPIO0 MIO	gpio0[24]	cmos	fast	pullup	inout	12
MIO 25	GPIO0 MIO	gpio0[25]	cmos	fast	pullup	inout	12
MIO 26	PMU GPI 0	gpi[0]	cmos	fast	pullup	in	12
MIO 27	GPIO1 MIO	gpio1[27]	cmos	fast	pullup	inout	12
MIO 28	GPIO1 MIO	gpio1[28]	cmos	fast	pullup	inout	12
MIO 29	GPIO1 MIO	gpio1[29]	cmos	fast	pullup	inout	12
MIO 30	GPIO1 MIO	gpio1[30]	cmos	fast	pullup	inout	12
MIO 31	GPIO1 MIO	gpio1[31]	cmos	fast	pullup	inout	12
MIO 32	GPIO1 MIO	gpio1[32]	cmos	fast	pullup	inout	12
MIO 33	GPIO1 MIO	gpio1[33]	cmos	fast	pullup	inout	12
MIO 34	PMU GPO 2	gpo[2]	cmos	fast	pullup	out	12
MIO 35	GPIO1 MIO	gpio1[35]	cmos	fast	pullup	inout	12
MIO 36	GPIO1 MIO	gpio1[36]	cmos	fast	pullup	inout	12
MIO 37	GPIO1 MIO	gpio1[37]	cmos	fast	pullup	inout	12
MIO 38	SPI 0	sclk_out	cmos	fast	pullup	inout	12
MIO 39	GPIO1 MIO	gpio1[39]	cmos	fast	pullup	inout	12
MIO 40	GPIO1 MIO	gpio1[40]	cmos	fast	pullup	inout	12
MIO 41	SPI 0	n_ss_out[0]	cmos	fast	pullup	inout	12
MIO 42	SPI 0	miso	cmos	fast	pullup	inout	12
MIO 43	SPI 0	mosi	cmos	fast	pullup	inout	12
MIO 44	GPIO1 MIO	gpio1[44]	cmos	fast	pullup	inout	12
MIO 45	SD 1	sdio1_cd_n	cmos	fast	pullup	in	12
MIO 46	SD 1	sdio1_data_out[0]	cmos	fast	pullup	inout	12
MIO 47	SD 1	sdio1_data_out[1]	cmos	fast	pullup	inout	12
MIO 48	SD 1	sdio1_data_out[2]	cmos	fast	pullup	inout	12
MIO 49	SD 1	sdio1_data_out[3]	cmos	fast	pullup	inout	12
MIO 50	SD 1	sdio1_cmd_out	cmos	fast	pullup	inout	12
MIO 51	SD 1	sdio1_clk_out	cmos	fast	pullup	out	12
MIO 52	Gem 2	rgmii_tx_clk	cmos	fast	pullup	out	12
MIO 53	Gem 2	rgmii_txd[0]	cmos	fast	pullup	out	12
MIO 54	Gem 2	rgmii_txd[1]	cmos	fast	pullup	out	12
MIO 55	Gem 2	rgmii_txd[2]	cmos	fast	pullup	out	12
MIO 56	Gem 2	rgmii_txd[3]	cmos	fast	pullup	out	12
MIO 57	Gem 2	rgmii_tx_ctl	cmos	fast	pullup	out	12
MIO 58	Gem 2	rgmii_rx_clk	cmos	fast	pullup	in	12
MIO 59	Gem 2	rgmii_rxd[0]	cmos	fast	pullup	in	12
MIO 60	Gem 2	rgmii_rxd[1]	cmos	fast	pullup	in	12
MIO 61	Gem 2	rgmii_rxd[2]	cmos	fast	pullup	in	12
MIO 62	Gem 2	rgmii_rxd[3]	cmos	fast	pullup	in	12
MIO 63	Gem 2	rgmii_rx_ctl	cmos	fast	pullup	in	12
MIO 64	USB 1	ulpi_clk_in	cmos	fast	pullup	in	12
MIO 65	USB 1	ulpi_dir	cmos	fast	pullup	in	12
MIO 66	USB 1	ulpi_tx_data[2]	cmos	fast	pullup	inout	12
MIO 67	USB 1	ulpi_nxt	cmos	fast	pullup	in	12
MIO 68	USB 1	ulpi_tx_data[0]	cmos	fast	pullup	inout	12
MIO 69	USB 1	ulpi_tx_data[1]	cmos	fast	pullup	inout	12
MIO 70	USB 1	ulpi_stp	cmos	fast	pullup	out	12
MIO 71	USB 1	ulpi_tx_data[3]	cmos	fast	pullup	inout	12
MIO 72	USB 1	ulpi_tx_data[4]	cmos	fast	pullup	inout	12
MIO 73	USB 1	ulpi_tx_data[5]	cmos	fast	pullup	inout	12
MIO 74	USB 1	ulpi_tx_data[6]	cmos	fast	pullup	inout	12
MIO 75	USB 1	ulpi_tx_data[7]	cmos	fast	pullup	inout	12
MIO 76	MDIO 2	gem2_mdc	cmos	fast	pullup	out	12
MIO 77	MDIO 2	gem2_mdio_out	cmos	fast	pullup	inout	12

PS Clocks information

PSS REF CLK : 33.333

Name	Source	Input Frequency (MHz)
APLL	PSS_REF_CLK	2400.000
DPLL	PSS_REF_CLK	2400.000
VPLL	PSS_REF_CLK	2100.000
RPLL	PSS_REF_CLK	2600.000
IOPLL	PSS_REF_CLK	3000.000

Peripheral	Requested Frequency (MHz)	Source	Actual Frequency (MHz)
GEM2 freq (MHz)	125	IOPLL	125.000000
USB1 freq (MHz)	250	IOPLL	250.000000
QSPI freq (MHz)	300	IOPLL	300.000000
SDIO1 freq (MHz)	200	RPLL	185.714279
UART0 freq (MHz)	100	IOPLL	100.000000
I2C1 freq (MHz)	100	IOPLL	100.000000
SPI0 freq (MHz)	200	RPLL	185.714279
CPU_R5 freq (MHz)	500	IOPLL	500.000000
IOU_SWITCH freq (MHz)	267	RPLL	260.000000
LPD_SWITCH freq (MHz)	500	IOPLL	500.000000
LPD_LSBUS freq (MHz)	100	IOPLL	100.000000
GEM_TSU freq (MHz)	250	IOPLL	250.000000
TIMESTAMP freq (MHz)	100	PSS_REF_CLK	33.333332
PSU__CRL_APB__USB3_REF_CTRL__freqmhz	20	IOPLL	20.000000
PCAP freq (MHz)	200	IOPLL	187.500000
DBG_LPD freq (MHz)	250	IOPLL	250.000000
ADMA freq (MHz)	500	IOPLL	500.000000
PL0 freq (MHz)	200	DPLL	200.000000
PL1 freq (MHz)	325	RPLL	325.000000
AMS freq (MHz)	50	IOPLL	50.000000
ACPU freq (MHz)	1200	APLL	1200.000000
DBG FPD freq (MHz)	250	IOPLL	250.000000
DDR_CTRL freq MHz)	266.500	DPLL	240.000000
GDMA freq (MHz)	600	DPLL	600.000000
DPDMA freq (MHz)	600	DPLL	600.000000
TOPSW_MAIN freq (MHz)	533.333	VPLL	525.000000
TOPSW_LSBUS freq (MHz)	100	IOPLL	100.000000
DBG TSTMP freq (MHz)	250	IOPLL	250.000000

DDR Memory information

Parameter name	Value	Description
ENABLE	1	Enable the PS DDR Controller
DDR Interface freq (MHz)	533	--
MEMORY TYPE	LPDDR 4	Type of memory interface
DM DBI	Components
BUS WIDTH	32 Bit	Data width of DDR interface, not including ECC data width
ECC	Disabled	Enables error correction code support
SPEED BIN	LPDDR4_1066	Speed Bin
CL	NA	Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL	NA	CAS write latency setting in memory clock cycles
DDR AL	0	Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD	10	tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP	12	Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC	63	Row cycle time (ns)
T RAS MIN	42	Minimum number of memory clock cycles required between an Active and Precharge command
T FAW	40.0	Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH	32 Bits	Width of individual DRAM components
DEVICE CAPACITY	8192 MBits	Storage capacity of individual DRAM components
BG ADDR COUNT	NA	Number of bank group address pins
RANK ADDR COUNT	0	Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT	3	Number of bank address pins
ROW ADDR COUNT	15	Number of row address pins
COL ADDR COUNT	10	Number of column address bits
C_DDR_RAM_HIGHADDR	0x3FFFFFFF	--

GT lanes information

Protocol

GT lane#

Ref Clk Sel

Ref freq (MHz)