<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Jan  9 11:19:27 2026" VIVADOVERSION="2024.2">

  <SYSTEMINFO ARCH="zynquplus" DEVICE="xczu1cg" NAME="design_1" PACKAGE="sbva484" SPEEDGRADE="-1"/>

  <EXTERNALPORTS>
    <PORT DIR="O" NAME="adc_cs" SIGIS="undef" SIGNAME="Iffo120g_core_0_adc_cs">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="adc_cs"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" LEFT="7" NAME="adc_d_in_n" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_adc_d_in_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="adc_d_in_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" LEFT="7" NAME="adc_d_in_p" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_adc_d_in_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="adc_d_in_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="adc_dco_in_n" SIGIS="undef" SIGNAME="External_Ports_adc_dco_in_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="adc_dco_in_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="adc_dco_in_p" SIGIS="undef" SIGNAME="External_Ports_adc_dco_in_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="adc_dco_in_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="adc_fco_in_n" SIGIS="undef" SIGNAME="External_Ports_adc_fco_in_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="adc_fco_in_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="adc_fco_in_p" SIGIS="undef" SIGNAME="External_Ports_adc_fco_in_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="adc_fco_in_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="adc_pdwn" SIGIS="undef" SIGNAME="Iffo120g_core_0_adc_pdwn">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="adc_pdwn"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="adc_sync_div" SIGIS="undef" SIGNAME="Iffo120g_core_0_adc_sync_div">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="adc_sync_div"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="5" NAME="baseProbe" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_probe">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Base_core_0" PORT="probe"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="baseRgb0_b" SIGIS="undef" SIGNAME="Base_core_0_rgb0_b">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Base_core_0" PORT="rgb0_b"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="baseRgb0_g" SIGIS="undef" SIGNAME="Base_core_0_rgb0_g">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Base_core_0" PORT="rgb0_g"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="baseRgb0_r" SIGIS="undef" SIGNAME="Base_core_0_rgb0_r">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Base_core_0" PORT="rgb0_r"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="i2c0_scl" SIGIS="undef" SIGNAME="External_Ports_i2c0_scl">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="scl"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="i2c0_sda" SIGIS="undef" SIGNAME="External_Ports_i2c0_sda">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="sda"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="3" NAME="iffo120gProbe" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_probe">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="probe"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="iffo120gRgb0_b" SIGIS="undef" SIGNAME="Iffo120g_core_0_rgb0_b">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="rgb0_b"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="iffo120gRgb0_g" SIGIS="undef" SIGNAME="Iffo120g_core_0_rgb0_g">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="rgb0_g"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="iffo120gRgb0_r" SIGIS="undef" SIGNAME="Iffo120g_core_0_rgb0_r">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="rgb0_r"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="pll_ce" SIGIS="undef" SIGNAME="Iffo120g_core_0_pll_ce">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="pll_ce"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="pll_le" SIGIS="undef" SIGNAME="Iffo120g_core_0_pll_le">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="pll_le"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="pll_muxout" SIGIS="undef" SIGNAME="External_Ports_pll_muxout">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="pll_muxout"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="pll_tx_data" SIGIS="undef" SIGNAME="Iffo120g_core_0_pll_tx_data">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="pll_tx_data"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="refclk" SIGIS="clk" SIGNAME="External_Ports_refclk">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="refclk_prt"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="rfe_cs" SIGIS="undef" SIGNAME="Iffo120g_core_0_rfe_cs">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="rfe_cs"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="rfe_reset" POLARITY="ACTIVE_LOW" SIGIS="undef" SIGNAME="Iffo120g_core_0_rfe_reset">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="rfe_reset"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="rfe_tx1_en" SIGIS="undef" SIGNAME="Iffo120g_core_0_rfe_tx1_en">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="rfe_tx1_en"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="rfe_tx2_en" SIGIS="undef" SIGNAME="Iffo120g_core_0_rfe_tx2_en">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="rfe_tx2_en"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="rfe_tx3_en" SIGIS="undef" SIGNAME="Iffo120g_core_0_rfe_tx3_en">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="rfe_tx3_en"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="spi_miso" SIGIS="undef" SIGNAME="External_Ports_spi_miso">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="miso"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="spi_mosi" SIGIS="undef" SIGNAME="Iffo120g_core_0_mosi">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="mosi"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="spi_sclk" SIGIS="undef" SIGNAME="Iffo120g_core_0_sclk">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="sclk"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="tr_en" SIGIS="undef" SIGNAME="Iffo120g_core_0_tr_en">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="tr_en"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="wp_eeprom_rf" SIGIS="undef" SIGNAME="Iffo120g_core_0_wp_eeprom_rf">
      <CONNECTIONS>
        <CONNECTION INSTANCE="Iffo120g_core_0" PORT="wp_eeprom_rf"/>
      </CONNECTIONS>
    </PORT>
  </EXTERNALPORTS>

  <EXTERNALINTERFACES/>

  <MODULES>
    <MODULE COREREVISION="65" FULLNAME="/Base_core_0" HWVERSION="1.0" INSTANCE="Base_core_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="Base_core" VLNV="indiesemi.com:user:Base_core:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="apuAXIL" NAME="reg0" RANGE="0x10000000000" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="fAclk" VALUE="100000"/>
        <PARAMETER NAME="fAdcclk" VALUE="250000"/>
        <PARAMETER NAME="fDspclk" VALUE="250000"/>
        <PARAMETER NAME="fMclk" VALUE="100000"/>
        <PARAMETER NAME="fMemclk" VALUE="300000"/>
        <PARAMETER NAME="fXdspclk" VALUE="400000"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_Base_core_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0x2000000000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0x20000003FF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="adcclk" SIGIS="clk" SIGNAME="Iffo120g_core_0_adcclk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="adcclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="39" NAME="apuAXIL_araddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="apuAXIL_arprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="apuAXIL_arready" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="apuAXIL_arvalid" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="39" NAME="apuAXIL_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="apuAXIL_awprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="apuAXIL_awready" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="apuAXIL_awvalid" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="apuAXIL_bready" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="apuAXIL_bresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="apuAXIL_bvalid" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="apuAXIL_rdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="apuAXIL_rready" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="apuAXIL_rresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="apuAXIL_rvalid" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="apuAXIL_wdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="apuAXIL_wready" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="apuAXIL_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="apuAXIL_wvalid" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_ps8_0_100M_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ps8_0_100M" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="cubeAXIS_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="cubeAXIS_tlast" SIGIS="undef"/>
        <PORT DIR="I" NAME="cubeAXIS_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="cubeAXIS_tuser" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="cubeAXIS_tvalid" SIGIS="undef"/>
        <PORT CLKFREQUENCY="250000000" DIR="I" NAME="dspclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk2">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk2"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="lanefault" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_lanefault">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="lanefault"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="lddrAXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="lddrAXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="lddrAXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="lddrAXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="lddrAXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="lddrAXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="lddrAXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="lddrAXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="lddrAXI_arready" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="lddrAXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="lddrAXI_arvalid" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="lddrAXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="lddrAXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="lddrAXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="lddrAXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="lddrAXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="lddrAXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="lddrAXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="lddrAXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="lddrAXI_awready" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="lddrAXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="lddrAXI_awvalid" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="lddrAXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="lddrAXI_bready" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="lddrAXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="lddrAXI_bvalid" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="lddrAXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="lddrAXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="lddrAXI_rlast" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="lddrAXI_rready" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="lddrAXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="lddrAXI_rvalid" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="lddrAXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="lddrAXI_wlast" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="lddrAXI_wready" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="lddrAXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="lddrAXI_wvalid" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp2_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="300000000" DIR="I" NAME="memclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk3"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="mmic0Ch0AXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch0AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch0iAXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic0Ch0AXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch0AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch0iAXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic0Ch0AXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch0AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch0iAXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="mmic0Ch1AXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch1AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch0qAXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic0Ch1AXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch1AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch0qAXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic0Ch1AXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch1AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch0qAXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="mmic0Ch2AXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch2AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch1iAXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic0Ch2AXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch2AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch1iAXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic0Ch2AXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch2AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch1iAXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="mmic0Ch3AXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch3AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch1qAXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic0Ch3AXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch3AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch1qAXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic0Ch3AXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch3AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch1qAXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="mmic1Ch0AXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch0AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch2iAXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic1Ch0AXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch0AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch2iAXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic1Ch0AXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch0AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch2iAXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="mmic1Ch1AXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch1AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch2qAXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic1Ch1AXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch1AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch2qAXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic1Ch1AXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch1AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch2qAXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="mmic1Ch2AXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch2AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch3iAXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic1Ch2AXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch2AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch3iAXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic1Ch2AXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch2AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch3iAXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="mmic1Ch3AXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch3AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch3qAXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic1Ch3AXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch3AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch3qAXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="mmic1Ch3AXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch3AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="ch3qAXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="mmic2Ch0AXIS_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="mmic2Ch0AXIS_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic2Ch0AXIS_tlast" SIGIS="undef"/>
        <PORT DIR="O" NAME="mmic2Ch0AXIS_tready" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic2Ch0AXIS_tvalid" SIGIS="undef"/>
        <PORT DIR="I" LEFT="15" NAME="mmic2Ch1AXIS_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="mmic2Ch1AXIS_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic2Ch1AXIS_tlast" SIGIS="undef"/>
        <PORT DIR="O" NAME="mmic2Ch1AXIS_tready" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic2Ch1AXIS_tvalid" SIGIS="undef"/>
        <PORT DIR="I" LEFT="15" NAME="mmic2Ch2AXIS_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="mmic2Ch2AXIS_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic2Ch2AXIS_tlast" SIGIS="undef"/>
        <PORT DIR="O" NAME="mmic2Ch2AXIS_tready" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic2Ch2AXIS_tvalid" SIGIS="undef"/>
        <PORT DIR="I" LEFT="15" NAME="mmic2Ch3AXIS_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="mmic2Ch3AXIS_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic2Ch3AXIS_tlast" SIGIS="undef"/>
        <PORT DIR="O" NAME="mmic2Ch3AXIS_tready" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic2Ch3AXIS_tvalid" SIGIS="undef"/>
        <PORT DIR="I" LEFT="15" NAME="mmic3Ch0AXIS_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="mmic3Ch0AXIS_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic3Ch0AXIS_tlast" SIGIS="undef"/>
        <PORT DIR="O" NAME="mmic3Ch0AXIS_tready" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic3Ch0AXIS_tvalid" SIGIS="undef"/>
        <PORT DIR="I" LEFT="15" NAME="mmic3Ch1AXIS_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="mmic3Ch1AXIS_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic3Ch1AXIS_tlast" SIGIS="undef"/>
        <PORT DIR="O" NAME="mmic3Ch1AXIS_tready" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic3Ch1AXIS_tvalid" SIGIS="undef"/>
        <PORT DIR="I" LEFT="15" NAME="mmic3Ch2AXIS_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="mmic3Ch2AXIS_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic3Ch2AXIS_tlast" SIGIS="undef"/>
        <PORT DIR="O" NAME="mmic3Ch2AXIS_tready" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic3Ch2AXIS_tvalid" SIGIS="undef"/>
        <PORT DIR="I" LEFT="15" NAME="mmic3Ch3AXIS_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="mmic3Ch3AXIS_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic3Ch3AXIS_tlast" SIGIS="undef"/>
        <PORT DIR="O" NAME="mmic3Ch3AXIS_tready" SIGIS="undef"/>
        <PORT DIR="I" NAME="mmic3Ch3AXIS_tvalid" SIGIS="undef"/>
        <PORT DIR="O" LEFT="5" NAME="probe" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_probe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="baseProbe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="rgb0_b" SIGIS="undef" SIGNAME="Base_core_0_rgb0_b">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="baseRgb0_b"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="rgb0_g" SIGIS="undef" SIGNAME="Base_core_0_rgb0_g">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="baseRgb0_g"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="rgb0_r" SIGIS="undef" SIGNAME="Base_core_0_rgb0_r">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="baseRgb0_r"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="sddrAXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="sddrAXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="sddrAXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="sddrAXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="sddrAXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="sddrAXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="sddrAXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="sddrAXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="sddrAXI_arready" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="sddrAXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="sddrAXI_arvalid" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="sddrAXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="sddrAXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="sddrAXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="sddrAXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="sddrAXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="sddrAXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="sddrAXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="sddrAXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="sddrAXI_awready" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="sddrAXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="sddrAXI_awvalid" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="sddrAXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="sddrAXI_bready" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="sddrAXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="sddrAXI_bvalid" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="sddrAXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="sddrAXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="sddrAXI_rlast" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="sddrAXI_rready" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="sddrAXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="sddrAXI_rvalid" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="sddrAXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="sddrAXI_wlast" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="sddrAXI_wready" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="sddrAXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="sddrAXI_wvalid" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp3_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="strbFrame" SIGIS="undef" SIGNAME="Iffo120g_core_0_strbFrame">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="strbFrame"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="strbLanefaultClear" SIGIS="undef" SIGNAME="Base_core_0_strbLanefaultClear">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="strbLanefaultClear"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="xddrAXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="xddrAXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="xddrAXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="xddrAXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="xddrAXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="xddrAXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="xddrAXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="xddrAXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="xddrAXI_arready" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="xddrAXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="xddrAXI_arvalid" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="xddrAXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="xddrAXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="xddrAXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="xddrAXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="xddrAXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="xddrAXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="xddrAXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="xddrAXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="xddrAXI_awready" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="xddrAXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="xddrAXI_awvalid" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="xddrAXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="xddrAXI_bready" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="xddrAXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="xddrAXI_bvalid" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="xddrAXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="xddrAXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="xddrAXI_rlast" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="xddrAXI_rready" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="xddrAXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="xddrAXI_rvalid" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="xddrAXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="xddrAXI_wlast" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="xddrAXI_wready" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="xddrAXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="xddrAXI_wvalid" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp1_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="400000000" DIR="I" NAME="xdspclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk1"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="cubeAXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_zynq_ultra_ps_e_0_0_pl_clk2"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="250000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="32"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="cubeAXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="cubeAXIS_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="cubeAXIS_tready"/>
            <PORTMAP LOGICAL="TUSER" PHYSICAL="cubeAXIS_tuser"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="cubeAXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch0iAXIS" NAME="mmic0Ch0AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic0Ch0AXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic0Ch0AXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic0Ch0AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch0qAXIS" NAME="mmic0Ch1AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic0Ch1AXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic0Ch1AXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic0Ch1AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch1iAXIS" NAME="mmic0Ch2AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic0Ch2AXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic0Ch2AXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic0Ch2AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch1qAXIS" NAME="mmic0Ch3AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic0Ch3AXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic0Ch3AXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic0Ch3AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch2iAXIS" NAME="mmic1Ch0AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic1Ch0AXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic1Ch0AXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic1Ch0AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch2qAXIS" NAME="mmic1Ch1AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic1Ch1AXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic1Ch1AXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic1Ch1AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch3iAXIS" NAME="mmic1Ch2AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic1Ch2AXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic1Ch2AXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic1Ch2AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch3qAXIS" NAME="mmic1Ch3AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic1Ch3AXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic1Ch3AXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic1Ch3AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="mmic2Ch0AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic2Ch0AXIS_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="mmic2Ch0AXIS_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic2Ch0AXIS_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="mmic2Ch0AXIS_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic2Ch0AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="mmic2Ch1AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic2Ch1AXIS_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="mmic2Ch1AXIS_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic2Ch1AXIS_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="mmic2Ch1AXIS_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic2Ch1AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="mmic2Ch2AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic2Ch2AXIS_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="mmic2Ch2AXIS_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic2Ch2AXIS_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="mmic2Ch2AXIS_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic2Ch2AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="mmic2Ch3AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic2Ch3AXIS_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="mmic2Ch3AXIS_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic2Ch3AXIS_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="mmic2Ch3AXIS_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic2Ch3AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="mmic3Ch0AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic3Ch0AXIS_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="mmic3Ch0AXIS_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic3Ch0AXIS_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="mmic3Ch0AXIS_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic3Ch0AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="mmic3Ch1AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic3Ch1AXIS_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="mmic3Ch1AXIS_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic3Ch1AXIS_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="mmic3Ch1AXIS_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic3Ch1AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="mmic3Ch2AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic3Ch2AXIS_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="mmic3Ch2AXIS_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic3Ch2AXIS_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="mmic3Ch2AXIS_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic3Ch2AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="mmic3Ch3AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="mmic3Ch3AXIS_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="mmic3Ch3AXIS_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="mmic3Ch3AXIS_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="mmic3Ch3AXIS_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="mmic3Ch3AXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M00_AXI" DATAWIDTH="64" NAME="apuAXIL" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="ADDR_WIDTH" VALUE="40"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="apuAXIL_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="apuAXIL_arprot"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="apuAXIL_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="apuAXIL_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="apuAXIL_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="apuAXIL_awprot"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="apuAXIL_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="apuAXIL_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="apuAXIL_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="apuAXIL_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="apuAXIL_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="apuAXIL_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="apuAXIL_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="apuAXIL_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="apuAXIL_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="apuAXIL_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="apuAXIL_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="apuAXIL_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="apuAXIL_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Base_core_0_lddrAXI" DATAWIDTH="128" NAME="lddrAXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="ADDR_WIDTH" VALUE="40"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_zynq_ultra_ps_e_0_0_pl_clk3"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="300000000"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="6"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="lddrAXI_araddr"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="lddrAXI_arburst"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="lddrAXI_arcache"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="lddrAXI_arid"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="lddrAXI_arlen"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="lddrAXI_arlock"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="lddrAXI_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="lddrAXI_arqos"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="lddrAXI_arready"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="lddrAXI_arsize"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="lddrAXI_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="lddrAXI_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="lddrAXI_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="lddrAXI_awcache"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="lddrAXI_awid"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="lddrAXI_awlen"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="lddrAXI_awlock"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="lddrAXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="lddrAXI_awqos"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="lddrAXI_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="lddrAXI_awsize"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="lddrAXI_awvalid"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="lddrAXI_bid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="lddrAXI_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="lddrAXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="lddrAXI_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="lddrAXI_rdata"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="lddrAXI_rid"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="lddrAXI_rlast"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="lddrAXI_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="lddrAXI_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="lddrAXI_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="lddrAXI_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="lddrAXI_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="lddrAXI_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="lddrAXI_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="lddrAXI_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Base_core_0_sddrAXI" DATAWIDTH="128" NAME="sddrAXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="ADDR_WIDTH" VALUE="40"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_zynq_ultra_ps_e_0_0_pl_clk3"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="300000000"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="6"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="sddrAXI_araddr"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="sddrAXI_arburst"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="sddrAXI_arcache"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="sddrAXI_arid"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="sddrAXI_arlen"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="sddrAXI_arlock"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="sddrAXI_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="sddrAXI_arqos"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="sddrAXI_arready"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="sddrAXI_arsize"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="sddrAXI_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="sddrAXI_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="sddrAXI_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="sddrAXI_awcache"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="sddrAXI_awid"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="sddrAXI_awlen"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="sddrAXI_awlock"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="sddrAXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="sddrAXI_awqos"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="sddrAXI_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="sddrAXI_awsize"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="sddrAXI_awvalid"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="sddrAXI_bid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="sddrAXI_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="sddrAXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="sddrAXI_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="sddrAXI_rdata"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="sddrAXI_rid"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="sddrAXI_rlast"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="sddrAXI_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="sddrAXI_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="sddrAXI_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="sddrAXI_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="sddrAXI_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="sddrAXI_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="sddrAXI_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="sddrAXI_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Base_core_0_xddrAXI" DATAWIDTH="128" NAME="xddrAXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="ADDR_WIDTH" VALUE="40"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_zynq_ultra_ps_e_0_0_pl_clk3"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="300000000"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="6"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="xddrAXI_araddr"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="xddrAXI_arburst"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="xddrAXI_arcache"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="xddrAXI_arid"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="xddrAXI_arlen"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="xddrAXI_arlock"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="xddrAXI_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="xddrAXI_arqos"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="xddrAXI_arready"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="xddrAXI_arsize"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="xddrAXI_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="xddrAXI_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="xddrAXI_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="xddrAXI_awcache"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="xddrAXI_awid"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="xddrAXI_awlen"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="xddrAXI_awlock"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="xddrAXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="xddrAXI_awqos"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="xddrAXI_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="xddrAXI_awsize"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="xddrAXI_awvalid"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="xddrAXI_bid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="xddrAXI_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="xddrAXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="xddrAXI_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="xddrAXI_rdata"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="xddrAXI_rid"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="xddrAXI_rlast"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="xddrAXI_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="xddrAXI_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="xddrAXI_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="xddrAXI_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="xddrAXI_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="xddrAXI_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="xddrAXI_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="xddrAXI_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE ADDRESSBLOCK="HP0_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="lddrAXI" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0_FPD"/>
        <MEMRANGE ADDRESSBLOCK="HP1_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="sddrAXI" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP1_FPD"/>
        <MEMRANGE ADDRESSBLOCK="HPC1_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="xddrAXI" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC1_FPD"/>
      </MEMORYMAP>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="zynq_ultra_ps_e_0"/>
      </PERIPHERALS>
    </MODULE>
    <MODULE COREREVISION="7" FULLNAME="/Iffo120g_core_0" HWVERSION="1.0" INSTANCE="Iffo120g_core_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="Iffo120g_core" VLNV="user.org:user:Iffo120g_core:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="fAclk" VALUE="100000"/>
        <PARAMETER NAME="fAdcclk" VALUE="240000"/>
        <PARAMETER NAME="fDlyclk" VALUE="300000"/>
        <PARAMETER NAME="fMclk" VALUE="100000"/>
        <PARAMETER NAME="fRefclk" VALUE="80000"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_Iffo120g_core_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="adc_cs" SIGIS="undef" SIGNAME="Iffo120g_core_0_adc_cs">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_cs"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="adc_d_in_n" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_adc_d_in_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_d_in_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="adc_d_in_p" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_adc_d_in_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_d_in_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="adc_dco_in_n" SIGIS="undef" SIGNAME="External_Ports_adc_dco_in_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_dco_in_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="adc_dco_in_p" SIGIS="undef" SIGNAME="External_Ports_adc_dco_in_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_dco_in_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="adc_fco_in_n" SIGIS="undef" SIGNAME="External_Ports_adc_fco_in_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_fco_in_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="adc_fco_in_p" SIGIS="undef" SIGNAME="External_Ports_adc_fco_in_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_fco_in_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="adc_pdwn" SIGIS="undef" SIGNAME="Iffo120g_core_0_adc_pdwn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_pdwn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="adc_sync_div" SIGIS="undef" SIGNAME="Iffo120g_core_0_adc_sync_div">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_sync_div"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="O" NAME="adcclk" SIGIS="clk" SIGNAME="Iffo120g_core_0_adcclk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="adcclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="39" NAME="apuAXIL_araddr" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="apuAXIL_arprot" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="apuAXIL_arready" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="apuAXIL_arvalid" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="39" NAME="apuAXIL_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="apuAXIL_awprot" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="apuAXIL_awready" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="apuAXIL_awvalid" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="apuAXIL_bready" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="apuAXIL_bresp" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="apuAXIL_bvalid" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="apuAXIL_rdata" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="apuAXIL_rready" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="apuAXIL_rresp" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="apuAXIL_rvalid" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="apuAXIL_wdata" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="apuAXIL_wready" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="apuAXIL_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="apuAXIL_wvalid" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_ps8_0_100M_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ps8_0_100M" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="ch0iAXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch0AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic0Ch0AXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch0iAXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch0AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic0Ch0AXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch0iAXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch0AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic0Ch0AXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="ch0qAXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch1AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic0Ch1AXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch0qAXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch1AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic0Ch1AXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch0qAXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch1AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic0Ch1AXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="ch1iAXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch2AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic0Ch2AXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch1iAXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch2AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic0Ch2AXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch1iAXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch2AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic0Ch2AXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="ch1qAXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch3AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic0Ch3AXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch1qAXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch3AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic0Ch3AXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch1qAXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic0Ch3AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic0Ch3AXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="ch2iAXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch0AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic1Ch0AXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch2iAXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch0AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic1Ch0AXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch2iAXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch0AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic1Ch0AXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="ch2qAXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch1AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic1Ch1AXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch2qAXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch1AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic1Ch1AXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch2qAXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch1AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic1Ch1AXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="ch3iAXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch2AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic1Ch2AXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch3iAXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch2AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic1Ch2AXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch3iAXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch2AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic1Ch2AXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="ch3qAXIS_tdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch3AXIS_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic1Ch3AXIS_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch3qAXIS_tlast" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch3AXIS_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic1Ch3AXIS_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ch3qAXIS_tvalid" SIGIS="undef" SIGNAME="Base_core_0_mmic1Ch3AXIS_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="mmic1Ch3AXIS_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="300000000" DIR="I" NAME="dlyclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk3"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="lanefault" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_lanefault">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lanefault"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="miso" SIGIS="undef" SIGNAME="External_Ports_spi_miso">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="spi_miso"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="mosi" SIGIS="undef" SIGNAME="Iffo120g_core_0_mosi">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="spi_mosi"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="pll_ce" SIGIS="undef" SIGNAME="Iffo120g_core_0_pll_ce">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="pll_ce"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="pll_le" SIGIS="undef" SIGNAME="Iffo120g_core_0_pll_le">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="pll_le"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="pll_muxout" SIGIS="undef" SIGNAME="External_Ports_pll_muxout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="pll_muxout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="pll_tx_data" SIGIS="undef" SIGNAME="Iffo120g_core_0_pll_tx_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="pll_tx_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="probe" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_probe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="iffo120gProbe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="psI2c0Scl_in" SIGIS="undef" SIGNAME="Iffo120g_core_0_psI2c0Scl_in">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="emio_i2c0_scl_i"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="psI2c0Scl_out" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_i2c0_scl_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="emio_i2c0_scl_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="psI2c0Scl_tri" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_i2c0_scl_t">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="emio_i2c0_scl_t"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="psI2c0Sda_in" SIGIS="undef" SIGNAME="Iffo120g_core_0_psI2c0Sda_in">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="emio_i2c0_sda_i"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="psI2c0Sda_out" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_i2c0_sda_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="emio_i2c0_sda_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="psI2c0Sda_tri" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_i2c0_sda_t">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="emio_i2c0_sda_t"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="psSpi0Miso" SIGIS="undef" SIGNAME="Iffo120g_core_0_psSpi0Miso">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="emio_spi0_m_i"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="psSpi0Mosi" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_spi0_m_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="emio_spi0_m_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="psSpi0Sclk" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_spi0_sclk_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="emio_spi0_sclk_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="psSpi0Ss0" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_spi0_ss_o_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="emio_spi0_ss_o_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="psSpi0Ss1" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_spi0_ss1_o_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="emio_spi0_ss1_o_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="psSpi0Ss2" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_spi0_ss2_o_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="emio_spi0_ss2_o_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="refclk_prt" SIGIS="clk" SIGNAME="External_Ports_refclk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="refclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="rfe_cs" SIGIS="undef" SIGNAME="Iffo120g_core_0_rfe_cs">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="rfe_cs"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="rfe_reset" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="Iffo120g_core_0_rfe_reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="rfe_reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="rfe_tx1_en" SIGIS="undef" SIGNAME="Iffo120g_core_0_rfe_tx1_en">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="rfe_tx1_en"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="rfe_tx2_en" SIGIS="undef" SIGNAME="Iffo120g_core_0_rfe_tx2_en">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="rfe_tx2_en"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="rfe_tx3_en" SIGIS="undef" SIGNAME="Iffo120g_core_0_rfe_tx3_en">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="rfe_tx3_en"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="rgb0_b" SIGIS="undef" SIGNAME="Iffo120g_core_0_rgb0_b">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="iffo120gRgb0_b"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="rgb0_g" SIGIS="undef" SIGNAME="Iffo120g_core_0_rgb0_g">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="iffo120gRgb0_g"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="rgb0_r" SIGIS="undef" SIGNAME="Iffo120g_core_0_rgb0_r">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="iffo120gRgb0_r"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="scl" SIGIS="undef" SIGNAME="External_Ports_i2c0_scl">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="i2c0_scl"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="sclk" SIGIS="undef" SIGNAME="Iffo120g_core_0_sclk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="spi_sclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="sda" SIGIS="undef" SIGNAME="External_Ports_i2c0_sda">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="i2c0_sda"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="strbFrame" SIGIS="undef" SIGNAME="Iffo120g_core_0_strbFrame">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="strbFrame"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="strbLanefaultClear" SIGIS="undef" SIGNAME="Base_core_0_strbLanefaultClear">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="strbLanefaultClear"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="tr_en" SIGIS="undef" SIGNAME="Iffo120g_core_0_tr_en">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="tr_en"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="wp_eeprom_rf" SIGIS="undef" SIGNAME="Iffo120g_core_0_wp_eeprom_rf">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="wp_eeprom_rf"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch0iAXIS" NAME="ch0iAXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="ch0iAXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="ch0iAXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="ch0iAXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch0qAXIS" NAME="ch0qAXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="ch0qAXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="ch0qAXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="ch0qAXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch1iAXIS" NAME="ch1iAXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="ch1iAXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="ch1iAXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="ch1iAXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch1qAXIS" NAME="ch1qAXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="ch1qAXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="ch1qAXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="ch1qAXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch2iAXIS" NAME="ch2iAXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="ch2iAXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="ch2iAXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="ch2iAXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch2qAXIS" NAME="ch2qAXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="ch2qAXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="ch2qAXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="ch2qAXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch3iAXIS" NAME="ch3iAXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="ch3iAXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="ch3iAXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="ch3iAXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Iffo120g_core_0_ch3qAXIS" NAME="ch3qAXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_Iffo120g_core_0_0_adcclk"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="ch3qAXIS_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="ch3qAXIS_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="ch3qAXIS_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M01_AXI" DATAWIDTH="64" NAME="apuAXIL" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="ADDR_WIDTH" VALUE="40"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="apuAXIL_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="apuAXIL_arprot"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="apuAXIL_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="apuAXIL_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="apuAXIL_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="apuAXIL_awprot"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="apuAXIL_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="apuAXIL_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="apuAXIL_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="apuAXIL_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="apuAXIL_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="apuAXIL_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="apuAXIL_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="apuAXIL_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="apuAXIL_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="apuAXIL_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="apuAXIL_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="apuAXIL_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="apuAXIL_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="34" FULLNAME="/ps8_0_axi_periph" HWVERSION="2.1" INSTANCE="ps8_0_axi_periph" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="Component_Name" VALUE="design_1_ps8_0_axi_periph_0"/>
        <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
        <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
        <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M00_SECURE" VALUE="0"/>
        <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M01_SECURE" VALUE="0"/>
        <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M02_SECURE" VALUE="0"/>
        <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M03_SECURE" VALUE="0"/>
        <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M04_SECURE" VALUE="0"/>
        <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M05_SECURE" VALUE="0"/>
        <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M06_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M06_SECURE" VALUE="0"/>
        <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M07_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M07_SECURE" VALUE="0"/>
        <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M08_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M08_SECURE" VALUE="0"/>
        <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M09_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M09_SECURE" VALUE="0"/>
        <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M10_SECURE" VALUE="0"/>
        <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M11_SECURE" VALUE="0"/>
        <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M12_SECURE" VALUE="0"/>
        <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M13_SECURE" VALUE="0"/>
        <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M14_SECURE" VALUE="0"/>
        <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M15_SECURE" VALUE="0"/>
        <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M16_SECURE" VALUE="0"/>
        <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M17_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M17_SECURE" VALUE="0"/>
        <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M18_SECURE" VALUE="0"/>
        <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M19_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M19_SECURE" VALUE="0"/>
        <PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M20_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M20_SECURE" VALUE="0"/>
        <PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M21_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M21_SECURE" VALUE="0"/>
        <PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M22_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M22_SECURE" VALUE="0"/>
        <PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M23_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M23_SECURE" VALUE="0"/>
        <PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M24_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M24_SECURE" VALUE="0"/>
        <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M25_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M25_SECURE" VALUE="0"/>
        <PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M26_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M26_SECURE" VALUE="0"/>
        <PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M27_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M27_SECURE" VALUE="0"/>
        <PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M28_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M28_SECURE" VALUE="0"/>
        <PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M29_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M29_SECURE" VALUE="0"/>
        <PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M30_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M30_SECURE" VALUE="0"/>
        <PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M31_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M31_SECURE" VALUE="0"/>
        <PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M32_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M32_SECURE" VALUE="0"/>
        <PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M33_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M33_SECURE" VALUE="0"/>
        <PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M34_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M34_SECURE" VALUE="0"/>
        <PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M35_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M35_SECURE" VALUE="0"/>
        <PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M36_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M36_SECURE" VALUE="0"/>
        <PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M37_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M37_SECURE" VALUE="0"/>
        <PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M38_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M38_SECURE" VALUE="0"/>
        <PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M39_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M39_SECURE" VALUE="0"/>
        <PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M40_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M40_SECURE" VALUE="0"/>
        <PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M41_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M41_SECURE" VALUE="0"/>
        <PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M42_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M42_SECURE" VALUE="0"/>
        <PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M43_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M43_SECURE" VALUE="0"/>
        <PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M44_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M44_SECURE" VALUE="0"/>
        <PARAMETER NAME="M45_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M45_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M45_SECURE" VALUE="0"/>
        <PARAMETER NAME="M46_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M46_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M46_SECURE" VALUE="0"/>
        <PARAMETER NAME="M47_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M47_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M47_SECURE" VALUE="0"/>
        <PARAMETER NAME="M48_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M48_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M48_SECURE" VALUE="0"/>
        <PARAMETER NAME="M49_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M49_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M49_SECURE" VALUE="0"/>
        <PARAMETER NAME="M50_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M50_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M50_SECURE" VALUE="0"/>
        <PARAMETER NAME="M51_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M51_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M51_SECURE" VALUE="0"/>
        <PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M52_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M52_SECURE" VALUE="0"/>
        <PARAMETER NAME="M53_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M53_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M53_SECURE" VALUE="0"/>
        <PARAMETER NAME="M54_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M54_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M54_SECURE" VALUE="0"/>
        <PARAMETER NAME="M55_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M55_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M55_SECURE" VALUE="0"/>
        <PARAMETER NAME="M56_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M56_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M56_SECURE" VALUE="0"/>
        <PARAMETER NAME="M57_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M57_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M57_SECURE" VALUE="0"/>
        <PARAMETER NAME="M58_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M58_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M58_SECURE" VALUE="0"/>
        <PARAMETER NAME="M59_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M59_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M59_SECURE" VALUE="0"/>
        <PARAMETER NAME="M60_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M60_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M60_SECURE" VALUE="0"/>
        <PARAMETER NAME="M61_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M61_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M61_SECURE" VALUE="0"/>
        <PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M62_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M62_SECURE" VALUE="0"/>
        <PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M63_SECURE" VALUE="0"/>
        <PARAMETER NAME="NUM_MI" VALUE="2"/>
        <PARAMETER NAME="NUM_SI" VALUE="1"/>
        <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
        <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
        <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
        <PARAMETER NAME="S00_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S01_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S01_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S02_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S02_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S03_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S03_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S04_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S04_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S05_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S05_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S06_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S06_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S07_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S07_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S08_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S08_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S09_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S09_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S10_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S10_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S11_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S11_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S12_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S12_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S13_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S13_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S14_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S14_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S15_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S15_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="STRATEGY" VALUE="0"/>
        <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="3"/>
        <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="ARESETN" SIGIS="rst" SIGNAME="rst_ps8_0_100M_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ps8_0_100M" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_ARESETN" SIGIS="rst" SIGNAME="rst_ps8_0_100M_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ps8_0_100M" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_apuAXIL_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="apuAXIL_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_ARESETN" SIGIS="rst" SIGNAME="rst_ps8_0_100M_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ps8_0_100M" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="M01_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_AXI_arready" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_arvalid" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="M01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_AXI_awready" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_awvalid" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_bready" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_AXI_bvalid" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_rready" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_AXI_rvalid" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_AXI_wready" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_wvalid" SIGIS="undef" SIGNAME="Iffo120g_core_0_apuAXIL_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="apuAXIL_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="rst_ps8_0_100M_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ps8_0_100M" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="39" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="S00_AXI_aruser" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_aruser">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_aruser"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="39" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="S00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="S00_AXI_awuser" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awuser">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awuser"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="S00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="S00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_wvalid"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="zynq_ultra_ps_e_0_M_AXI_HPM0_FPD" DATAWIDTH="128" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="S00_AXI_arid"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
            <PORTMAP LOGICAL="ARUSER" PHYSICAL="S00_AXI_aruser"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="S00_AXI_awid"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
            <PORTMAP LOGICAL="AWUSER" PHYSICAL="S00_AXI_awuser"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="S00_AXI_bid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="S00_AXI_rid"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M00_AXI" DATAWIDTH="64" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M00_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M00_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M01_AXI" DATAWIDTH="64" NAME="M01_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M01_AXI_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M01_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M01_AXI_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M01_AXI_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M01_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M01_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M01_AXI_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M01_AXI_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M01_AXI_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M01_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M01_AXI_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M01_AXI_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M01_AXI_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M01_AXI_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M01_AXI_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M01_AXI_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M01_AXI_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M01_AXI_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M01_AXI_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="16" FULLNAME="/rst_ps8_0_100M" HWVERSION="5.0" INSTANCE="rst_ps8_0_100M" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_rst_ps8_0_100M_0"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="aux_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef"/>
        <PORT DIR="I" NAME="ext_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="zynq_ultra_ps_e_0_pl_resetn0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_resetn0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="I" NAME="mb_debug_sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="O" NAME="mb_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="rst_ps8_0_100M_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_ARESETN"/>
            <CONNECTION INSTANCE="Base_core_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE CONFIGURABLE="TRUE" COREREVISION="5" FULLNAME="/zynq_ultra_ps_e_0" HWVERSION="3.5" INSTANCE="zynq_ultra_ps_e_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" IS_PL="FALSE" MODTYPE="zynq_ultra_ps_e" VLNV="xilinx.com:ip:zynq_ultra_ps_e:3.5">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=zynq_ultra_ps_e;v=v3_5;d=pg201-zynq-ultrascale-plus-processing-system.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="SAXIGP2" NAME="HP0_DDR_LOW" RANGE="0x80000000" USAGE="memory"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C_DP_USE_AUDIO" VALUE="0"/>
        <PARAMETER NAME="C_DP_USE_VIDEO" VALUE="0"/>
        <PARAMETER NAME="C_EMIO_GPIO_WIDTH" VALUE="95"/>
        <PARAMETER NAME="C_EN_EMIO_TRACE" VALUE="0"/>
        <PARAMETER NAME="C_EN_FIFO_ENET0" VALUE="0"/>
        <PARAMETER NAME="C_EN_FIFO_ENET1" VALUE="0"/>
        <PARAMETER NAME="C_EN_FIFO_ENET2" VALUE="0"/>
        <PARAMETER NAME="C_EN_FIFO_ENET3" VALUE="0"/>
        <PARAMETER NAME="C_MAXIGP0_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_MAXIGP1_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_MAXIGP2_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_NUM_F2P_0_INTR_INPUTS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_F2P_1_INTR_INPUTS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_FABRIC_RESETS" VALUE="1"/>
        <PARAMETER NAME="C_PL_CLK0_BUF" VALUE="TRUE"/>
        <PARAMETER NAME="C_PL_CLK1_BUF" VALUE="TRUE"/>
        <PARAMETER NAME="C_PL_CLK2_BUF" VALUE="TRUE"/>
        <PARAMETER NAME="C_PL_CLK3_BUF" VALUE="TRUE"/>
        <PARAMETER NAME="C_SAXIGP0_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_SAXIGP1_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_SAXIGP2_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_SAXIGP3_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_SAXIGP4_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_SAXIGP5_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_SAXIGP6_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_SD0_INTERNAL_BUS_WIDTH" VALUE="5"/>
        <PARAMETER NAME="C_SD1_INTERNAL_BUS_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_TRACE_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_TRACE_PIPELINE_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C_USE_DEBUG_TEST" VALUE="0"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP0" VALUE="0"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP1" VALUE="0"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP2" VALUE="0"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP3" VALUE="0"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP4" VALUE="0"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP5" VALUE="0"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP6" VALUE="0"/>
        <PARAMETER NAME="CAN0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="CAN1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="CSU_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_zynq_ultra_ps_e_0_0"/>
        <PARAMETER NAME="DP_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="GEM0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="GEM1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="GEM2_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="GEM3_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="GPIO_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="IIC0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="IIC1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="NAND_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="PCIE_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="PJTAG_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="PMU_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="PSU_BANK_0_IO_STANDARD" VALUE="LVCMOS33"/>
        <PARAMETER NAME="PSU_BANK_1_IO_STANDARD" VALUE="LVCMOS33"/>
        <PARAMETER NAME="PSU_BANK_2_IO_STANDARD" VALUE="LVCMOS33"/>
        <PARAMETER NAME="PSU_BANK_3_IO_STANDARD" VALUE="LVCMOS33"/>
        <PARAMETER NAME="PSU_DDR_RAM_HIGHADDR" VALUE="0x3FFFFFFF"/>
        <PARAMETER NAME="PSU_DDR_RAM_HIGHADDR_OFFSET" VALUE="0x00000002"/>
        <PARAMETER NAME="PSU_DDR_RAM_LOWADDR_OFFSET" VALUE="0x40000000"/>
        <PARAMETER NAME="PSU_DYNAMIC_DDR_CONFIG_EN" VALUE="0"/>
        <PARAMETER NAME="PSU_IMPORT_BOARD_PRESET"/>
        <PARAMETER NAME="PSU_MIO_0_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_0_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_0_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_0_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_0_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_0_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_10_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_10_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_10_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_10_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_10_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_10_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_11_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_11_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_11_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_11_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_11_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_11_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_12_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_12_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_12_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_12_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_12_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_12_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_13_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_13_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_13_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_13_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_13_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_13_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_14_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_14_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_14_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_14_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_14_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_14_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_15_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_15_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_15_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_15_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_15_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_15_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_16_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_16_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_16_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_16_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_16_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_16_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_17_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_17_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_17_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_17_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_17_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_17_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_18_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_18_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_18_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_18_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_18_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_18_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_19_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_19_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_19_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_19_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_19_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_19_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_1_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_1_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_1_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_1_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_1_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_1_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_20_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_20_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_20_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_20_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_20_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_20_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_21_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_21_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_21_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_21_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_21_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_21_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_22_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_22_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_22_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_22_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_22_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_22_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_23_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_23_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_23_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_23_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_23_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_23_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_24_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_24_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_24_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_24_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_24_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_24_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_25_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_25_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_25_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_25_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_25_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_25_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_26_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_26_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_26_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_26_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_26_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_26_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_27_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_27_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_27_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_27_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_27_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_27_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_28_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_28_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_28_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_28_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_28_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_28_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_29_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_29_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_29_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_29_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_29_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_29_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_2_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_2_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_2_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_2_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_2_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_2_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_30_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_30_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_30_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_30_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_30_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_30_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_31_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_31_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_31_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_31_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_31_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_31_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_32_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_32_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_32_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_32_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_32_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_32_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_33_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_33_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_33_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_33_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_33_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_33_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_34_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_34_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_34_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_34_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_34_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_34_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_35_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_35_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_35_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_35_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_35_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_35_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_36_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_36_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_36_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_36_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_36_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_36_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_37_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_37_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_37_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_37_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_37_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_37_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_38_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_38_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_38_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_38_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_38_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_38_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_39_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_39_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_39_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_39_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_39_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_39_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_3_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_3_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_3_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_3_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_3_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_3_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_40_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_40_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_40_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_40_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_40_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_40_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_41_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_41_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_41_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_41_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_41_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_41_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_42_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_42_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_42_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_42_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_42_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_42_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_43_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_43_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_43_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_43_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_43_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_43_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_44_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_44_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_44_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_44_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_44_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_44_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_45_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_45_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_45_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_45_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_45_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_45_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_46_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_46_DRIVE_STRENGTH" VALUE="4"/>
        <PARAMETER NAME="PSU_MIO_46_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_46_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_46_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_46_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_47_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_47_DRIVE_STRENGTH" VALUE="4"/>
        <PARAMETER NAME="PSU_MIO_47_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_47_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_47_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_47_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_48_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_48_DRIVE_STRENGTH" VALUE="4"/>
        <PARAMETER NAME="PSU_MIO_48_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_48_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_48_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_48_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_49_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_49_DRIVE_STRENGTH" VALUE="4"/>
        <PARAMETER NAME="PSU_MIO_49_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_49_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_49_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_49_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_4_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_4_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_4_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_4_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_4_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_4_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_50_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_50_DRIVE_STRENGTH" VALUE="4"/>
        <PARAMETER NAME="PSU_MIO_50_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_50_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_50_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_50_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_51_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_51_DRIVE_STRENGTH" VALUE="4"/>
        <PARAMETER NAME="PSU_MIO_51_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_51_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_51_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_51_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_52_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_52_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_52_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_52_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_52_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_52_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_53_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_53_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_53_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_53_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_53_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_53_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_54_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_54_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_54_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_54_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_54_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_54_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_55_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_55_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_55_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_55_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_55_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_55_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_56_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_56_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_56_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_56_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_56_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_56_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_57_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_57_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_57_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_57_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_57_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_57_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_58_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_58_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_58_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_58_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_58_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_58_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_59_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_59_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_59_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_59_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_59_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_59_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_5_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_5_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_5_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_5_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_5_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_5_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_60_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_60_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_60_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_60_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_60_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_60_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_61_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_61_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_61_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_61_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_61_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_61_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_62_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_62_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_62_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_62_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_62_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_62_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_63_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_63_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_63_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_63_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_63_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_63_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_64_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_64_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_64_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_64_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_64_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_64_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_65_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_65_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_65_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_65_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_65_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_65_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_66_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_66_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_66_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_66_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_66_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_66_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_67_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_67_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_67_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_67_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_67_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_67_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_68_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_68_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_68_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_68_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_68_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_68_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_69_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_69_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_69_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_69_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_69_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_69_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_6_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_6_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_6_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_6_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_6_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_6_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_70_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_70_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_70_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_70_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_70_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_70_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_71_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_71_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_71_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_71_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_71_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_71_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_72_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_72_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_72_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_72_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_72_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_72_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_73_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_73_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_73_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_73_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_73_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_73_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_74_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_74_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_74_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_74_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_74_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_74_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_75_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_75_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_75_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_75_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_75_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_75_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_76_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_76_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_76_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_76_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_76_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_76_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_77_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_77_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_77_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_77_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_77_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_77_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_7_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_7_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_7_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_7_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_7_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_7_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_8_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_8_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_8_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_8_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_8_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_8_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_9_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_9_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_9_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_9_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_9_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_9_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_TREE_PERIPHERALS" VALUE="Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#GPIO0 MIO#I2C 1#I2C 1#UART 0#UART 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#PMU GPI 0#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Gem 2#Gem 2#Gem 2#Gem 2#Gem 2#Gem 2#Gem 2#Gem 2#Gem 2#Gem 2#Gem 2#Gem 2#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#MDIO 2#MDIO 2"/>
        <PARAMETER NAME="PSU_MIO_TREE_SIGNALS" VALUE="sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#gpio0[7]#scl_out#sda_out#rxd#txd#gpio0[12]#gpio0[13]#gpio0[14]#gpio0[15]#gpio0[16]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpi[0]#gpio1[27]#gpio1[28]#gpio1[29]#gpio1[30]#gpio1[31]#gpio1[32]#gpio1[33]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gem2_mdc#gem2_mdio_out"/>
        <PARAMETER NAME="PSU_PERIPHERAL_BOARD_PRESET"/>
        <PARAMETER NAME="PSU_SD0_INTERNAL_BUS_WIDTH" VALUE="8"/>
        <PARAMETER NAME="PSU_SD1_INTERNAL_BUS_WIDTH" VALUE="4"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T0" VALUE="NA"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T1" VALUE="NA"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T2" VALUE="NA"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T3" VALUE="NA"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T4" VALUE="NA"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T5" VALUE="NA"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T6" VALUE="NA"/>
        <PARAMETER NAME="PSU_UIPARAM_GENERATE_SUMMARY" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU_USB3__DUAL_CLOCK_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU_VALUE_SILVERSION" VALUE="3"/>
        <PARAMETER NAME="PSU__ACPU0__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__ACPU1__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__ACPU2__POWER__ON" VALUE="0"/>
        <PARAMETER NAME="PSU__ACPU3__POWER__ON" VALUE="0"/>
        <PARAMETER NAME="PSU__ACTUAL__IP" VALUE="1"/>
        <PARAMETER NAME="PSU__ACT_DDR_FREQ_MHZ" VALUE="480.000000"/>
        <PARAMETER NAME="PSU__AFI0_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__AFI1_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__AUX_REF_CLK__FREQMHZ" VALUE="33.333"/>
        <PARAMETER NAME="PSU__CAN0_LOOP_CAN1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CAN0__GRP_CLK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CAN0__GRP_CLK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CAN0__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CAN0__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CAN1__GRP_CLK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CAN1__GRP_CLK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CAN1__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CAN1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ" VALUE="1200.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__FREQMHZ" VALUE="1200"/>
        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__SRCSEL" VALUE="APLL"/>
        <PARAMETER NAME="PSU__CRF_APB__ACPU__FRAC_ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__DIV2" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__FBDIV" VALUE="72"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__FRACDATA" VALUE="0.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__FRACFREQ" VALUE="27.138"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_FRAC_CFG__ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__APM_CTRL__DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__APM_CTRL__FREQMHZ" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__APM_CTRL__SRCSEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ" VALUE="250.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0" VALUE="5"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ" VALUE="250.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ" VALUE="240.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__DDR_CTRL__DIVISOR0" VALUE="5"/>
        <PARAMETER NAME="PSU__CRF_APB__DDR_CTRL__FREQMHZ" VALUE="533"/>
        <PARAMETER NAME="PSU__CRF_APB__DDR_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ" VALUE="600.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ" VALUE="600"/>
        <PARAMETER NAME="PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__DIV2" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__FBDIV" VALUE="72"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__FRACDATA" VALUE="0.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__FRACFREQ" VALUE="27.138"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ" VALUE="25"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0" VALUE="63"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ" VALUE="25"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL" VALUE="VPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ" VALUE="27"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1" VALUE="10"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ" VALUE="27"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL" VALUE="VPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ" VALUE="320"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0" VALUE="5"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ" VALUE="300"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ" VALUE="600.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ" VALUE="600"/>
        <PARAMETER NAME="PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ" VALUE="600"/>
        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ" VALUE="-1"/>
        <PARAMETER NAME="PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0" VALUE="-1"/>
        <PARAMETER NAME="PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ" VALUE="-1"/>
        <PARAMETER NAME="PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL" VALUE="NA"/>
        <PARAMETER NAME="PSU__CRF_APB__GTGREF0__ENABLE" VALUE="NA"/>
        <PARAMETER NAME="PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0" VALUE="5"/>
        <PARAMETER NAME="PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__SATA_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0" VALUE="5"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ" VALUE="525.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ" VALUE="533.333"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL" VALUE="VPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__DIV2" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__FBDIV" VALUE="63"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__FRACDATA" VALUE="0.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__FRACFREQ" VALUE="27.138"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ" VALUE="500.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__AFI6__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ" VALUE="50.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0" VALUE="30"/>
        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ" VALUE="50"/>
        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ" VALUE="500.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ" VALUE="180"/>
        <PARAMETER NAME="PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ" VALUE="180"/>
        <PARAMETER NAME="PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL" VALUE="SysOsc"/>
        <PARAMETER NAME="PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ" VALUE="250.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ" VALUE="1000"/>
        <PARAMETER NAME="PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ" VALUE="1000"/>
        <PARAMETER NAME="PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ" VALUE="1500.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ" VALUE="1500"/>
        <PARAMETER NAME="PSU__CRL_APB__DLL_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0" VALUE="12"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0" VALUE="12"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ" VALUE="125.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0" VALUE="12"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0" VALUE="12"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ" VALUE="250.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__DIV2" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__FBDIV" VALUE="90"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__FRACDATA" VALUE="0.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__FRACFREQ" VALUE="27.138"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ" VALUE="240.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0" VALUE="5"/>
        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ" VALUE="267"/>
        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ" VALUE="500.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ" VALUE="187.500000"/>
        <PARAMETER NAME="PSU__CRL_APB__PCAP_CTRL__DIVISOR0" VALUE="8"/>
        <PARAMETER NAME="PSU__CRL_APB__PCAP_CTRL__FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__PCAP_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ" VALUE="400.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ" VALUE="400"/>
        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ" VALUE="250.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ" VALUE="300.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0" VALUE="4"/>
        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ" VALUE="300"/>
        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ" VALUE="300.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0" VALUE="5"/>
        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ" VALUE="300"/>
        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__DIV2" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__FBDIV" VALUE="72"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__FRACDATA" VALUE="0.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__FRACFREQ" VALUE="27.138"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0" VALUE="7"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ" VALUE="200.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ" VALUE="200.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ" VALUE="214"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0" VALUE="7"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ" VALUE="250.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ" VALUE="20.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0" VALUE="25"/>
        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ" VALUE="20"/>
        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__USB3__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSUPMU__PERIPHERAL__VALID" VALUE="1"/>
        <PARAMETER NAME="PSU__CSU_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_0__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_0__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_10__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_10__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_11__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_11__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_12__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_12__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_1__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_2__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_2__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_3__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_3__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_4__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_4__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_5__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_5__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_6__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_6__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_7__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_7__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_8__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_8__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_9__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_9__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDRC__ADDR_MIRROR" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__AL" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__BANK_ADDR_COUNT" VALUE="3"/>
        <PARAMETER NAME="PSU__DDRC__BG_ADDR_COUNT" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__BRC_MAPPING" VALUE="ROW_BANK_COL"/>
        <PARAMETER NAME="PSU__DDRC__BUS_WIDTH" VALUE="32 Bit"/>
        <PARAMETER NAME="PSU__DDRC__CL" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__CLOCK_STOP_EN" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__COL_ADDR_COUNT" VALUE="10"/>
        <PARAMETER NAME="PSU__DDRC__COMPONENTS" VALUE="Components"/>
        <PARAMETER NAME="PSU__DDRC__CWL" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__DDR3L_T_REF_RANGE" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__DDR3_T_REF_RANGE" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__DDR4_ADDR_MAPPING" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__DDR4_CAL_MODE_ENABLE" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__DDR4_CRC_CONTROL" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__DDR4_MAXPWR_SAVING_EN" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__DDR4_T_REF_MODE" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__DDR4_T_REF_RANGE" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__DEEP_PWR_DOWN_EN" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DERATE_INT_D" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDRC__DEVICE_CAPACITY" VALUE="8192 MBits"/>
        <PARAMETER NAME="PSU__DDRC__DIMM_ADDR_MIRROR" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DM_DBI" VALUE="DM_NO_DBI"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_0_3" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_12_15" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_16_19" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_20_23" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_24_27" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_28_31" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_32_35" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_36_39" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_40_43" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_44_47" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_48_51" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_4_7" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_52_55" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_56_59" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_60_63" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_64_67" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_68_71" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_8_11" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DRAM_WIDTH" VALUE="32 Bits"/>
        <PARAMETER NAME="PSU__DDRC__ECC" VALUE="Disabled"/>
        <PARAMETER NAME="PSU__DDRC__ECC_SCRUB" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__ENABLE_2T_TIMING" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__ENABLE_DP_SWITCH" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__ENABLE_LP4_SLOWBOOT" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__EN_2ND_CLK" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__FGRM" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__FREQ_MHZ" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__HIGH_TEMP" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDRC__LPDDR3_DUALRANK_SDP" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__LPDDR3_T_REF_RANGE" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__LPDDR4_T_REF_RANGE" VALUE="Normal (0-85)"/>
        <PARAMETER NAME="PSU__DDRC__LP_ASR" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__MEMORY_TYPE" VALUE="LPDDR 4"/>
        <PARAMETER NAME="PSU__DDRC__PARITY_ENABLE" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__PARTNO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDRC__PER_BANK_REFRESH" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__PHY_DBI_MODE" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__PLL_BYPASS" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__PWR_DOWN_EN" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__RANK_ADDR_COUNT" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__RD_DQS_CENTER" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__ROW_ADDR_COUNT" VALUE="15"/>
        <PARAMETER NAME="PSU__DDRC__SB_TARGET" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__SELF_REF_ABORT" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__SPEED_BIN" VALUE="LPDDR4_1066"/>
        <PARAMETER NAME="PSU__DDRC__STATIC_RD_MODE" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__TRAIN_DATA_EYE" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__TRAIN_READ_GATE" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__TRAIN_WRITE_LEVEL" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__T_FAW" VALUE="40.0"/>
        <PARAMETER NAME="PSU__DDRC__T_RAS_MIN" VALUE="42"/>
        <PARAMETER NAME="PSU__DDRC__T_RC" VALUE="63"/>
        <PARAMETER NAME="PSU__DDRC__T_RCD" VALUE="10"/>
        <PARAMETER NAME="PSU__DDRC__T_RP" VALUE="12"/>
        <PARAMETER NAME="PSU__DDRC__VENDOR_PART" VALUE="OTHERS"/>
        <PARAMETER NAME="PSU__DDRC__VIDEO_BUFFER_SIZE" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__VREF" VALUE="1"/>
        <PARAMETER NAME="PSU__DDR_HIGH_ADDRESS_GUI_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__DDR_QOS_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP0_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP0_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP1_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP1_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP2_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP2_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP3_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP3_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP0_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP0_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP1_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP1_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP2_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP2_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP3_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP3_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT0_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT1_VN1_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT1_VN2_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT2_VN1_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT2_VN2_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT3_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT4_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT5_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_RD_HPR_THRSHLD"/>
        <PARAMETER NAME="PSU__DDR_QOS_RD_LPR_THRSHLD"/>
        <PARAMETER NAME="PSU__DDR_QOS_WR_THRSHLD"/>
        <PARAMETER NAME="PSU__DDR_SW_REFRESH_ENABLED" VALUE="1"/>
        <PARAMETER NAME="PSU__DDR__INTERFACE__FREQMHZ" VALUE="266.500"/>
        <PARAMETER NAME="PSU__DEVICE_TYPE" VALUE="CG"/>
        <PARAMETER NAME="PSU__DISPLAYPORT__LANE0__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__DISPLAYPORT__LANE0__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DISPLAYPORT__LANE1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__DISPLAYPORT__LANE1__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DISPLAYPORT__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__DLL__ISUSED" VALUE="1"/>
        <PARAMETER NAME="PSU__DPAUX__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__DPAUX__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DP__LANE_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DP__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DP__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__ENABLE__DDR__REFRESH__SIGNALS" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET0__FIFO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET0__GRP_MDIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET0__GRP_MDIO__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__ENET0__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET0__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__ENET0__PTP__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET0__TSU__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET1__FIFO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET1__GRP_MDIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET1__GRP_MDIO__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__ENET1__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__ENET1__PTP__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET1__TSU__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET2__FIFO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET2__GRP_MDIO__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__ENET2__GRP_MDIO__IO" VALUE="MIO 76 .. 77"/>
        <PARAMETER NAME="PSU__ENET2__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__ENET2__PERIPHERAL__IO" VALUE="MIO 52 .. 63"/>
        <PARAMETER NAME="PSU__ENET2__PTP__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET2__TSU__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET3__FIFO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET3__GRP_MDIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET3__GRP_MDIO__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__ENET3__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET3__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__ENET3__PTP__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET3__TSU__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__EN_AXI_STATUS_PORTS" VALUE="0"/>
        <PARAMETER NAME="PSU__EN_EMIO_TRACE" VALUE="0"/>
        <PARAMETER NAME="PSU__EP__IP" VALUE="0"/>
        <PARAMETER NAME="PSU__EXPAND__CORESIGHT" VALUE="0"/>
        <PARAMETER NAME="PSU__EXPAND__FPD_SLAVES" VALUE="0"/>
        <PARAMETER NAME="PSU__EXPAND__GIC" VALUE="0"/>
        <PARAMETER NAME="PSU__EXPAND__LOWER_LPS_SLAVES" VALUE="0"/>
        <PARAMETER NAME="PSU__EXPAND__UPPER_LPS_SLAVES" VALUE="0"/>
        <PARAMETER NAME="PSU__FPDMASTERS_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__FPD_SLCR__WDT1__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__FPD_SLCR__WDT1__FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__FPD_SLCR__WDT_CLK_SEL__SELECT" VALUE="APB"/>
        <PARAMETER NAME="PSU__FPGA_PL0_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__FPGA_PL1_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__FPGA_PL2_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__FPGA_PL3_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__FP__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__FTM__CTI_IN_0" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_IN_1" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_IN_2" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_IN_3" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_OUT_0" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_OUT_1" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_OUT_2" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_OUT_3" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__GPI" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__GPO" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM0_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM0_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM0__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM0__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM1_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM1_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM1__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM1__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM2_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM2_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM2__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM2__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM3_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM3_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM3__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM3__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM__TSU__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM__TSU__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEN_IPI_0__MASTER" VALUE="APU"/>
        <PARAMETER NAME="PSU__GEN_IPI_10__MASTER" VALUE="NONE"/>
        <PARAMETER NAME="PSU__GEN_IPI_1__MASTER" VALUE="RPU0"/>
        <PARAMETER NAME="PSU__GEN_IPI_2__MASTER" VALUE="RPU1"/>
        <PARAMETER NAME="PSU__GEN_IPI_3__MASTER" VALUE="PMU"/>
        <PARAMETER NAME="PSU__GEN_IPI_4__MASTER" VALUE="PMU"/>
        <PARAMETER NAME="PSU__GEN_IPI_5__MASTER" VALUE="PMU"/>
        <PARAMETER NAME="PSU__GEN_IPI_6__MASTER" VALUE="PMU"/>
        <PARAMETER NAME="PSU__GEN_IPI_7__MASTER" VALUE="NONE"/>
        <PARAMETER NAME="PSU__GEN_IPI_8__MASTER" VALUE="NONE"/>
        <PARAMETER NAME="PSU__GEN_IPI_9__MASTER" VALUE="NONE"/>
        <PARAMETER NAME="PSU__GEN_IPI__TRUSTZONE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GPIO0_MIO__IO" VALUE="MIO 0 .. 25"/>
        <PARAMETER NAME="PSU__GPIO0_MIO__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__GPIO1_MIO__IO" VALUE="MIO 26 .. 51"/>
        <PARAMETER NAME="PSU__GPIO1_MIO__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__GPIO2_MIO__IO" VALUE="MIO 52 .. 77"/>
        <PARAMETER NAME="PSU__GPIO2_MIO__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__GPIO_EMIO_WIDTH" VALUE="95"/>
        <PARAMETER NAME="PSU__GPIO_EMIO__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__GPIO_EMIO__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GPIO_EMIO__WIDTH" VALUE="[94:0]"/>
        <PARAMETER NAME="PSU__GPU_PP0__POWER__ON" VALUE="0"/>
        <PARAMETER NAME="PSU__GPU_PP1__POWER__ON" VALUE="0"/>
        <PARAMETER NAME="PSU__GT_REF_CLK__FREQMHZ" VALUE="33.333"/>
        <PARAMETER NAME="PSU__GT__LINK_SPEED" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GT__PRE_EMPH_LVL_4"/>
        <PARAMETER NAME="PSU__GT__VLT_SWNG_LVL_4"/>
        <PARAMETER NAME="PSU__HIGH_ADDRESS__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__HPM0_FPD__NUM_READ_THREADS" VALUE="4"/>
        <PARAMETER NAME="PSU__HPM0_FPD__NUM_WRITE_THREADS" VALUE="4"/>
        <PARAMETER NAME="PSU__HPM0_LPD__NUM_READ_THREADS" VALUE="4"/>
        <PARAMETER NAME="PSU__HPM0_LPD__NUM_WRITE_THREADS" VALUE="4"/>
        <PARAMETER NAME="PSU__HPM1_FPD__NUM_READ_THREADS" VALUE="4"/>
        <PARAMETER NAME="PSU__HPM1_FPD__NUM_WRITE_THREADS" VALUE="4"/>
        <PARAMETER NAME="PSU__I2C0_LOOP_I2C1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__I2C0__GRP_INT__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__I2C0__GRP_INT__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__I2C0__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__I2C0__PERIPHERAL__IO" VALUE="EMIO"/>
        <PARAMETER NAME="PSU__I2C1__GRP_INT__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__I2C1__GRP_INT__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__I2C1__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__I2C1__PERIPHERAL__IO" VALUE="MIO 8 .. 9"/>
        <PARAMETER NAME="PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL" VALUE="APB"/>
        <PARAMETER NAME="PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL" VALUE="APB"/>
        <PARAMETER NAME="PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL" VALUE="APB"/>
        <PARAMETER NAME="PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL" VALUE="APB"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC0__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC0__FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC1__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC1__FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC2__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC2__FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC3__ACT_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC3__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__IOU_SLCR__WDT0__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__WDT0__FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__WDT_CLK_SEL__SELECT" VALUE="APB"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ADMA_CHAN__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_AIB_AXI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_AMS__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APM_FPD__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_COMM__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_CPUMNT__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_CTI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_EXTERR__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_IPI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_L2ERR__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_PMU__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_REGS__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ATB_LPD__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_CAN0__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_CAN1__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_CLKMON__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_CSUPMU_WDT__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_CSU_DMA__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_CSU__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_DDR_SS__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_DPDMA__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_DPORT__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_EFUSE__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT0_WAKEUP__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT0__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT1_WAKEUP__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT1__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT2_WAKEUP__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT2__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT3_WAKEUP__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT3__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_FPD_APB__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_FPD_ATB_ERR__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_FP_WDT__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_GDMA_CHAN__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_GPIO__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_GPU__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_I2C0__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_I2C1__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_LPD_APB__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_LPD_APM__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_LP_WDT__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_NAND__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_OCM_ERR__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_PCIE_DMA__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_PCIE_LEGACY__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_PCIE_MSC__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_PCIE_MSI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_PL_IPI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_QSPI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_RPU_IPI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_RPU_PERMON__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_RTC_ALARM__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_RTC_SECONDS__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SATA__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SDIO0_WAKE__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SDIO0__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SDIO1_WAKE__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SDIO1__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SPI0__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SPI1__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC0__INT0" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC0__INT1" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC0__INT2" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC1__INT0" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC1__INT1" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC1__INT2" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC2__INT0" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC2__INT1" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC2__INT2" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC3__INT0" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC3__INT1" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC3__INT2" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_UART0__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_UART1__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_USB3_ENDPOINT__INT0" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_USB3_ENDPOINT__INT1" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_USB3_OTG__INT0" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_USB3_OTG__INT1" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_XMPU_FPD__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_XMPU_LPD__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F__INTF_FPD_SMMU__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F__INTF_PPD_CCI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__L2_BANK0__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__LPDMA0_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA1_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA2_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA3_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA4_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA5_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA6_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA7_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT" VALUE="APB"/>
        <PARAMETER NAME="PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__LPD_SLCR__CSUPMU__FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__MAXIGP0__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__MAXIGP1__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__MAXIGP2__DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST" VALUE="1"/>
        <PARAMETER NAME="PSU__M_AXI_GP0__FREQMHZ" VALUE="100.0"/>
        <PARAMETER NAME="PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST" VALUE="1"/>
        <PARAMETER NAME="PSU__M_AXI_GP1__FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST" VALUE="1"/>
        <PARAMETER NAME="PSU__M_AXI_GP2__FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PSU__NAND_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND__CHIP_ENABLE__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND__CHIP_ENABLE__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__NAND__DATA_STROBE__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND__DATA_STROBE__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__NAND__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__NAND__READY0_BUSY__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND__READY0_BUSY__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__NAND__READY1_BUSY__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND__READY1_BUSY__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__NAND__READY_BUSY__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND__READY_BUSY__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__NUM_F2P0__INTR__INPUTS" VALUE="1"/>
        <PARAMETER NAME="PSU__NUM_F2P1__INTR__INPUTS" VALUE="1"/>
        <PARAMETER NAME="PSU__NUM_FABRIC_RESETS" VALUE="1"/>
        <PARAMETER NAME="PSU__OCM_BANK0__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__OCM_BANK1__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__OCM_BANK2__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__OCM_BANK3__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__OVERRIDE_HPX_QOS" VALUE="0"/>
        <PARAMETER NAME="PSU__OVERRIDE__BASIC_CLOCK" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__ACS_VIOLAION" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__ACS_VIOLATION" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__AER_CAPABILITY" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__ATOMICOP_EGRESS_BLOCKED" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_64BIT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_PREFETCHABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_VAL"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_64BIT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_PREFETCHABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_VAL"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_64BIT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_PREFETCHABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_VAL"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_64BIT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_PREFETCHABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_VAL"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_64BIT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_PREFETCHABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_VAL"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_64BIT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_PREFETCHABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_VAL"/>
        <PARAMETER NAME="PSU__PCIE__BASE_CLASS_MENU" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BRIDGE_BAR_INDICATOR" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__CAP_SLOT_IMPLEMENTED" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__CLASS_CODE_BASE"/>
        <PARAMETER NAME="PSU__PCIE__CLASS_CODE_INTERFACE"/>
        <PARAMETER NAME="PSU__PCIE__CLASS_CODE_SUB"/>
        <PARAMETER NAME="PSU__PCIE__CLASS_CODE_VALUE"/>
        <PARAMETER NAME="PSU__PCIE__COMPLETER_ABORT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__COMPLTION_TIMEOUT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__CORRECTABLE_INT_ERR" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__CRS_SW_VISIBILITY" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__DEVICE_ID"/>
        <PARAMETER NAME="PSU__PCIE__DEVICE_PORT_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__ECRC_CHECK" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__ECRC_ERR" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__ECRC_GEN" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__EROM_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__EROM_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__EROM_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__EROM_VAL"/>
        <PARAMETER NAME="PSU__PCIE__FLOW_CONTROL_ERR" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__HEADER_LOG_OVERFLOW" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__INTERFACE_WIDTH" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__INTX_GENERATION" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__INTX_PIN" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__LANE0__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__LANE0__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__LANE1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__LANE1__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__LANE2__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__LANE2__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__LANE3__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__LANE3__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__LEGACY_INTERRUPT" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__LINK_SPEED" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__MAXIMUM_LINK_WIDTH" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__MAX_PAYLOAD_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__MC_BLOCKED_TLP" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MSIX_BAR_INDICATOR"/>
        <PARAMETER NAME="PSU__PCIE__MSIX_CAPABILITY" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MSIX_PBA_BAR_INDICATOR"/>
        <PARAMETER NAME="PSU__PCIE__MSIX_PBA_OFFSET" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MSIX_TABLE_OFFSET" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MSIX_TABLE_SIZE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MSI_64BIT_ADDR_CAPABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MSI_CAPABILITY" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MSI_MULTIPLE_MSG_CAPABLE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__MULTIHEADER" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ENDPOINT_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ROOTPORT_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__PERM_ROOT_ERR_UPDATE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__RECEIVER_ERR" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__RECEIVER_OVERFLOW" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__RESET__POLARITY" VALUE="Active Low"/>
        <PARAMETER NAME="PSU__PCIE__REVISION_ID"/>
        <PARAMETER NAME="PSU__PCIE__SUBSYSTEM_ID"/>
        <PARAMETER NAME="PSU__PCIE__SUBSYSTEM_VENDOR_ID"/>
        <PARAMETER NAME="PSU__PCIE__SUB_CLASS_INTERFACE_MENU" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__SURPRISE_DOWN" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__TLP_PREFIX_BLOCKED" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__UNCORRECTABL_INT_ERR" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__USE_CLASS_CODE_LOOKUP_ASSISTANT" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__VENDOR_ID"/>
        <PARAMETER NAME="PSU__PJTAG__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PJTAG__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PL_CLK0_BUF" VALUE="TRUE"/>
        <PARAMETER NAME="PSU__PL_CLK1_BUF" VALUE="TRUE"/>
        <PARAMETER NAME="PSU__PL_CLK2_BUF" VALUE="TRUE"/>
        <PARAMETER NAME="PSU__PL_CLK3_BUF" VALUE="TRUE"/>
        <PARAMETER NAME="PSU__PL__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__PMU_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__AIBACK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__EMIO_GPI__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__EMIO_GPO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPI0__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__PMU__GPI0__IO" VALUE="MIO 26"/>
        <PARAMETER NAME="PSU__PMU__GPI1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPI1__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPI2__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPI2__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPI3__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPI3__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPI4__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPI4__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPI5__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPI5__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPO0__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPO0__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPO1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPO1__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPO2__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__PMU__GPO2__IO" VALUE="MIO 34"/>
        <PARAMETER NAME="PSU__PMU__GPO2__POLARITY" VALUE="low"/>
        <PARAMETER NAME="PSU__PMU__GPO3__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPO3__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPO3__POLARITY" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPO4__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPO4__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPO4__POLARITY" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPO5__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPO5__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPO5__POLARITY" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__PMU__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__PLERROR__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PRESET_APPLIED" VALUE="0"/>
        <PARAMETER NAME="PSU__PROTECTION__DDR_SEGMENTS" VALUE="NONE"/>
        <PARAMETER NAME="PSU__PROTECTION__DEBUG" VALUE="0"/>
        <PARAMETER NAME="PSU__PROTECTION__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PROTECTION__FPD_SEGMENTS" VALUE="SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |  SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |  SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |  SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |  SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |  SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |  SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |  SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |  SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem"/>
        <PARAMETER NAME="PSU__PROTECTION__LOCK_UNUSED_SEGMENTS" VALUE="0"/>
        <PARAMETER NAME="PSU__PROTECTION__LPD_SEGMENTS" VALUE="SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem"/>
        <PARAMETER NAME="PSU__PROTECTION__MASTERS" VALUE="USB1:NonSecure;1|USB0:NonSecure;0|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;1|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;1|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1"/>
        <PARAMETER NAME="PSU__PROTECTION__MASTERS_TZ" VALUE="GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure"/>
        <PARAMETER NAME="PSU__PROTECTION__OCM_SEGMENTS" VALUE="NONE"/>
        <PARAMETER NAME="PSU__PROTECTION__PRESUBSYSTEMS" VALUE="NONE"/>
        <PARAMETER NAME="PSU__PROTECTION__SLAVES" VALUE="LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;0|LPD;USB3_0;FF9D0000;FF9DFFFF;0|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;1|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;3FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1"/>
        <PARAMETER NAME="PSU__PROTECTION__SUBSYSTEMS" VALUE="PMU Firmware:PMU|Secure Subsystem:"/>
        <PARAMETER NAME="PSU__PSS_ALT_REF_CLK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PSS_ALT_REF_CLK__FREQMHZ" VALUE="33.333"/>
        <PARAMETER NAME="PSU__PSS_ALT_REF_CLK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PSS_REF_CLK__FREQMHZ" VALUE="33.33333333333333333"/>
        <PARAMETER NAME="PSU__QSPI_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__QSPI_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__QSPI__GRP_FBCLK__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__QSPI__GRP_FBCLK__IO" VALUE="MIO 6"/>
        <PARAMETER NAME="PSU__QSPI__PERIPHERAL__DATA_MODE" VALUE="x4"/>
        <PARAMETER NAME="PSU__QSPI__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__QSPI__PERIPHERAL__IO" VALUE="MIO 0 .. 5"/>
        <PARAMETER NAME="PSU__QSPI__PERIPHERAL__MODE" VALUE="Single"/>
        <PARAMETER NAME="PSU__REPORT__DBGLOG" VALUE="0"/>
        <PARAMETER NAME="PSU__RPU_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__RPU__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__SATA__LANE0__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SATA__LANE0__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SATA__LANE1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SATA__LANE1__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SATA__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SATA__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SATA__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SAXIGP0__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__SAXIGP1__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__SAXIGP2__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__SAXIGP3__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__SAXIGP4__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__SAXIGP5__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__SAXIGP6__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__SD0_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__SD0_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__SD0__CLK_100_SDR_OTAP_DLY" VALUE="0x00"/>
        <PARAMETER NAME="PSU__SD0__CLK_200_SDR_OTAP_DLY" VALUE="0x00"/>
        <PARAMETER NAME="PSU__SD0__CLK_50_DDR_ITAP_DLY" VALUE="0x00"/>
        <PARAMETER NAME="PSU__SD0__CLK_50_DDR_OTAP_DLY" VALUE="0x00"/>
        <PARAMETER NAME="PSU__SD0__CLK_50_SDR_ITAP_DLY" VALUE="0x00"/>
        <PARAMETER NAME="PSU__SD0__CLK_50_SDR_OTAP_DLY" VALUE="0x00"/>
        <PARAMETER NAME="PSU__SD0__DATA_TRANSFER_MODE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD0__GRP_CD__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD0__GRP_CD__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD0__GRP_POW__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD0__GRP_POW__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD0__GRP_WP__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD0__GRP_WP__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD0__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD0__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD0__RESET__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD0__SLOT_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD1_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__SD1_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__SD1__CLK_100_SDR_OTAP_DLY" VALUE="0x0"/>
        <PARAMETER NAME="PSU__SD1__CLK_200_SDR_OTAP_DLY" VALUE="0x0"/>
        <PARAMETER NAME="PSU__SD1__CLK_50_DDR_ITAP_DLY" VALUE="0x0"/>
        <PARAMETER NAME="PSU__SD1__CLK_50_DDR_OTAP_DLY" VALUE="0x0"/>
        <PARAMETER NAME="PSU__SD1__CLK_50_SDR_ITAP_DLY" VALUE="0x15"/>
        <PARAMETER NAME="PSU__SD1__CLK_50_SDR_OTAP_DLY" VALUE="0x5"/>
        <PARAMETER NAME="PSU__SD1__DATA_TRANSFER_MODE" VALUE="4Bit"/>
        <PARAMETER NAME="PSU__SD1__GRP_CD__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SD1__GRP_CD__IO" VALUE="MIO 45"/>
        <PARAMETER NAME="PSU__SD1__GRP_POW__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD1__GRP_POW__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD1__GRP_WP__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD1__GRP_WP__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD1__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SD1__PERIPHERAL__IO" VALUE="MIO 46 .. 51"/>
        <PARAMETER NAME="PSU__SD1__RESET__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD1__SLOT_TYPE" VALUE="SD 2.0"/>
        <PARAMETER NAME="PSU__SPI0_LOOP_SPI1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SPI0__GRP_SS0__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SPI0__GRP_SS0__IO" VALUE="EMIO"/>
        <PARAMETER NAME="PSU__SPI0__GRP_SS1__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SPI0__GRP_SS1__IO" VALUE="EMIO"/>
        <PARAMETER NAME="PSU__SPI0__GRP_SS2__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SPI0__GRP_SS2__IO" VALUE="EMIO"/>
        <PARAMETER NAME="PSU__SPI0__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SPI0__PERIPHERAL__IO" VALUE="EMIO"/>
        <PARAMETER NAME="PSU__SPI1__GRP_SS0__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SPI1__GRP_SS0__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SPI1__GRP_SS1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SPI1__GRP_SS1__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SPI1__GRP_SS2__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SPI1__GRP_SS2__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SPI1__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SPI1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SWDT0__CLOCK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SWDT0__CLOCK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SWDT0__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SWDT0__PERIPHERAL__IO" VALUE="NA"/>
        <PARAMETER NAME="PSU__SWDT0__RESET__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SWDT0__RESET__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SWDT1__CLOCK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SWDT1__CLOCK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SWDT1__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SWDT1__PERIPHERAL__IO" VALUE="NA"/>
        <PARAMETER NAME="PSU__SWDT1__RESET__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SWDT1__RESET__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__S_AXI_GP0__FREQMHZ" VALUE="300.0"/>
        <PARAMETER NAME="PSU__S_AXI_GP1__FREQMHZ" VALUE="300.0"/>
        <PARAMETER NAME="PSU__S_AXI_GP2__FREQMHZ" VALUE="300.0"/>
        <PARAMETER NAME="PSU__S_AXI_GP3__FREQMHZ" VALUE="300.0"/>
        <PARAMETER NAME="PSU__S_AXI_GP4__FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PSU__S_AXI_GP5__FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PSU__S_AXI_GP6__FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PSU__TCM0A__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__TCM0B__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__TCM1A__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__TCM1B__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__TESTSCAN__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TRACE_PIPELINE_WIDTH" VALUE="8"/>
        <PARAMETER NAME="PSU__TRACE__INTERNAL_WIDTH" VALUE="32"/>
        <PARAMETER NAME="PSU__TRACE__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TRACE__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TRACE__WIDTH" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TRISTATE__INVERTED" VALUE="1"/>
        <PARAMETER NAME="PSU__TSU__BUFG_PORT_LOOPBACK" VALUE="0"/>
        <PARAMETER NAME="PSU__TSU__BUFG_PORT_PAIR" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC0__CLOCK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC0__CLOCK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC0__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__TTC0__PERIPHERAL__IO" VALUE="NA"/>
        <PARAMETER NAME="PSU__TTC0__WAVEOUT__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC0__WAVEOUT__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC1__CLOCK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC1__CLOCK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC1__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__TTC1__PERIPHERAL__IO" VALUE="NA"/>
        <PARAMETER NAME="PSU__TTC1__WAVEOUT__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC1__WAVEOUT__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC2__CLOCK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC2__CLOCK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC2__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__TTC2__PERIPHERAL__IO" VALUE="NA"/>
        <PARAMETER NAME="PSU__TTC2__WAVEOUT__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC2__WAVEOUT__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC3__CLOCK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC3__CLOCK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC3__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC3__PERIPHERAL__IO" VALUE="NA"/>
        <PARAMETER NAME="PSU__TTC3__WAVEOUT__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC3__WAVEOUT__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__UART0_LOOP_UART1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__UART0__BAUD_RATE" VALUE="115200"/>
        <PARAMETER NAME="PSU__UART0__MODEM__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__UART0__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__UART0__PERIPHERAL__IO" VALUE="MIO 10 .. 11"/>
        <PARAMETER NAME="PSU__UART1__BAUD_RATE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__UART1__MODEM__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__UART1__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__UART1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB0_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__USB0__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB0__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB0__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB0__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB0__RESET__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB0__RESET__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB1_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__USB1__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__USB1__PERIPHERAL__IO" VALUE="MIO 64 .. 75"/>
        <PARAMETER NAME="PSU__USB1__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB1__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB1__RESET__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB1__RESET__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB2_0__EMIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB2_1__EMIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB3_0__EMIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB3_0__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB3_0__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB3_1__EMIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB3_1__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB3_1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB__RESET__MODE" VALUE="Boot Pin"/>
        <PARAMETER NAME="PSU__USB__RESET__POLARITY" VALUE="Active Low"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP0" VALUE="0"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP1" VALUE="0"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP2" VALUE="0"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP3" VALUE="0"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP4" VALUE="0"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP5" VALUE="0"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP6" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__ADMA" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__APU_LEGACY_INTERRUPT" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__AUDIO" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__CLK" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__CLK0" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__CLK1" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__CLK2" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__CLK3" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__CROSS_TRIGGER" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__DDR_INTF_REQUESTED" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__DEBUG__TEST" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__EVENT_RPU" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__FABRIC__RST" VALUE="1"/>
        <PARAMETER NAME="PSU__USE__FTM" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__GDMA" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__IRQ" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__IRQ0" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__IRQ1" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__M_AXI_GP0" VALUE="1"/>
        <PARAMETER NAME="PSU__USE__M_AXI_GP1" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__M_AXI_GP2" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__PROC_EVENT_BUS" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__RPU_LEGACY_INTERRUPT" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__RST0" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__RST1" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__RST2" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__RST3" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__RTC" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__STM" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__S_AXI_ACE" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__S_AXI_ACP" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP0" VALUE="1"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP1" VALUE="1"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP2" VALUE="1"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP3" VALUE="1"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP4" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP5" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP6" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__USB3_0_HUB" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__USB3_1_HUB" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__VIDEO" VALUE="0"/>
        <PARAMETER NAME="PSU__VIDEO_REF_CLK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__VIDEO_REF_CLK__FREQMHZ" VALUE="33.333"/>
        <PARAMETER NAME="PSU__VIDEO_REF_CLK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="QSPI_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SATA_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SD0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SD1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SPI0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SPI1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SUBPRESET1" VALUE="Custom"/>
        <PARAMETER NAME="SUBPRESET2" VALUE="Custom"/>
        <PARAMETER NAME="SWDT0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SWDT1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="TRACE_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="TTC0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="TTC1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="TTC2_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="TTC3_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="UART0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="UART1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="USB0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="USB1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="preset" VALUE="None"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0x00000000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0x7FFFFFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="emio_i2c0_scl_i" SIGIS="undef" SIGNAME="Iffo120g_core_0_psI2c0Scl_in">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="psI2c0Scl_in"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="emio_i2c0_scl_o" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_i2c0_scl_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="psI2c0Scl_out"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="emio_i2c0_scl_t" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_i2c0_scl_t">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="psI2c0Scl_tri"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="emio_i2c0_sda_i" SIGIS="undef" SIGNAME="Iffo120g_core_0_psI2c0Sda_in">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="psI2c0Sda_in"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="emio_i2c0_sda_o" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_i2c0_sda_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="psI2c0Sda_out"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="emio_i2c0_sda_t" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_i2c0_sda_t">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="psI2c0Sda_tri"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="emio_spi0_m_i" SIGIS="undef" SIGNAME="Iffo120g_core_0_psSpi0Miso">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="psSpi0Miso"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="emio_spi0_m_o" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_spi0_m_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="psSpi0Mosi"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="emio_spi0_mo_t" SIGIS="undef"/>
        <PORT DIR="I" NAME="emio_spi0_s_i" SIGIS="undef"/>
        <PORT DIR="O" NAME="emio_spi0_s_o" SIGIS="undef"/>
        <PORT DIR="I" NAME="emio_spi0_sclk_i" SIGIS="undef"/>
        <PORT DIR="O" NAME="emio_spi0_sclk_o" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_spi0_sclk_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="psSpi0Sclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="emio_spi0_sclk_t" SIGIS="undef"/>
        <PORT DIR="O" NAME="emio_spi0_so_t" SIGIS="undef"/>
        <PORT DIR="O" NAME="emio_spi0_ss1_o_n" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_spi0_ss1_o_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="psSpi0Ss1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="emio_spi0_ss2_o_n" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_spi0_ss2_o_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="psSpi0Ss2"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="emio_spi0_ss_i_n" SIGIS="undef"/>
        <PORT DIR="O" NAME="emio_spi0_ss_n_t" SIGIS="undef"/>
        <PORT DIR="O" NAME="emio_spi0_ss_o_n" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_emio_spi0_ss_o_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="psSpi0Ss0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="maxigp0_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="maxigp0_arburst" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="maxigp0_arcache" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp0_arid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="maxigp0_arlen" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_arlock" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="maxigp0_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="maxigp0_arqos" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp0_arready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="maxigp0_arsize" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp0_aruser" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_aruser">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_aruser"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_arvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="maxigp0_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="maxigp0_awburst" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="maxigp0_awcache" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp0_awid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="maxigp0_awlen" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_awlock" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="maxigp0_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="maxigp0_awqos" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp0_awready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="maxigp0_awsize" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp0_awuser" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awuser">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awuser"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_awvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="maxigp0_bid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_bready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="maxigp0_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp0_bvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="maxigp0_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="maxigp0_rid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp0_rlast" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_rready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="maxigp0_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp0_rvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="maxigp0_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_wlast" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp0_wready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp0_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_wvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="maxihpm0_fpd_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="O" NAME="pl_clk0" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_ACLK"/>
            <CONNECTION INSTANCE="rst_ps8_0_100M" PORT="slowest_sync_clk"/>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxihpm0_fpd_aclk"/>
            <CONNECTION INSTANCE="Base_core_0" PORT="aclk"/>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="aclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="400000000" DIR="O" NAME="pl_clk1" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xdspclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="250000000" DIR="O" NAME="pl_clk2" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk2">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="dspclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="300000000" DIR="O" NAME="pl_clk3" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxihpc0_fpd_aclk"/>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxihpc1_fpd_aclk"/>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxihp0_fpd_aclk"/>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxihp1_fpd_aclk"/>
            <CONNECTION INSTANCE="Base_core_0" PORT="memclk"/>
            <CONNECTION INSTANCE="Iffo120g_core_0" PORT="dlyclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="pl_resetn0" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="zynq_ultra_ps_e_0_pl_resetn0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ps8_0_100M" PORT="ext_reset_in"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="48" NAME="saxigp0_araddr" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="saxigp0_arburst" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="saxigp0_arcache" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="5" NAME="saxigp0_arid" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="7" NAME="saxigp0_arlen" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="saxigp0_arlock" SIGIS="undef"/>
        <PORT DIR="I" LEFT="2" NAME="saxigp0_arprot" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="saxigp0_arqos" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="saxigp0_arready" SIGIS="undef"/>
        <PORT DIR="I" LEFT="2" NAME="saxigp0_arsize" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="saxigp0_aruser" SIGIS="undef"/>
        <PORT DIR="I" NAME="saxigp0_arvalid" SIGIS="undef"/>
        <PORT DIR="I" LEFT="48" NAME="saxigp0_awaddr" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="saxigp0_awburst" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="saxigp0_awcache" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="5" NAME="saxigp0_awid" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="7" NAME="saxigp0_awlen" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="saxigp0_awlock" SIGIS="undef"/>
        <PORT DIR="I" LEFT="2" NAME="saxigp0_awprot" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="saxigp0_awqos" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="saxigp0_awready" SIGIS="undef"/>
        <PORT DIR="I" LEFT="2" NAME="saxigp0_awsize" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="saxigp0_awuser" SIGIS="undef"/>
        <PORT DIR="I" NAME="saxigp0_awvalid" SIGIS="undef"/>
        <PORT DIR="O" LEFT="5" NAME="saxigp0_bid" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="saxigp0_bready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="1" NAME="saxigp0_bresp" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="saxigp0_bvalid" SIGIS="undef"/>
        <PORT DIR="O" LEFT="127" NAME="saxigp0_rdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="5" NAME="saxigp0_rid" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="saxigp0_rlast" SIGIS="undef"/>
        <PORT DIR="I" NAME="saxigp0_rready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="1" NAME="saxigp0_rresp" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="saxigp0_rvalid" SIGIS="undef"/>
        <PORT DIR="I" LEFT="127" NAME="saxigp0_wdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="saxigp0_wlast" SIGIS="undef"/>
        <PORT DIR="O" NAME="saxigp0_wready" SIGIS="undef"/>
        <PORT DIR="I" LEFT="15" NAME="saxigp0_wstrb" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="saxigp0_wvalid" SIGIS="undef"/>
        <PORT DIR="I" LEFT="48" NAME="saxigp1_araddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="saxigp1_arburst" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp1_arcache" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="saxigp1_arid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="saxigp1_arlen" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp1_arlock" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp1_arprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp1_arqos" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp1_arready" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp1_arsize" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp1_arvalid" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="48" NAME="saxigp1_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="saxigp1_awburst" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp1_awcache" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="saxigp1_awid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="saxigp1_awlen" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp1_awlock" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp1_awprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp1_awqos" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp1_awready" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp1_awsize" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp1_awvalid" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="saxigp1_bid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp1_bready" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="saxigp1_bresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp1_bvalid" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="saxigp1_rdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="saxigp1_rid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp1_rlast" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp1_rready" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="saxigp1_rresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp1_rvalid" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="saxigp1_wdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp1_wlast" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp1_wready" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="saxigp1_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp1_wvalid" SIGIS="undef" SIGNAME="Base_core_0_xddrAXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="xddrAXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="48" NAME="saxigp2_araddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="saxigp2_arburst" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp2_arcache" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="saxigp2_arid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="saxigp2_arlen" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp2_arlock" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp2_arprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp2_arqos" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp2_arready" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp2_arsize" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp2_arvalid" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="48" NAME="saxigp2_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="saxigp2_awburst" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp2_awcache" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="saxigp2_awid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="saxigp2_awlen" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp2_awlock" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp2_awprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp2_awqos" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp2_awready" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp2_awsize" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp2_awvalid" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="saxigp2_bid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp2_bready" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="saxigp2_bresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp2_bvalid" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="saxigp2_rdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="saxigp2_rid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp2_rlast" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp2_rready" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="saxigp2_rresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp2_rvalid" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="saxigp2_wdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp2_wlast" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp2_wready" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="saxigp2_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp2_wvalid" SIGIS="undef" SIGNAME="Base_core_0_lddrAXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="lddrAXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="48" NAME="saxigp3_araddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="saxigp3_arburst" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp3_arcache" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="saxigp3_arid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="saxigp3_arlen" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp3_arlock" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp3_arprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp3_arqos" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp3_arready" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp3_arsize" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp3_arvalid" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="48" NAME="saxigp3_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="saxigp3_awburst" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp3_awcache" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="saxigp3_awid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="saxigp3_awlen" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp3_awlock" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp3_awprot" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp3_awqos" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp3_awready" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp3_awsize" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp3_awvalid" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="saxigp3_bid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp3_bready" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="saxigp3_bresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp3_bvalid" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="saxigp3_rdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="saxigp3_rid" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp3_rlast" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp3_rready" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="saxigp3_rresp" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp3_rvalid" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="saxigp3_wdata" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp3_wlast" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp3_wready" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="saxigp3_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp3_wvalid" SIGIS="undef" SIGNAME="Base_core_0_sddrAXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="Base_core_0" PORT="sddrAXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="300000000" DIR="I" NAME="saxihp0_fpd_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk3"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="300000000" DIR="I" NAME="saxihp1_fpd_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk3"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="300000000" DIR="I" NAME="saxihpc0_fpd_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk3"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="300000000" DIR="I" NAME="saxihpc1_fpd_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk3"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="zynq_ultra_ps_e_0_M_AXI_HPM0_FPD" DATAWIDTH="128" NAME="M_AXI_HPM0_FPD" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="ADDR_WIDTH" VALUE="40"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="16"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="16"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="16"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="maxigp0_araddr"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="maxigp0_arburst"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="maxigp0_arcache"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="maxigp0_arid"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="maxigp0_arlen"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="maxigp0_arlock"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="maxigp0_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="maxigp0_arqos"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="maxigp0_arready"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="maxigp0_arsize"/>
            <PORTMAP LOGICAL="ARUSER" PHYSICAL="maxigp0_aruser"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="maxigp0_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="maxigp0_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="maxigp0_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="maxigp0_awcache"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="maxigp0_awid"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="maxigp0_awlen"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="maxigp0_awlock"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="maxigp0_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="maxigp0_awqos"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="maxigp0_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="maxigp0_awsize"/>
            <PORTMAP LOGICAL="AWUSER" PHYSICAL="maxigp0_awuser"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="maxigp0_awvalid"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="maxigp0_bid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="maxigp0_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="maxigp0_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="maxigp0_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="maxigp0_rdata"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="maxigp0_rid"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="maxigp0_rlast"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="maxigp0_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="maxigp0_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="maxigp0_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="maxigp0_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="maxigp0_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="maxigp0_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="maxigp0_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="maxigp0_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" DATAWIDTH="128" NAME="S_AXI_HPC0_FPD" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="ADDR_WIDTH" VALUE="49"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="1"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="1"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_zynq_ultra_ps_e_0_0_pl_clk3"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="300000000"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="6"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="saxigp0_araddr"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="saxigp0_arburst"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="saxigp0_arcache"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="saxigp0_arid"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="saxigp0_arlen"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="saxigp0_arlock"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="saxigp0_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="saxigp0_arqos"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="saxigp0_arready"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="saxigp0_arsize"/>
            <PORTMAP LOGICAL="ARUSER" PHYSICAL="saxigp0_aruser"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="saxigp0_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="saxigp0_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="saxigp0_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="saxigp0_awcache"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="saxigp0_awid"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="saxigp0_awlen"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="saxigp0_awlock"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="saxigp0_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="saxigp0_awqos"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="saxigp0_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="saxigp0_awsize"/>
            <PORTMAP LOGICAL="AWUSER" PHYSICAL="saxigp0_awuser"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="saxigp0_awvalid"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="saxigp0_bid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="saxigp0_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="saxigp0_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="saxigp0_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="saxigp0_rdata"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="saxigp0_rid"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="saxigp0_rlast"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="saxigp0_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="saxigp0_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="saxigp0_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="saxigp0_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="saxigp0_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="saxigp0_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="saxigp0_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="saxigp0_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Base_core_0_xddrAXI" DATAWIDTH="128" NAME="S_AXI_HPC1_FPD" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="ADDR_WIDTH" VALUE="49"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="1"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="1"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_zynq_ultra_ps_e_0_0_pl_clk3"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="300000000"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="6"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="saxigp1_araddr"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="saxigp1_arburst"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="saxigp1_arcache"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="saxigp1_arid"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="saxigp1_arlen"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="saxigp1_arlock"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="saxigp1_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="saxigp1_arqos"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="saxigp1_arready"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="saxigp1_arsize"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="saxigp1_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="saxigp1_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="saxigp1_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="saxigp1_awcache"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="saxigp1_awid"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="saxigp1_awlen"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="saxigp1_awlock"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="saxigp1_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="saxigp1_awqos"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="saxigp1_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="saxigp1_awsize"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="saxigp1_awvalid"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="saxigp1_bid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="saxigp1_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="saxigp1_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="saxigp1_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="saxigp1_rdata"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="saxigp1_rid"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="saxigp1_rlast"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="saxigp1_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="saxigp1_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="saxigp1_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="saxigp1_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="saxigp1_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="saxigp1_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="saxigp1_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="saxigp1_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Base_core_0_lddrAXI" DATAWIDTH="128" NAME="S_AXI_HP0_FPD" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="ADDR_WIDTH" VALUE="49"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="1"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="1"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_zynq_ultra_ps_e_0_0_pl_clk3"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="300000000"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="6"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="saxigp2_araddr"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="saxigp2_arburst"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="saxigp2_arcache"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="saxigp2_arid"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="saxigp2_arlen"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="saxigp2_arlock"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="saxigp2_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="saxigp2_arqos"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="saxigp2_arready"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="saxigp2_arsize"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="saxigp2_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="saxigp2_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="saxigp2_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="saxigp2_awcache"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="saxigp2_awid"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="saxigp2_awlen"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="saxigp2_awlock"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="saxigp2_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="saxigp2_awqos"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="saxigp2_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="saxigp2_awsize"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="saxigp2_awvalid"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="saxigp2_bid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="saxigp2_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="saxigp2_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="saxigp2_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="saxigp2_rdata"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="saxigp2_rid"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="saxigp2_rlast"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="saxigp2_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="saxigp2_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="saxigp2_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="saxigp2_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="saxigp2_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="saxigp2_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="saxigp2_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="saxigp2_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="Base_core_0_sddrAXI" DATAWIDTH="128" NAME="S_AXI_HP1_FPD" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="ADDR_WIDTH" VALUE="49"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="1"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="1"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_zynq_ultra_ps_e_0_0_pl_clk3"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="300000000"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="6"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="saxigp3_araddr"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="saxigp3_arburst"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="saxigp3_arcache"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="saxigp3_arid"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="saxigp3_arlen"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="saxigp3_arlock"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="saxigp3_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="saxigp3_arqos"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="saxigp3_arready"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="saxigp3_arsize"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="saxigp3_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="saxigp3_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="saxigp3_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="saxigp3_awcache"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="saxigp3_awid"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="saxigp3_awlen"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="saxigp3_awlock"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="saxigp3_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="saxigp3_awqos"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="saxigp3_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="saxigp3_awsize"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="saxigp3_awvalid"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="saxigp3_bid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="saxigp3_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="saxigp3_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="saxigp3_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="saxigp3_rdata"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="saxigp3_rid"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="saxigp3_rlast"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="saxigp3_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="saxigp3_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="saxigp3_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="saxigp3_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="saxigp3_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="saxigp3_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="saxigp3_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="saxigp3_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="IIC_0" TYPE="INITIATOR" VLNV="xilinx.com:interface:iic:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="SCL_I" PHYSICAL="emio_i2c0_scl_i"/>
            <PORTMAP LOGICAL="SCL_O" PHYSICAL="emio_i2c0_scl_o"/>
            <PORTMAP LOGICAL="SCL_T" PHYSICAL="emio_i2c0_scl_t"/>
            <PORTMAP LOGICAL="SDA_I" PHYSICAL="emio_i2c0_sda_i"/>
            <PORTMAP LOGICAL="SDA_O" PHYSICAL="emio_i2c0_sda_o"/>
            <PORTMAP LOGICAL="SDA_T" PHYSICAL="emio_i2c0_sda_t"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="SPI_0" TYPE="INITIATOR" VLNV="xilinx.com:interface:spi:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="IO0_I" PHYSICAL="emio_spi0_s_i"/>
            <PORTMAP LOGICAL="IO0_O" PHYSICAL="emio_spi0_m_o"/>
            <PORTMAP LOGICAL="IO0_T" PHYSICAL="emio_spi0_mo_t"/>
            <PORTMAP LOGICAL="IO1_I" PHYSICAL="emio_spi0_m_i"/>
            <PORTMAP LOGICAL="IO1_O" PHYSICAL="emio_spi0_s_o"/>
            <PORTMAP LOGICAL="IO1_T" PHYSICAL="emio_spi0_so_t"/>
            <PORTMAP LOGICAL="SCK_I" PHYSICAL="emio_spi0_sclk_i"/>
            <PORTMAP LOGICAL="SCK_O" PHYSICAL="emio_spi0_sclk_o"/>
            <PORTMAP LOGICAL="SCK_T" PHYSICAL="emio_spi0_sclk_t"/>
            <PORTMAP LOGICAL="SS1_O" PHYSICAL="emio_spi0_ss1_o_n"/>
            <PORTMAP LOGICAL="SS2_O" PHYSICAL="emio_spi0_ss2_o_n"/>
            <PORTMAP LOGICAL="SS_I" PHYSICAL="emio_spi0_ss_i_n"/>
            <PORTMAP LOGICAL="SS_O" PHYSICAL="emio_spi0_ss_o_n"/>
            <PORTMAP LOGICAL="SS_T" PHYSICAL="emio_spi0_ss_n_t"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0x2000000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x20000003FF" INSTANCE="Base_core_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="apuAXIL"/>
      </MEMORYMAP>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="Base_core_0"/>
      </PERIPHERALS>
    </MODULE>
  </MODULES>

</EDKSYSTEM>
